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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4k 600

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

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  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.4k 214

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1k 330

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 822 221

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 731 177

Repositories

Showing 10 of 110 repositories
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 95 Apache-2.0 44 105 60 Updated Nov 23, 2024
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 1 0 0 Updated Nov 23, 2024
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 2 Apache-2.0 0 0 2 Updated Nov 23, 2024
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 297 ISC 75 45 (5 issues need help) 22 Updated Nov 23, 2024
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,007 Apache-2.0 600 314 (1 issue needs help) 169 Updated Nov 22, 2024
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 76 Apache-2.0 38 68 8 Updated Nov 22, 2024
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 119 Apache-2.0 22 16 27 Updated Nov 22, 2024
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 250 Apache-2.0 75 22 14 Updated Nov 23, 2024
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    chipsalliance/adams-bridge’s past year of commit activity
    SystemVerilog 9 Apache-2.0 1 2 0 Updated Nov 22, 2024
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 6 Apache-2.0 3 1 0 Updated Nov 22, 2024
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