libs: ahb_slv_sif: Latch hsize on address phase #502
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Accordingly to IHI0033A 3.4, HSIZE is of address bus timing. Signed-off-by: Wiktoria Kuna <[email protected]>
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This is a good fix, but will be postponed until 2.0. |
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Alrighty, thanks @calebofearth! |
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Related PR: chipsalliance/caliptra-rtl#502 Signed-off-by: Robert Szczepanski <[email protected]>
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@wkkuna we'd like to merge this Pull Request. Can you run it through any local tests you have (VCS simulation, spyglass lint, synthesis) and submit the branch stamp (described in https://github.com/chipsalliance/caliptra-rtl/blob/main/.github/workflow_metadata/README.md)? |
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Accordingly to IHI0033A 3.4,
HSIZEis of address bus timing.When two consecutive
NONSEQtransfers (say A and B) of differentHSIZEvalue are issued, the effective size of A isHSIZE(B)and effective size of B is depended on the manager implementation.