DELETE THIS -- TEST PR -- User/anjpar/caliptra ss fuse ctrl #607

nileshbpat · 2024-10-23T22:26:29Z

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… incomplete EX access)

… into user/anjpar/caliptra_ss_fuse_ctrl

… incomplete EX access)

Ready & valid are 1-bit wide, do not access using bit select / range. Signed-off-by: Wiktoria Kuna <[email protected]>

When 'r_pri' is not set, read operation should be granted only if a read 'r_dv' is pending and there's no required write action 'w_dv'. Signed-off-by: Wiktoria Kuna <[email protected]>

…AT>0; compile fixes for sram

…b; upd COV IF

… add AXI assertions

…oke tests pass

…tion

… cleanup

…flicts

…tion testbenches for both

…not used by Caliptra

… gasket

linux-foundation-easycla · 2024-10-23T22:26:36Z

✅ login: calebofearth / name: Caleb (eaca0f7, f6baa02, 3d20f62, 29bedff, 9c3343f, 9f1e954, 4536941, 65dd299, b811e1d, f5b883f, e50cda0, d467e3a, d770c8f, 5f5b0ef, 77f2378, b481ac2, 1645788, 2024d33, 5b7ca3c, a9a17f7, 0a58401, 02d9398, 1ca975a, 04276f4, 53536e0, 5ca7753, 4c8b312, 2da17e8, 38a014c, 29151a1, 2f8d8c0, d47b17b, d4582ae, 77dc50c, ed23e36, 2e8a116, 393beeb, 7e156a7, cc519b9, 886c6f2, b3e2b6c, 356de67, bce6f7e, 0f3e910, 67adfed, 854d4ac, 85c3caf, b20e46f, e9703e4)
✅ login: wkkuna (3bcc3b8, 2faf5cc)
❌ The email address for the commit (cb9d70c, c33f2f9, 424c705, e3ee607, f7474f4, 6487e08, 7ebd355, 5f61c24, e671e11) is not linked to the GitHub account, preventing the EasyCLA check. Consult this Help Article and GitHub Help to resolve. (To view the commit's email address, add .patch at the end of this PR page's URL.) For further assistance with EasyCLA, please submit a support request ticket.

calebofearth and others added 30 commits May 31, 2024 12:30

Initial pass at AXI sub -- read channel only

d770c8f

Compile for AXI sub

f6baa02

AXI sub -- write channel + exclusive access fixups

5ca7753

Exclusive access support OFF by default

5b7ca3c

Only latch err from component when the access is allowed (i.e. not an…

1645788

… incomplete EX access)

Add AXI sub wrapper and simplex arbiter

02d9398

Syntax fix

9c3343f

Add ID signal to component interface

5f5b0ef

Add component inf 'write' signal

65dd299

New handshake assertions; i/f X checks conditional upon valid signals

2024d33

Merge remote-tracking branch 'chips/cwhitehead-msft-gen2-axi-modules'…

cb9d70c

… into user/anjpar/caliptra_ss_fuse_ctrl

Initial pass at AXI sub -- read channel only

3d20f62

Compile for AXI sub

04276f4

AXI sub -- write channel + exclusive access fixups

f5b883f

Exclusive access support OFF by default

a9a17f7

Only latch err from component when the access is allowed (i.e. not an…

b481ac2

… incomplete EX access)

Add AXI sub wrapper and simplex arbiter

eaca0f7

Syntax fix

53536e0

Add ID signal to component interface

29bedff

Add component inf 'write' signal

d4582ae

New handshake assertions; i/f X checks conditional upon valid signals

d467e3a

Swap APB for AXI, replace all 'user' references with 'AXI ID'

9f1e954

axi_sub_wr: Fix rp valid/ready access

3bcc3b8

Ready & valid are 1-bit wide, do not access using bit select / range. Signed-off-by: Wiktoria Kuna <[email protected]>

axi_sub_arb: Fix arbiter read grant condition

2faf5cc

When 'r_pri' is not set, read operation should be granted only if a read 'r_dv' is pending and there's no required write action 'w_dv'. Signed-off-by: Wiktoria Kuna <[email protected]>

Remove LENB override; fix resp-pipe part-select in axi_sub_wr

e50cda0

AXI sub tb integration -- compiles and passes smoke_test_hw_config

1ca975a

Fixups to get sims working VCS + Verilator

4536941

Initial AXI DMA reg file

77f2378

Format

b811e1d

First pass - AXI DMA

0a58401

calebofearth and others added 27 commits July 25, 2024 15:22

Defaults: AW=32, DW=64

ed23e36

Mv skidbuffer to libs; add r/w error sigs in axi_sub to work with C_L…

2da17e8

…AT>0; compile fixes for sram

Syntax fix

d47b17b

Add all module inst/connections; syntax fixes for compilation

29151a1

Include DMA reg set in docs

2e8a116

Inst. DMA; connect SRAM through MBOX dir mode mux; add DMA regs in ar…

4c8b312

…b; upd COV IF

Updates for AXI DMA connections

67adfed

AW should be derived from SRAM depth

85c3caf

Add new reg fields; syntax cleanup to simulate; now passes smoke test

bce6f7e

Fix reset if-else syntax on ctx FF blocks

38a014c

Default assignment fix

b3e2b6c

TB updates to support all prev. functionality; smoke_test_dma passes;…

2f8d8c0

… add AXI assertions

Update all caliptra_isr with new DMA interrupts; fw updates so all sm…

7e156a7

…oke tests pass

Update HDL file lists

393beeb

Different init syntax for Verilator to compile vs VCS

356de67

Update smoke_test_kv_hmac_multiblock_flow w/ DMA intr to pass compila…

b20e46f

…tion

Add mailbox payload operations

886c6f2

Default return of 0 for dma operations

854d4ac

Reorder fail var assignment

cc519b9

Fixes for DMA write and hold signaling to mailbox sram

e9703e4

Fixes for credits and bytes requested calculations

0f3e910

Initial pass at Fuse Controller and Tl --> AXI replacement, pre build…

c33f2f9

… cleanup

Merged chips/cwhitehead-msft-gen2-axi-modules branch and resolved con…

424c705

…flicts

Fixed filename typo in fuse_ctrl config

e3ee607

Initial commit of AXI2TLUL gasket, fuse controller and basic verifica…

f7474f4

…tion testbenches for both

Removed lc_creator_seed_sw_rw_en, lc_owner_seed_sw_rw_en as they are …

6487e08

…not used by Caliptra

Added all dependencies for lc_ctrl, greated lc_ctrl_top with AXI2TLUL…

7ebd355

… gasket

Anjana Parthasarathy added 2 commits October 29, 2024 14:23

Initial RDL file for OTP controller

5f61c24

Otp_ctrl RDL file

e671e11

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DELETE THIS -- TEST PR -- User/anjpar/caliptra ss fuse ctrl #607

DELETE THIS -- TEST PR -- User/anjpar/caliptra ss fuse ctrl #607

nileshbpat commented Oct 23, 2024

linux-foundation-easycla bot commented Oct 23, 2024 •

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nileshbpat commented Oct 23, 2024

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