diff --git a/trunk/configs/templates/MI-R3G.config b/trunk/configs/templates/MI-R3G.config
index bb5852e39e7..362ac5e48fb 100644
--- a/trunk/configs/templates/MI-R3G.config
+++ b/trunk/configs/templates/MI-R3G.config
@@ -19,7 +19,7 @@ CONFIG_TOOLCHAIN_DIR=/opt/rt-n56u/toolchain-mipsel
 #CONFIG_FIRMWARE_TYPE_ROOTFS_IN_RAM=y
 
 ### Force MT7621 CPU clock to 900MHz (override Uboot settings)
-#CONFIG_FIRMWARE_CPU_900MHZ=y
+CONFIG_FIRMWARE_CPU_900MHZ=y
 
 ### Enable MT7621 CPU sleep mode (downclock to 220MHz on idle)
 #CONFIG_FIRMWARE_CPU_SLEEP=y
diff --git a/trunk/linux-3.4.x/arch/mips/rt2880/init.c b/trunk/linux-3.4.x/arch/mips/rt2880/init.c
index 0210ada1ca1..f3378622f7c 100644
--- a/trunk/linux-3.4.x/arch/mips/rt2880/init.c
+++ b/trunk/linux-3.4.x/arch/mips/rt2880/init.c
@@ -551,9 +551,9 @@ static void prom_init_sysclk(void)
 	case 1: /* CPU PLL */
 		reg = (*(volatile u32 *)(RALINK_MEMCTRL_BASE + 0x648));
 #if defined(CONFIG_RALINK_MT7621_PLL900)
-		if ((reg & 0xff) != 0xc2) {
-			reg &= ~(0xff);
-			reg |=  (0xc2);
+		if ((reg & 0x7ff) != 0x362) {
+			reg &= ~(0x7ff);
+			reg |=  (0x362);
 			(*((volatile u32 *)(RALINK_MEMCTRL_BASE + 0x648))) = reg;
 			udelay(10);
 		}