tuple3_0_sel0_std_logic_vector is not declared

[DigitalBrains1]

As we are separating clash-cores from clash-compiler, I tried to support not just Clash master but also Clash 1.8. But there are several cores in clash-cores that fail their test suite on Clash 1.8.1 on several GHC versions.

This issue is about the test suite for the XpmCdcHandshake core. It only fails in VHDL, Verilog works fine.

The core works fine on Clash master, and with Clash 1.8.1 it also passes the test suite on some GHC's, but on other GHC's, it gives the error below. The error below was created with GHC 9.6.6.

These combinations work fine: Clash 1.8.1 and GHC 8.10.7, 9.0.2, 9.2.8, 9.4.8.

These combinations error out: Clash 1.8.1 and GHC 9.6.6, 9.8.2.

The essence of the error message in the test suite is:

                  INFO: [VRFC 10-3107] analyzing entity 'top_4'
                  ERROR: [VRFC 10-2989] 'tuple3_0_sel0_std_logic_vector' is not declared [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:122]
                  ERROR: [VRFC 10-3220] choice is not a record element of 'tuple3' [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:122]
                  ERROR: [VRFC 10-2989] 'tuple3_0_sel1_std_logic_0' is not declared [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:123]
                  ERROR: [VRFC 10-3220] choice is not a record element of 'tuple3' [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:123]
                  ERROR: [VRFC 10-2989] 'tuple3_0_sel2_std_logic_1' is not declared [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:124]
                  ERROR: [VRFC 10-3220] choice is not a record element of 'tuple3' [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:124]
                  ERROR: [VRFC 10-3717] some record elements are missing in this aggregate of 'tuple3' [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:122]

Full Vivado error message

              Vivado
                sim tb0: FAIL (12.83s)
                  Program /opt/tools/Xilinx/Vivado/2022.1/bin/vivado exited with code 1, but we expected 0.
                  
                  Stderr was:
                  ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/t
mp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/project/sim.sim/sim_1/behav/xsim/xvhdl.log' file for more in
formation.
                  ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry 
this operation.
                  
                  
                  Stdout was:
                  
                  ****** Vivado v2022.1 (64-bit)
                    **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
                    **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
                      ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
                  
                  INFO: [Common 17-1239] XILINX_LOCAL_USER_DATA is set to 'no'.
                  source /tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/sim.tcl
                  # set_msg_config -severity {CRITICAL WARNING} -new_severity ERROR
                  # source -notrace {/home/peter/.cabal/store/ghc-9.6.6/clash-lib-1.8.1-a980c3342dd29a956782a229a850f6
f75599e5c8a2dd0514e3cf8f1656ba737e/share/data-files/tcl/clashConnector.tcl}
                  # clash::readMetadata {/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.t
b0/}
                  Clash [1]: New top component: tb0
                  Clash [1]: Top entity is tb0
                  # clash::createAndReadIp -dir ip
                  # clash::readHdl
                  # set_property TOP $clash::topEntity [current_fileset -sim]
                  # set_property -name xsim.elaborate.xelab.more_options -value {-L xpm} -objects [current_fileset -si
m]
                  # save_project_as sim project -force
                  # set_property RUNTIME all [current_fileset -sim]
                  # launch_simulation
                  Command: launch_simulation 
                  INFO: [Vivado 12-12493] Simulation top is 'tb0'
                  WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
                  INFO: [Vivado 12-5682] Launching behavioral simulation in '/tmp/clash-test_XpmCdcHandshake-63504bdaf
2d95229/vivado-tb0/project/sim.sim/sim_1/behav/xsim'
                  INFO: [SIM-utils-51] Simulation object is 'sim_1'
                  INFO: [SIM-utils-72] Using boost library from '/opt/tools/Xilinx/Vivado/2022.1/tps/boost_1_72_0'
                  INFO: [USF-XSim-7] Finding pre-compiled libraries...
                  INFO: [USF-XSim-11] File '/opt/tools/Xilinx/Vivado/2022.1/data/xsim/xsim.ini' copied to run dir:'/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/project/sim.sim/sim_1/behav/xsim'
                  INFO: [SIM-utils-54] Inspecting design source files for 'tb0' in fileset 'sim_1'...
                  INFO: [USF-XSim-97] Finding global include files...
                  INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
                  INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
                  INFO: [USF-XSim-2] XSim::Compile design
                  INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/project/sim.sim/sim_1/behav/xsim'
                  xvlog --incr --relax -prj tb0_vlog.prj
                  INFO: [VRFC 10-2263] Analyzing Verilog file "/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/project/sim.sim/sim_1/behav/xsim/glbl.v" into library tb0
                  INFO: [VRFC 10-311] analyzing module glbl
                  xvhdl --incr --relax -prj tb0_vhdl.prj
                  INFO: [VRFC 10-163] Analyzing VHDL file "/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/tb0_slv2string_B426B45701B03559.vhdl" into library tb0
                  INFO: [VRFC 10-163] Analyzing VHDL file "/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/XpmCdcHandshake_tb0_types.vhdl" into library tb0
                  INFO: [VRFC 10-163] Analyzing VHDL file "/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/dstFsm_4.vhdl" into library tb0
                  INFO: [VRFC 10-3107] analyzing entity 'dstFsm_4'
                  INFO: [VRFC 10-163] Analyzing VHDL file "/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/srcFsm_4.vhdl" into library tb0
                  INFO: [VRFC 10-3107] analyzing entity 'srcFsm_4'
                  INFO: [VRFC 10-163] Analyzing VHDL file "/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl" into library tb0
                  INFO: [VRFC 10-3107] analyzing entity 'top_4'
                  ERROR: [VRFC 10-2989] 'tuple3_0_sel0_std_logic_vector' is not declared [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:122]
                  ERROR: [VRFC 10-3220] choice is not a record element of 'tuple3' [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:122]
                  ERROR: [VRFC 10-2989] 'tuple3_0_sel1_std_logic_0' is not declared [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:123]
                  ERROR: [VRFC 10-3220] choice is not a record element of 'tuple3' [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:123]
                  ERROR: [VRFC 10-2989] 'tuple3_0_sel2_std_logic_1' is not declared [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:124]
                  ERROR: [VRFC 10-3220] choice is not a record element of 'tuple3' [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:124]
                  ERROR: [VRFC 10-3717] some record elements are missing in this aggregate of 'tuple3' [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:122]
                  ERROR: [VRFC 10-9458] unit 'structural' is ignored due to previous errors [/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl:20]
                  INFO: [VRFC 10-8704] VHDL file '/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/XpmCdcHandshake.tb0/top_4.vhdl' is ignored due to errors
                  INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
                  INFO: [USF-XSim-99] Step results log file:'/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/project/sim.sim/sim_1/behav/xsim/xvhdl.log'
                  ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
                  
                      while executing
                  "launch_simulation"
                      (file "/tmp/clash-test_XpmCdcHandshake-63504bdaf2d95229/vivado-tb0/sim.tcl" line 10)
                  INFO: [Common 17-206] Exiting Vivado at Sat Sep  7 11:41:17 2024...
                  
                  Use -p '/XpmCdcHandshake/&&/VHDL.tools.Vivado.sim tb0/' to rerun this test only.

An easy to work with repository can be found at clash-cores repro-1.8-issues. You can just do cabal run clash-cores-test-suite -- -p XpmCdcHandshake.VHDL (although investigating the bug obviously needs more).