From 365ac2f182f9fa0813183143d89aa5269e2195e7 Mon Sep 17 00:00:00 2001 From: RoboSchmied Date: Sat, 6 Apr 2024 06:02:39 +0200 Subject: [PATCH] Fix: 58 typos Signed-off-by: RoboSchmied --- core/net/ip/uipopt.h | 2 +- cpu/arm/aducrf101/Common/ADuCRF101.h | 10 +++++----- cpu/arm/common/CMSIS/core_cm0.h | 4 ++-- cpu/arm/common/CMSIS/core_cm0plus.h | 4 ++-- cpu/arm/common/CMSIS/core_cm3.h | 4 ++-- cpu/arm/common/CMSIS/core_cm4.h | 4 ++-- cpu/arm/common/CMSIS/core_cm7.h | 4 ++-- cpu/arm/common/CMSIS/core_sc000.h | 4 ++-- cpu/arm/common/CMSIS/core_sc300.h | 4 ++-- cpu/arm/common/SD-card/config.h | 2 +- cpu/arm/stm32f103/stm32f10x_map.h | 2 +- cpu/arm/stm32l152/regs.h | 10 +++++----- cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h | 10 +++++----- .../org/contikios/cooja/mote/memory/MemoryBuffer.java | 4 ++-- .../org/contikios/cooja/mote/memory/MemoryLayout.java | 6 +++--- 15 files changed, 37 insertions(+), 37 deletions(-) diff --git a/core/net/ip/uipopt.h b/core/net/ip/uipopt.h index 7a523b254e8..ac68e145b58 100644 --- a/core/net/ip/uipopt.h +++ b/core/net/ip/uipopt.h @@ -598,7 +598,7 @@ void uip_log(char *msg); * \defgroup uipoptcpu CPU architecture configuration * @{ * - * The CPU architecture configuration is where the endianess of the + * The CPU architecture configuration is where the endianness of the * CPU on which uIP is to be run is specified. Most CPUs today are * little endian, and the most notable exception are the Motorolas * which are big endian. The BYTE_ORDER macro should be changed to diff --git a/cpu/arm/aducrf101/Common/ADuCRF101.h b/cpu/arm/aducrf101/Common/ADuCRF101.h index 1e28f5cfb97..500175de2a5 100644 --- a/cpu/arm/aducrf101/Common/ADuCRF101.h +++ b/cpu/arm/aducrf101/Common/ADuCRF101.h @@ -7375,11 +7375,11 @@ typedef struct { /*!< pADI_INTERRUPT Structure /* AIRCR[VECTKEYSTAT] - Reads as 0xFA05 */ #define AIRCR_VECTKEYSTAT_MSK (0xFFFF << 16 ) -/* AIRCR[ENDIANESS] - This bit is static or configured by a hardware input on reset */ -#define AIRCR_ENDIANESS_MSK (0x1 << 15 ) -#define AIRCR_ENDIANESS (0x1 << 15 ) -#define AIRCR_ENDIANESS_DIS (0x0 << 15 ) /* DIS */ -#define AIRCR_ENDIANESS_EN (0x1 << 15 ) /* EN */ +/* AIRCR[ENDIANNESS] - This bit is static or configured by a hardware input on reset */ +#define AIRCR_ENDIANNESS_MSK (0x1 << 15 ) +#define AIRCR_ENDIANNESS (0x1 << 15 ) +#define AIRCR_ENDIANNESS_DIS (0x0 << 15 ) /* DIS */ +#define AIRCR_ENDIANNESS_EN (0x1 << 15 ) /* EN */ /* AIRCR[PRIGROUP] - Priority grouping position */ #define AIRCR_PRIGROUP_MSK (0x7 << 8 ) diff --git a/cpu/arm/common/CMSIS/core_cm0.h b/cpu/arm/common/CMSIS/core_cm0.h index 1ce68357613..4bc826e550f 100644 --- a/cpu/arm/common/CMSIS/core_cm0.h +++ b/cpu/arm/common/CMSIS/core_cm0.h @@ -450,8 +450,8 @@ typedef struct #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ diff --git a/cpu/arm/common/CMSIS/core_cm0plus.h b/cpu/arm/common/CMSIS/core_cm0plus.h index 8dc698a9af6..baddb4876e7 100644 --- a/cpu/arm/common/CMSIS/core_cm0plus.h +++ b/cpu/arm/common/CMSIS/core_cm0plus.h @@ -474,8 +474,8 @@ typedef struct #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ diff --git a/cpu/arm/common/CMSIS/core_cm3.h b/cpu/arm/common/CMSIS/core_cm3.h index de111368848..15ca67e098b 100644 --- a/cpu/arm/common/CMSIS/core_cm3.h +++ b/cpu/arm/common/CMSIS/core_cm3.h @@ -505,8 +505,8 @@ typedef struct #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ diff --git a/cpu/arm/common/CMSIS/core_cm4.h b/cpu/arm/common/CMSIS/core_cm4.h index 218bc0dfac3..f82b54c3d4b 100644 --- a/cpu/arm/common/CMSIS/core_cm4.h +++ b/cpu/arm/common/CMSIS/core_cm4.h @@ -565,8 +565,8 @@ typedef struct #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ diff --git a/cpu/arm/common/CMSIS/core_cm7.h b/cpu/arm/common/CMSIS/core_cm7.h index 1c1a5e68f36..3ce8013b634 100644 --- a/cpu/arm/common/CMSIS/core_cm7.h +++ b/cpu/arm/common/CMSIS/core_cm7.h @@ -609,8 +609,8 @@ typedef struct #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ diff --git a/cpu/arm/common/CMSIS/core_sc000.h b/cpu/arm/common/CMSIS/core_sc000.h index 514dbd81b9f..95e71455682 100644 --- a/cpu/arm/common/CMSIS/core_sc000.h +++ b/cpu/arm/common/CMSIS/core_sc000.h @@ -462,8 +462,8 @@ typedef struct #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ diff --git a/cpu/arm/common/CMSIS/core_sc300.h b/cpu/arm/common/CMSIS/core_sc300.h index 8bd18aa318a..bae5c5f6f4c 100644 --- a/cpu/arm/common/CMSIS/core_sc300.h +++ b/cpu/arm/common/CMSIS/core_sc300.h @@ -502,8 +502,8 @@ typedef struct #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ diff --git a/cpu/arm/common/SD-card/config.h b/cpu/arm/common/SD-card/config.h index d942669cedf..16a3c7d07bd 100644 --- a/cpu/arm/common/SD-card/config.h +++ b/cpu/arm/common/SD-card/config.h @@ -53,7 +53,7 @@ #define CLUSTER_PREALLOC_DIRECTORY 0 -/* Endianess configuration +/* Endianness configuration ----------------------- * Here you can configure wheter your architecture is little or big endian. This diff --git a/cpu/arm/stm32f103/stm32f10x_map.h b/cpu/arm/stm32f103/stm32f10x_map.h index d3dec163399..4d74611aace 100644 --- a/cpu/arm/stm32f103/stm32f10x_map.h +++ b/cpu/arm/stm32f103/stm32f10x_map.h @@ -2573,7 +2573,7 @@ typedef struct #define SCB_AIRCR_PRIGROUP6 ((u32)0x00000600) /* Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ #define SCB_AIRCR_PRIGROUP7 ((u32)0x00000700) /* Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ -#define SCB_AIRCR_ENDIANESS ((u32)0x00008000) /* Data endianness bit */ +#define SCB_AIRCR_ENDIANNESS ((u32)0x00008000) /* Data endianness bit */ #define SCB_AIRCR_VECTKEY ((u32)0xFFFF0000) /* Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ diff --git a/cpu/arm/stm32l152/regs.h b/cpu/arm/stm32l152/regs.h index 6d80c3622ee..fcfde2a9896 100644 --- a/cpu/arm/stm32l152/regs.h +++ b/cpu/arm/stm32l152/regs.h @@ -9989,11 +9989,11 @@ #define SCS_AIRCR_VECTKEY_MASK (0xFFFF0000u) #define SCS_AIRCR_VECTKEY_BIT (16) #define SCS_AIRCR_VECTKEY_BITS (16) -/* ENDIANESS field */ -#define SCS_AIRCR_ENDIANESS (0x00008000u) -#define SCS_AIRCR_ENDIANESS_MASK (0x00008000u) -#define SCS_AIRCR_ENDIANESS_BIT (15) -#define SCS_AIRCR_ENDIANESS_BITS (1) +/* ENDIANNESS field */ +#define SCS_AIRCR_ENDIANNESS (0x00008000u) +#define SCS_AIRCR_ENDIANNESS_MASK (0x00008000u) +#define SCS_AIRCR_ENDIANNESS_BIT (15) +#define SCS_AIRCR_ENDIANNESS_BITS (1) /* PRIGROUP field */ #define SCS_AIRCR_PRIGROUP (0x00000700u) #define SCS_AIRCR_PRIGROUP_MASK (0x00000700u) diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h index 5c60f682af9..3b383cfc6de 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h @@ -9959,11 +9959,11 @@ #define SCS_AIRCR_VECTKEY_MASK (0xFFFF0000u) #define SCS_AIRCR_VECTKEY_BIT (16) #define SCS_AIRCR_VECTKEY_BITS (16) - /* ENDIANESS field */ - #define SCS_AIRCR_ENDIANESS (0x00008000u) - #define SCS_AIRCR_ENDIANESS_MASK (0x00008000u) - #define SCS_AIRCR_ENDIANESS_BIT (15) - #define SCS_AIRCR_ENDIANESS_BITS (1) + /* ENDIANNESS field */ + #define SCS_AIRCR_ENDIANNESS (0x00008000u) + #define SCS_AIRCR_ENDIANNESS_MASK (0x00008000u) + #define SCS_AIRCR_ENDIANNESS_BIT (15) + #define SCS_AIRCR_ENDIANNESS_BITS (1) /* PRIGROUP field */ #define SCS_AIRCR_PRIGROUP (0x00000700u) #define SCS_AIRCR_PRIGROUP_MASK (0x00000700u) diff --git a/tools/cooja/java/org/contikios/cooja/mote/memory/MemoryBuffer.java b/tools/cooja/java/org/contikios/cooja/mote/memory/MemoryBuffer.java index 4f645a2e048..5ef30374546 100644 --- a/tools/cooja/java/org/contikios/cooja/mote/memory/MemoryBuffer.java +++ b/tools/cooja/java/org/contikios/cooja/mote/memory/MemoryBuffer.java @@ -34,7 +34,7 @@ /** * Basic routines for memory access with multi-arch support. * - * Handles endianess, integer size and address size. + * Handles endianness, integer size and address size. * * Supports padding/aligning. * @@ -85,7 +85,7 @@ public static MemoryBuffer wrap(MemoryLayout layout, byte[] array) { */ public static MemoryBuffer wrap(MemoryLayout layout, byte[] array, DataType[] structure) { ByteBuffer b = ByteBuffer.wrap(array); - b.order(layout.order); // preset endianess + b.order(layout.order); // preset endianness return new MemoryBuffer(layout, b, structure); } diff --git a/tools/cooja/java/org/contikios/cooja/mote/memory/MemoryLayout.java b/tools/cooja/java/org/contikios/cooja/mote/memory/MemoryLayout.java index 132af62d059..5a9eda91fe0 100644 --- a/tools/cooja/java/org/contikios/cooja/mote/memory/MemoryLayout.java +++ b/tools/cooja/java/org/contikios/cooja/mote/memory/MemoryLayout.java @@ -32,7 +32,7 @@ import java.nio.ByteOrder; /** - * Holds memory layout informations such as endianess, wordsize, C int size. + * Holds memory layout informations such as endianness, wordsize, C int size. * * @author Enrico Jorns */ @@ -174,13 +174,13 @@ public int getPaddingBytesFor(DataType currType, DataType nextType) { /** * Returns information string for this MemoryLayout. * - * @return String that shows Endianess and word size. + * @return String that shows Endianness and word size. */ @Override public String toString() { StringBuilder sb = new StringBuilder(); return sb.append("MemoryLayout: ") - .append("Endianess: ").append(order) + .append("Endianness: ").append(order) .append(", WORD_SIZE: ").append(WORD_SIZE) .toString(); }