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Investigate proper handling when ERL bit is set #10

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vhotspur opened this issue Jan 17, 2020 · 0 comments

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vhotspur commented Jan 17, 2020

There seems to be a difference in handling translations between virtual and physical addresses in MSIM 1.3.8.5 and current HEAD when ERL bit is set.

Not yet sure which version behaves correctly, perhaps the old MSIM treats the condition for Cache error and ERL=1 for any exception.

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