v2.3.1

Fixed

• Wrong formatting of virtual address in the result of tr and str (see #71, @HanyzPAPU)
• Propagate error when ddisk cannot write to a file (see #63, @PeterHero)

v2.3.0

Fixed

• wrong break documentation (see #55 and #56, @KronwarsCZ, @vhotspur)
• RISC-V executing from paged memory in M-mode (see #66, @HanyzPAPU)

Added

• setup C style (via .clang-format) (see #51, @vhotspur)
• CI checks C style as well as file encoding and line-endings (see #51, @vhotspur)
• completion for add prints available devices (see #31, @vhotspur)
• page table dumping commands ptd and sptd (see #67, @HanyzPAPU)
• virtual address translation commands tr and str (see #67, @HanyzPAPU)

Changed

• renamed RISC-V CPU commands (see #60, @HanyzPAPU)
  • csrrd is csrd, tlbrd is tlbd
• csrd dumps selected registers only (see #61, @HanyzPAPU)

v2.2.1

Fixed

• ebuild recipe (thx MFF sysadmins)
• RISC-V TLB documentation (@vhotspur, @HanyzPAPU)
• ReadTheDocs configuration (@vhotspur)

Changed

• EBREAK instruction on RISC-V halts simulation without TTY (as is done on MIPS) (@vhotspur)
• move changelog to a more structured format (@vhotspur)

v2.2.0

Release 2.2.0

v2.1.2

Release 2.1.2

v2.1.1

Release 2.1.1

v2.1.0

• Documentation moved to https://msim.readthedocs.io/
• Add simulated TLB for RISC-V (PR #36)

v2.0.0

Release 2.0.0 brought support of RISC-V processor to MSIM. See pull request #25 for the patch by Jan Papesch that made it possible.