v1.2.1

Updates and fixes to HBM support for Xilinx FPGAs.

v1.2.0

First release with support for HBM on the Xilinx Alveo U280 FPGA by using a new interface for allocation, which requires both the type of memory to use (DDR/HBM) and the bank number (0-31).

v1.1.1

Last tag that might support pre-Vitis devices (many things might already have broken, since we haven't tested pre-Vitis SDAccel or SDX for a while). Past this tag, only the Vitis-based build flow is intended to be supported (some components might work by accident).

v1.1.0

• The previously deprecated FindSDAccel.cmake has been removed.
• The Xilinx header SDAccel.h has been deprecated in favor of OpenCL.h.
• Dataflow functions can now be nested.
• Including hlslib as a subproject now exposes Xilinx and Intel headers and libraries in the interface, if found.
• If not built as the primary project, documentation and tests will not be built.
• std::vector<T> was replaced with std::unique_ptr<T[]> for Xilinx simulation to avoid issues with std::vector<bool>.
• FindVitis.cmake now exposes the platforminfo binary that can be used to query the device used by Vitis platforms.
• Assorted minor fixes.

v1.0.0

First "official" release of hlslib, coinciding with implementing support for Vitis 2020.1.
It is still recommended to use the head of master to gain quick access to bug fixes.