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ixgbe.diff
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ixgbe.diff
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Index: ./dev/pci/files.pci
===================================================================
RCS file: /cvs/src/sys/dev/pci/files.pci,v
retrieving revision 1.333
diff -u -p -r1.333 files.pci
--- ./dev/pci/files.pci 24 Dec 2017 19:50:56 -0000 1.333
+++ ./dev/pci/files.pci 17 Sep 2018 19:59:54 -0000
@@ -355,6 +355,7 @@ device ix: ether, ifnet, ifmedia
attach ix at pci
file dev/pci/if_ix.c ix
file dev/pci/ixgbe.c ix
+file dev/pci/ixgbe_api.c ix
file dev/pci/ixgbe_82598.c ix
file dev/pci/ixgbe_82599.c ix
file dev/pci/ixgbe_x540.c ix
Index: ./dev/pci/if_ix.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_ix.c,v
retrieving revision 1.152
diff -u -p -r1.152 if_ix.c
--- ./dev/pci/if_ix.c 22 Jun 2017 02:44:37 -0000 1.152
+++ ./dev/pci/if_ix.c 17 Sep 2018 19:59:55 -0000
@@ -85,6 +85,8 @@ const struct pci_matchid ixgbe_devices[]
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X550EM_X_SFP },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X550EM_X_10G_T },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X550EM_X_1G_T },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X550EM_A_SFP_N },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X550EM_A_SFP }
};
/*********************************************************************
@@ -141,6 +143,7 @@ void ixgbe_iff(struct ix_softc *);
void ixgbe_print_hw_stats(struct ix_softc *);
#endif
void ixgbe_update_link_status(struct ix_softc *);
+void ixgbe_config_dmac(struct ix_softc *adapter);
int ixgbe_get_buf(struct rx_ring *, int);
int ixgbe_encap(struct tx_ring *, struct mbuf *);
int ixgbe_dma_malloc(struct ix_softc *, bus_size_t,
@@ -305,6 +308,13 @@ ixgbe_attach(struct device *parent, stru
/* Get the PCI-E bus info and determine LAN ID */
hw->mac.ops.get_bus_info(hw);
+ /* Enable EEE power saving */
+ if (sc->feat_en & IXGBE_FEATURE_EEE)
+ printf("unsupported IXGBE_FEATURE_EEE");
+ // hw->mac.ops.setup_eee(hw, TRUE);
+ if (sc->feat_en & IXGBE_FEATURE_MSIX)
+ printf("unsupported IXGBE_FEATURE_MSIX");
+
/* Set an initial default flow control value */
sc->fc = ixgbe_fc_full;
@@ -705,6 +715,9 @@ ixgbe_init(void *arg)
/* Set up VLAN support and filter */
ixgbe_setup_vlan_hw_support(sc);
+ /* 4.0 move that after // Setup DMA Coalescing */
+ // ixgbe_config_dmac(sc);
+
/* Enable Receive engine */
rxctrl = IXGBE_READ_REG(&sc->hw, IXGBE_RXCTRL);
if (sc->hw.mac.type == ixgbe_mac_82598EB)
@@ -712,6 +725,7 @@ ixgbe_init(void *arg)
rxctrl |= IXGBE_RXCTRL_RXEN;
sc->hw.mac.ops.enable_rx_dma(&sc->hw, rxctrl);
+ // callout_reset(&adapter->timer, hz, ixgbe_local_timer, adapter);
timeout_add_sec(&sc->timer, 1);
/* Set up MSI/X routing */
@@ -759,9 +773,19 @@ ixgbe_init(void *arg)
/* Initialize the FC settings */
sc->hw.mac.ops.start_hw(&sc->hw);
+ /* 4.0 Setup DMA Coalescing * must be done on link speed*/
+ ixgbe_config_dmac(sc);
+
/* And now turn on interrupts */
ixgbe_enable_intr(sc);
+ /* 4.0 Enable the use of the MBX by the VF's */
+ //if (adapter->feat_en & IXGBE_FEATURE_SRIOV) {
+ // ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
+ // ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
+ // IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
+ //}
+
/* Now inform the stack we're ready */
ifp->if_flags |= IFF_RUNNING;
ifq_clr_oactive(&ifp->if_snd);
@@ -777,9 +801,10 @@ ixgbe_config_gpie(struct ix_softc *sc)
gpie = IXGBE_READ_REG(&sc->hw, IXGBE_GPIE);
- /* Fan Failure Interrupt */
- if (hw->device_id == IXGBE_DEV_ID_82598AT)
+ if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) {
+ /* Fan Failure Interrupt */
gpie |= IXGBE_SDP1_GPIEN;
+ }
if (sc->hw.mac.type == ixgbe_mac_82599EB) {
/* Add for Module detection */
@@ -796,7 +821,16 @@ ixgbe_config_gpie(struct ix_softc *sc)
gpie |= 0xf << IXGBE_GPIE_LLI_DELAY_SHIFT;
}
+ /* 4.0 */
+ if (sc->hw.mac.type == ixgbe_mac_X550EM_x ||
+ sc->hw.mac.type == ixgbe_mac_X550EM_a )
+ {
+ gpie |= IXGBE_SDP0_GPIEN_X540;
+ }
+
if (sc->hw.mac.type == ixgbe_mac_X540 ||
+ hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
+ hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N ||
hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
/*
@@ -812,6 +846,7 @@ ixgbe_config_gpie(struct ix_softc *sc)
gpie |= 0xf << IXGBE_GPIE_LLI_DELAY_SHIFT;
}
+
if (sc->msix > 1) {
/* Enable Enhanced MSIX mode */
gpie |= IXGBE_GPIE_MSIX_MODE;
@@ -838,6 +873,7 @@ ixgbe_config_delay_values(struct ix_soft
case ixgbe_mac_X540:
case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x:
+ case ixgbe_mac_X550EM_a: /* 4.0 */
tmp = IXGBE_DV_X540(frame, frame);
break;
default:
@@ -853,6 +889,7 @@ ixgbe_config_delay_values(struct ix_soft
case ixgbe_mac_X540:
case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x:
+ case ixgbe_mac_X550EM_a: /* 4.0 */
tmp = IXGBE_LOW_DV_X540(frame);
break;
default:
@@ -866,27 +903,6 @@ ixgbe_config_delay_values(struct ix_soft
hw->fc.send_xon = TRUE;
}
-/*
- * MSIX Interrupt Handlers
- */
-void
-ixgbe_enable_queue(struct ix_softc *sc, uint32_t vector)
-{
- uint64_t queue = 1ULL << vector;
- uint32_t mask;
-
- if (sc->hw.mac.type == ixgbe_mac_82598EB) {
- mask = (IXGBE_EIMS_RTX_QUEUE & queue);
- IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS, mask);
- } else {
- mask = (queue & 0xFFFFFFFF);
- if (mask)
- IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS_EX(0), mask);
- mask = (queue >> 32);
- if (mask)
- IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS_EX(1), mask);
- }
-}
void
ixgbe_disable_queue(struct ix_softc *sc, uint32_t vector)
@@ -998,7 +1014,8 @@ ixgbe_intr(void *arg)
}
/* Check for fan failure */
- if ((hw->device_id == IXGBE_DEV_ID_82598AT) &&
+ if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL &&
+ (hw->device_id == IXGBE_DEV_ID_82598AT) &&
(reg_eicr & IXGBE_EICR_GPI_SDP1)) {
printf("%s: CRITICAL: FAN FAILURE!! "
"REPLACE IMMEDIATELY!!\n", ifp->if_xname);
@@ -1371,6 +1388,17 @@ ixgbe_update_link_status(struct ix_softc
/* Update any Flow Control changes */
sc->hw.mac.ops.fc_enable(&sc->hw);
+ } else {
+ //if (sc->link_speed == IXGBE_LINK_SPEED_10GB_FULL){
+ /*
+ * Discard count for both MAC Local Fault and
+ * Remote Fault because those registers are
+ * valid only when the link speed is up and
+ * 10Gbps.
+ */
+ // IXGBE_READ_REG(hw, IXGBE_MLFC);
+ // IXGBE_READ_REG(hw, IXGBE_MRFC);
+ //
}
if (ifp->if_link_state != link_state) {
ifp->if_link_state = link_state;
@@ -1378,6 +1406,32 @@ ixgbe_update_link_status(struct ix_softc
}
}
+/************************************************************************
+ * ixgbe_config_dmac - Configure DMA Coalescing Driver 4.0v
+ ************************************************************************/
+void
+ixgbe_config_dmac(struct ix_softc *adapter)
+{
+ struct ixgbe_hw *hw = &adapter->hw;
+ struct ixgbe_dmac_config *dcfg = &hw->mac.dmac_config;
+
+ if (hw->mac.type < ixgbe_mac_X550 || !hw->mac.ops.dmac_config)
+ return;
+
+ if (dcfg->watchdog_timer ^ adapter->dmac ||
+ dcfg->link_speed ^ adapter->link_speed) {
+ dcfg->watchdog_timer = adapter->dmac;
+ dcfg->fcoe_en = false;
+ dcfg->link_speed = adapter->link_speed;
+ dcfg->num_tcs = 1;
+
+ INIT_DEBUGOUT2("dmac settings: watchdog %d, link speed %d\n",
+ dcfg->watchdog_timer, dcfg->link_speed);
+
+ hw->mac.ops.dmac_config(hw);
+ }
+} /* ixgbe_config_dmac */
+
/*********************************************************************
*
@@ -2041,6 +2095,9 @@ ixgbe_initialize_transmit_units(struct i
IXGBE_WRITE_REG(hw, IXGBE_TDH(i), 0);
IXGBE_WRITE_REG(hw, IXGBE_TDT(i), 0);
+ /* 4.0 Cache the tail address */
+ txr->tail = IXGBE_TDT(txr->me);
+
/* Setup Transmit Descriptor Cmd Settings */
txr->txd_cmd = IXGBE_TXD_CMD_IFCS;
txr->queue_status = IXGBE_QUEUE_IDLE;
@@ -2653,7 +2710,8 @@ ixgbe_initialize_receive_units(struct ix
bufsz = (sc->rx_mbuf_sz - ETHER_ALIGN) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
for (i = 0; i < sc->num_queues; i++, rxr++) {
- uint64_t rdba = rxr->rxdma.dma_map->dm_segs[0].ds_addr;
+ uint64_t rdba = rxr->rxdma.dma_map->dm_segs[0].ds_addr; //netbsd rxr->rxdma.dma_paddr;
+ uint64_t reg;
/* Setup the Base and Length of the Rx Descriptor Ring */
IXGBE_WRITE_REG(hw, IXGBE_RDBAL(i),
@@ -2666,9 +2724,18 @@ ixgbe_initialize_receive_units(struct ix
srrctl = bufsz | IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(i), srrctl);
+ /* 4.0 Set RQSMR (Receive Queue Statistic Mapping) register */
+ reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i / 4));
+ reg &= ~(0x000000ff << (i % 4 * 8));
+ reg |= i << (i % 4 * 8);
+ IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i / 4), reg);
+
/* Setup the HW Rx Head and Tail Descriptor Pointers */
IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
+
+ /* 4.0 Set the driver rx tail address */
+ rxr->tail = IXGBE_RDT(rxr->me);
}
if (sc->hw.mac.type != ixgbe_mac_82598EB) {
@@ -2682,10 +2749,10 @@ ixgbe_initialize_receive_units(struct ix
rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
rxcsum &= ~IXGBE_RXCSUM_PCSD;
+
+ ixgbe_initialize_rss_mapping(sc); /*4.0 driver always call that check feature ? */
/* Setup RSS */
if (sc->num_queues > 1) {
- ixgbe_initialize_rss_mapping(sc);
-
/* RSS and RX IPP Checksum are mutually exclusive */
rxcsum |= IXGBE_RXCSUM_PCSD;
}
@@ -2703,6 +2770,7 @@ ixgbe_initialize_rss_mapping(struct ix_s
struct ixgbe_hw *hw = &sc->hw;
uint32_t reta = 0, mrqc, rss_key[10];
int i, j, queue_id, table_size, index_mult;
+ uint32_t rss_hash_config;
/* set up random bits */
arc4random_buf(&rss_key, sizeof(rss_key));
@@ -2716,6 +2784,7 @@ ixgbe_initialize_rss_mapping(struct ix_s
break;
case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x:
+ case ixgbe_mac_X550EM_a: /* 4.0 */
table_size = 512;
break;
default:
@@ -2725,7 +2794,19 @@ ixgbe_initialize_rss_mapping(struct ix_s
/* Set up the redirection table */
for (i = 0, j = 0; i < table_size; i++, j++) {
if (j == sc->num_queues) j = 0;
- queue_id = (j * index_mult);
+ if (sc->feat_en & IXGBE_FEATURE_RSS) {
+ printf("4.0 ixgbe driver case");
+ /*
+ * Fetch the RSS bucket id for the given indirection
+ * entry. Cap it at the number of configured buckets
+ * (which is num_queues.)
+ * queue_id = rss_get_indirection_to_bucket(i); DEFINE at 0 ...
+ * queue_id = queue_id % adapter->num_queues;
+ */
+ queue_id = 0;
+ } else {
+ queue_id = (j * index_mult);
+ }
/*
* The low 8 bits are for hash value (n+0);
* The next 8 bits are for hash value (n+1), etc.
@@ -2746,6 +2827,8 @@ ixgbe_initialize_rss_mapping(struct ix_s
for (i = 0; i < 10; i++)
IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), rss_key[i]);
+ if (sc->feat_en & IXGBE_FEATURE_RSS)
+ rss_hash_config = 0x7E; /*4.0 rss_gethashconfig*/
/*
* Disable UDP - IP fragments aren't currently being handled
* and so we end up with a mix of 2-tuple and 4-tuple
@@ -2759,6 +2842,31 @@ ixgbe_initialize_rss_mapping(struct ix_s
| IXGBE_MRQC_RSS_FIELD_IPV6
| IXGBE_MRQC_RSS_FIELD_IPV6_TCP
;
+
+ /* 4.0 ixgbe_get_mrqc , reenable if IXGBE_FEATURE_RSS*//*
+ if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4)
+ mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
+ if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6)
+ mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
+ if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6_EX)
+ mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;*/
+ /* 4.0 ixgbe_get_mrqc *//*
+ switch (sc->iov_mode) {
+ case IXGBE_64_VM:
+ mrqc |= IXGBE_MRQC_VMDQRSS64EN;
+ break;
+ case IXGBE_32_VM:
+ mrqc |= IXGBE_MRQC_VMDQRSS32EN;
+ break;
+ case IXGBE_NO_VM:
+ mrqc |= 0;
+ break;
+ default:
+ panic("Unexpected SR-IOV mode %d", sc->iov_mode);
+ }
+ */
+ /* e 4.0 */
+
IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
}
@@ -3030,6 +3138,59 @@ ixgbe_setup_vlan_hw_support(struct ix_so
}
}
+
+/*
+ * MSIX Interrupt Handlers
+ */
+void
+ixgbe_enable_queue(struct ix_softc *sc, uint32_t vector)
+{
+ uint64_t queue = 1ULL << vector;
+ uint32_t mask;
+
+ if (sc->hw.mac.type == ixgbe_mac_82598EB) {
+ mask = (IXGBE_EIMS_RTX_QUEUE & queue);
+ IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS, mask);
+ } else {
+ mask = (queue & 0xFFFFFFFF);
+ if (mask)
+ IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS_EX(0), mask);
+ mask = (queue >> 32);
+ if (mask)
+ IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS_EX(1), mask);
+ }
+}
+/*v4.0 openbsd code
+
+#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
+
+void
+ixgbe_enable_queue(struct adapter *adapter, u32 vector)
+{
+ struct ixgbe_hw *hw = &adapter->hw;
+ struct ix_queue *que = &adapter->queues[vector];
+ u64 queue = (u64)(1ULL << vector);
+ u32 mask;
+
+ mutex_enter(&que->dc_mtx);
+ if (que->disabled_count > 0 && --que->disabled_count > 0)
+ goto out;
+
+ if (hw->mac.type == ixgbe_mac_82598EB) {
+ mask = (IXGBE_EIMS_RTX_QUEUE & queue);
+ IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
+ } else {
+ mask = (queue & 0xFFFFFFFF);
+ if (mask)
+ IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
+ mask = (queue >> 32);
+ if (mask)
+ IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
+ }
+out:
+ mutex_exit(&que->dc_mtx);
+} ixgbe_enable_queue */
+
void
ixgbe_enable_intr(struct ix_softc *sc)
{
@@ -3040,8 +3201,9 @@ ixgbe_enable_intr(struct ix_softc *sc)
mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
/* Enable Fan Failure detection */
- if (hw->device_id == IXGBE_DEV_ID_82598AT)
- mask |= IXGBE_EIMS_GPI_SDP1;
+ if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) {
+ mask |= IXGBE_EIMS_GPI_SDP1;
+ }
switch (sc->hw.mac.type) {
case ixgbe_mac_82599EB:
@@ -3061,6 +3223,7 @@ ixgbe_enable_intr(struct ix_softc *sc)
break;
case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x:
+ case ixgbe_mac_X550EM_a:
mask |= IXGBE_EIMS_ECC;
/* MAC thermal sensor is automatically enabled */
mask |= IXGBE_EIMS_TS;
@@ -3183,6 +3346,7 @@ ixgbe_set_ivar(struct ix_softc *sc, uint
case ixgbe_mac_X540:
case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x:
+ case ixgbe_mac_X550EM_a:
if (type == -1) { /* MISC IVAR */
index = (entry & 1) * 8;
ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
Index: ./dev/pci/if_ix.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_ix.h,v
retrieving revision 1.32
diff -u -p -r1.32 if_ix.h
--- ./dev/pci/if_ix.h 21 Nov 2016 17:21:33 -0000 1.32
+++ ./dev/pci/if_ix.h 17 Sep 2018 19:59:55 -0000
@@ -165,6 +165,7 @@ struct ix_queue {
struct tx_ring {
struct ix_softc *sc;
uint32_t me;
+ uint32_t tail; /* 4.0 just set during rx init ??>>.. */
uint32_t watchdog_timer;
union ixgbe_adv_tx_desc *tx_base;
struct ixgbe_tx_buf *tx_buffers;
@@ -192,6 +193,7 @@ struct tx_ring {
struct rx_ring {
struct ix_softc *sc;
uint32_t me;
+ uint32_t tail;
union ixgbe_adv_rx_desc *rx_base;
struct ixgbe_dma_alloc rxdma;
#if 0
@@ -252,10 +254,36 @@ struct ix_softc {
uint32_t link_speed;
bool link_up;
uint32_t linkvec;
+ /* 4.0 driver (x550) */
+ uint16_t dmac;
+ // uint32_t phy_layer; // prob usseless in openbsd ixgbe_get_supported_physical_layer => ixgbe_add_media_types
+ /* Power management-related */
+ bool wol_support;
+ uint32_t wufc;
/* Mbuf cluster size */
uint32_t rx_mbuf_sz;
+ /*4.0*/
+ /* Support for pluggable optics */
+ bool sfp_probe;
+ void *link_si; /* Link tasklet */
+ /* Tasklets for Link, SFP, Multispeed Fiber and Flow Director */
+ /*
+ adapter->link_si = softint_establish(SOFTINT_NET |IXGBE_SOFTINFT_FLAGS,
+ ixgbe_handle_link, adapter);
+ */
+ void *mod_si; /* SFP tasklet */
+ void *msf_si; /* Multispeed Fiber */
+ void *mbx_si; /* VF -> PF mailbox interrupt */
+ /* Flow Director */
+ int fdir_reinit;
+ void *fdir_si;
+
+ void *phy_si; /* PHY intr tasklet */
+
+ /// and workqueue stuff ?
+
/*
* Queues:
* This is the irq holder, it has
@@ -291,6 +319,35 @@ struct ix_softc {
unsigned long link_irq;
struct ixgbe_hw_stats stats;
+
+ /* 4.0 features */
+ uint32_t feat_cap;
+#define IXGBE_FEATURE_VF (uint32_t)(1 << 0)
+#ifndef PCI_IOV
+#define IXGBE_FEATURE_SRIOV (uint32_t)(1 << 1)
+#endif
+//#ifndef RSS
+#define IXGBE_FEATURE_RSS (uint32_t)(1 << 2)
+//#endif
+#ifndef DEV_NETMAP
+#define IXGBE_FEATURE_NETMAP (uint32_t)(1 << 3)
+#endif
+#define IXGBE_FEATURE_FAN_FAIL (uint32_t)(1 << 4)
+#define IXGBE_FEATURE_TEMP_SENSOR (uint32_t)(1 << 5)
+#define IXGBE_FEATURE_BYPASS (uint32_t)(1 << 6)
+#define IXGBE_FEATURE_LEGACY_TX (uint32_t)(1 << 7)
+#define IXGBE_FEATURE_FDIR (uint32_t)(1 << 8)
+#define IXGBE_FEATURE_MSI (uint32_t)(1 << 9)
+#define IXGBE_FEATURE_MSIX (uint32_t)(1 << 10)
+#define IXGBE_FEATURE_EEE (uint32_t)(1 << 11)
+#define IXGBE_FEATURE_LEGACY_IRQ (uint32_t)(1 << 12)
+#define IXGBE_FEATURE_NEEDS_CTXD (uint32_t)(1 << 13)
+#define IXGBE_FEATURE_FLAGS "\20" \
+ "\1" "VF" "\2" "SRIOV" "\3" "RSS" "\4" "NETMAP" \
+ "\5" "FAN_FAIL" "\6" "TEMP_SENSOR" "\7" "BYPASS" "\10" "LEGACY_TX" \
+ "\11" "FDIR" "\12" "MSI" "\13" "MSIX" "\14" "EEE" \
+ "\15" "LEGACY_IRQ" "\16" "NEEDS_CTXD"
+ uint32_t feat_en;
};
#endif /* _IX_H_ */
Index: ./dev/pci/ixgbe.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/ixgbe.c,v
retrieving revision 1.23
diff -u -p -r1.23 ixgbe.c
--- ./dev/pci/ixgbe.c 2 Dec 2016 15:22:57 -0000 1.23
+++ ./dev/pci/ixgbe.c 17 Sep 2018 19:59:55 -0000
@@ -1,8 +1,8 @@
-/* $OpenBSD: ixgbe.c,v 1.23 2016/12/02 15:22:57 mikeb Exp $ */
-
+/* $OpenBSD$ */
/******************************************************************************
+ SPDX-License-Identifier: BSD-3-Clause
- Copyright (c) 2001-2015, Intel Corporation
+ Copyright (c) 2001-2017, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -32,17 +32,11 @@
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
-/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 299200 2016-05-06 22:54:56Z pfg $*/
-/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_mbx.c 299200 2016-05-06 22:54:56Z pfg $*/
+/*$FreeBSD$*/
#include <dev/pci/ixgbe.h>
-
-#ifdef __sparc64__
-#include <dev/ofw/openfirm.h>
-#endif
-
-void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw,
- uint16_t link_status);
+#include <dev/pci/ixgbe_type.h>
+#include <dev/pci/ixgbe_api.h>
int32_t ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
int32_t ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
@@ -50,41 +44,30 @@ void ixgbe_release_eeprom_semaphore(stru
int32_t ixgbe_ready_eeprom(struct ixgbe_hw *hw);
void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, uint16_t data,
- uint16_t count);
+ uint16_t count);
uint16_t ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, uint16_t count);
void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec);
void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec);
void ixgbe_release_eeprom(struct ixgbe_hw *hw);
int32_t ixgbe_mta_vector(struct ixgbe_hw *hw, uint8_t *mc_addr);
-int32_t ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw);
-int32_t ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw);
-int32_t ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw);
-bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
-int32_t ixgbe_negotiate_fc(struct ixgbe_hw *hw, uint32_t adv_reg,
- uint32_t lp_reg, uint32_t adv_sym, uint32_t adv_asm,
- uint32_t lp_sym, uint32_t lp_asm);
-
-int32_t prot_autoc_read_generic(struct ixgbe_hw *, bool *, uint32_t *);
-int32_t prot_autoc_write_generic(struct ixgbe_hw *, uint32_t, bool);
-
-int32_t ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, uint32_t vlan);
-
-/* MBX */
-int32_t ixgbe_poll_for_msg(struct ixgbe_hw *hw, uint16_t mbx_id);
-int32_t ixgbe_poll_for_ack(struct ixgbe_hw *hw, uint16_t mbx_id);
-uint32_t ixgbe_read_v2p_mailbox(struct ixgbe_hw *hw);
-int32_t ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, uint32_t mask,
- int32_t index);
-int32_t ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, uint16_t vf_number);
-int32_t ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, uint16_t vf_number);
-int32_t ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, uint16_t vf_number);
-int32_t ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, uint16_t vf_number);
-int32_t ixgbe_write_mbx_pf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size,
- uint16_t vf_number);
-int32_t ixgbe_read_mbx_pf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size,
- uint16_t vf_number);
-
+int32_t ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
+ uint16_t *san_mac_offset);
+int32_t ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, uint16_t offset,
+ uint16_t words, uint16_t *data);
+int32_t ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, uint16_t offset,
+ uint16_t words, uint16_t *data);
+int32_t ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
+ uint16_t offset);
+int32_t ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, uint16_t offset,
+ uint16_t words, uint16_t *data);
+int32_t ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, uint16_t offset,
+ uint16_t words, uint16_t *data);
+int32_t ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, uint16_t offset,
+ uint16_t words, uint16_t *data);
+int32_t ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw);
+int32_t ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, uint8_t *addr_list,
+ uint32_t addr_count, ixgbe_mc_addr_itr next);
/**
* ixgbe_init_ops_generic - Inits function ptrs
@@ -96,18 +79,23 @@ int32_t ixgbe_init_ops_generic(struct ix
{
struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
struct ixgbe_mac_info *mac = &hw->mac;
- uint32_t eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+ uint32_t eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
DEBUGFUNC("ixgbe_init_ops_generic");
/* EEPROM */
eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
/* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
- if (eec & IXGBE_EEC_PRES)
+ if (eec & IXGBE_EEC_PRES) {
eeprom->ops.read = ixgbe_read_eerd_generic;
- else
+ eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
+ } else {
eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
+ eeprom->ops.read_buffer =
+ ixgbe_read_eeprom_buffer_bit_bang_generic;
+ }
eeprom->ops.write = ixgbe_write_eeprom_generic;
+ eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
eeprom->ops.validate_checksum =
ixgbe_validate_eeprom_checksum_generic;
eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
@@ -135,6 +123,7 @@ int32_t ixgbe_init_ops_generic(struct ix
mac->ops.led_off = ixgbe_led_off_generic;
mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
+ mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic;
/* RAR, Multicast, VLAN */
mac->ops.set_rar = ixgbe_set_rar_generic;
@@ -143,11 +132,13 @@ int32_t ixgbe_init_ops_generic(struct ix
mac->ops.set_vmdq = NULL;
mac->ops.clear_vmdq = NULL;
mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
+ mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
mac->ops.enable_mc = ixgbe_enable_mc_generic;
mac->ops.disable_mc = ixgbe_disable_mc_generic;
mac->ops.clear_vfta = NULL;
mac->ops.set_vfta = NULL;
+ mac->ops.set_vlvf = NULL;
mac->ops.init_uta_tables = NULL;
mac->ops.enable_rx = ixgbe_enable_rx_generic;
mac->ops.disable_rx = ixgbe_disable_rx_generic;
@@ -155,11 +146,15 @@ int32_t ixgbe_init_ops_generic(struct ix
/* Flow Control */
mac->ops.fc_enable = ixgbe_fc_enable_generic;
mac->ops.setup_fc = ixgbe_setup_fc_generic;
+ mac->ops.fc_autoneg = ixgbe_fc_autoneg;
/* Link */
mac->ops.get_link_capabilities = NULL;
mac->ops.setup_link = NULL;
mac->ops.check_link = NULL;
+ mac->ops.dmac_config = NULL;
+ mac->ops.dmac_update_tcs = NULL;
+ mac->ops.dmac_config_tcs = NULL;
return IXGBE_SUCCESS;
}
@@ -185,16 +180,30 @@ bool ixgbe_device_supports_autoneg_fc(st
case ixgbe_media_type_fiber_fixed:
case ixgbe_media_type_fiber_qsfp:
case ixgbe_media_type_fiber:
- hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
- /* if link is down, assume supported */
- if (link_up)
- supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
+ /* flow control autoneg black list */
+ switch (hw->device_id) {
+ case IXGBE_DEV_ID_X550EM_A_SFP:
+ case IXGBE_DEV_ID_X550EM_A_SFP_N:
+ case IXGBE_DEV_ID_X550EM_A_QSFP:
+ case IXGBE_DEV_ID_X550EM_A_QSFP_N:
+ supported = FALSE;
+ break;
+ default:
+ hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
+ /* if link is down, assume supported */
+ if (link_up)
+ supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
TRUE : FALSE;
- else
- supported = TRUE;
+ else
+ supported = TRUE;
+ }
+
break;
case ixgbe_media_type_backplane:
- supported = TRUE;
+ if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
+ supported = FALSE;
+ else
+ supported = TRUE;
break;
case ixgbe_media_type_copper:
/* only some copper devices support flow control autoneg */
@@ -206,6 +215,9 @@ bool ixgbe_device_supports_autoneg_fc(st
case IXGBE_DEV_ID_X550T:
case IXGBE_DEV_ID_X550T1:
case IXGBE_DEV_ID_X550EM_X_10G_T:
+ case IXGBE_DEV_ID_X550EM_A_10G_T:
+ case IXGBE_DEV_ID_X550EM_A_1G_T:
+ case IXGBE_DEV_ID_X550EM_A_1G_T_L:
supported = TRUE;
break;
default:
@@ -215,11 +227,10 @@ bool ixgbe_device_supports_autoneg_fc(st
break;
}
- if (!supported) {
+ if (!supported)
ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
- "Device %x does not support flow control autoneg",
- hw->device_id);
- }
+ "Device %x does not support flow control autoneg",
+ hw->device_id);
return supported;
}
@@ -237,7 +248,7 @@ int32_t ixgbe_setup_fc_generic(struct ix
uint16_t reg_cu = 0;
bool locked = FALSE;
- DEBUGFUNC("ixgbe_setup_fc");
+ DEBUGFUNC("ixgbe_setup_fc_generic");
/* Validate the requested mode */
if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
@@ -266,7 +277,7 @@ int32_t ixgbe_setup_fc_generic(struct ix
if (ret_val != IXGBE_SUCCESS)
goto out;
- /* only backplane uses autoc so fall though */
+ /* fall through - only backplane uses autoc */
case ixgbe_media_type_fiber_fixed:
case ixgbe_media_type_fiber_qsfp:
case ixgbe_media_type_fiber:
@@ -391,8 +402,9 @@ out:
**/
int32_t ixgbe_start_hw_generic(struct ixgbe_hw *hw)
{
- int32_t ret_val = IXGBE_SUCCESS;
+ int32_t ret_val;
uint32_t ctrl_ext;
+ uint16_t device_caps;
DEBUGFUNC("ixgbe_start_hw_generic");
@@ -414,17 +426,32 @@ int32_t ixgbe_start_hw_generic(struct ix
IXGBE_WRITE_FLUSH(hw);
/* Setup flow control */
- if (hw->mac.ops.setup_fc) {
- ret_val = hw->mac.ops.setup_fc(hw);
- if (ret_val != IXGBE_SUCCESS)
- goto out;
+ ret_val = ixgbe_setup_fc(hw);
+ if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) {
+ DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val);
+ return ret_val;
+ }
+
+ /* Cache bit indicating need for crosstalk fix */
+ switch (hw->mac.type) {
+ case ixgbe_mac_82599EB:
+ case ixgbe_mac_X550EM_x:
+ case ixgbe_mac_X550EM_a:
+ hw->mac.ops.get_device_caps(hw, &device_caps);
+ if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
+ hw->need_crosstalk_fix = FALSE;
+ else
+ hw->need_crosstalk_fix = TRUE;
+ break;
+ default:
+ hw->need_crosstalk_fix = FALSE;
+ break;
}
/* Clear adapter stopped flag */
hw->adapter_stopped = FALSE;
-out:
- return ret_val;
+ return IXGBE_SUCCESS;
}
/**
@@ -485,11 +512,18 @@ int32_t ixgbe_init_hw_generic(struct ixg
/* Reset the hardware */
status = hw->mac.ops.reset_hw(hw);
- if (status == IXGBE_SUCCESS) {
+ if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) {
/* Start the HW */
status = hw->mac.ops.start_hw(hw);
}
+ /* Initialize the LED link active for LED blink support */
+ if (hw->mac.ops.init_led_link_act)
+ hw->mac.ops.init_led_link_act(hw);
+
+ if (status != IXGBE_SUCCESS)
+ DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status);
+
return status;
}
@@ -608,6 +642,340 @@ int32_t ixgbe_clear_hw_cntrs_generic(str
}
/**
+ * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
+ * @hw: pointer to hardware structure
+ * @pba_num: stores the part number string from the EEPROM
+ * @pba_num_size: part number string buffer length
+ *
+ * Reads the part number string from the EEPROM.
+ **/
+int32_t ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, uint8_t *pba_num,
+ uint32_t pba_num_size)
+{
+ int32_t ret_val;
+ uint16_t data;
+ uint16_t pba_ptr;
+ uint16_t offset;
+ uint16_t length;
+
+ DEBUGFUNC("ixgbe_read_pba_string_generic");
+
+ if (pba_num == NULL) {
+ DEBUGOUT("PBA string buffer was null\n");
+ return IXGBE_ERR_INVALID_ARGUMENT;
+ }
+
+ ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
+ if (ret_val) {
+ DEBUGOUT("NVM Read Error\n");
+ return ret_val;
+ }
+
+ ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
+ if (ret_val) {
+ DEBUGOUT("NVM Read Error\n");
+ return ret_val;
+ }
+
+ /*
+ * if data is not ptr guard the PBA must be in legacy format which
+ * means pba_ptr is actually our second data word for the PBA number
+ * and we can decode it into an ascii string
+ */
+ if (data != IXGBE_PBANUM_PTR_GUARD) {
+ DEBUGOUT("NVM PBA number is not stored as string\n");
+
+ /* we will need 11 characters to store the PBA */
+ if (pba_num_size < 11) {
+ DEBUGOUT("PBA string buffer too small\n");
+ return IXGBE_ERR_NO_SPACE;
+ }
+
+ /* extract hex string from data and pba_ptr */
+ pba_num[0] = (data >> 12) & 0xF;
+ pba_num[1] = (data >> 8) & 0xF;
+ pba_num[2] = (data >> 4) & 0xF;
+ pba_num[3] = data & 0xF;
+ pba_num[4] = (pba_ptr >> 12) & 0xF;
+ pba_num[5] = (pba_ptr >> 8) & 0xF;
+ pba_num[6] = '-';
+ pba_num[7] = 0;
+ pba_num[8] = (pba_ptr >> 4) & 0xF;
+ pba_num[9] = pba_ptr & 0xF;
+
+ /* put a null character on the end of our string */
+ pba_num[10] = '\0';
+
+ /* switch all the data but the '-' to hex char */
+ for (offset = 0; offset < 10; offset++) {
+ if (pba_num[offset] < 0xA)
+ pba_num[offset] += '0';
+ else if (pba_num[offset] < 0x10)
+ pba_num[offset] += 'A' - 0xA;
+ }
+
+ return IXGBE_SUCCESS;
+ }
+
+ ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
+ if (ret_val) {
+ DEBUGOUT("NVM Read Error\n");
+ return ret_val;
+ }
+
+ if (length == 0xFFFF || length == 0) {
+ DEBUGOUT("NVM PBA number section invalid length\n");
+ return IXGBE_ERR_PBA_SECTION;
+ }
+
+ /* check if pba_num buffer is big enough */
+ if (pba_num_size < (((uint32_t)length * 2) - 1)) {
+ DEBUGOUT("PBA string buffer too small\n");
+ return IXGBE_ERR_NO_SPACE;
+ }
+
+ /* trim pba length from start of string */
+ pba_ptr++;
+ length--;
+
+ for (offset = 0; offset < length; offset++) {
+ ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
+ if (ret_val) {
+ DEBUGOUT("NVM Read Error\n");
+ return ret_val;
+ }
+ pba_num[offset * 2] = (uint8_t)(data >> 8);
+ pba_num[(offset * 2) + 1] = (uint8_t)(data & 0xFF);
+ }
+ pba_num[offset * 2] = '\0';
+
+ return IXGBE_SUCCESS;
+}
+
+/**
+ * ixgbe_read_pba_num_generic - Reads part number from EEPROM
+ * @hw: pointer to hardware structure
+ * @pba_num: stores the part number from the EEPROM
+ *
+ * Reads the part number from the EEPROM.
+ **/
+int32_t ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, uint32_t *pba_num)
+{
+ int32_t ret_val;
+ uint16_t data;
+
+ DEBUGFUNC("ixgbe_read_pba_num_generic");
+
+ ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
+ if (ret_val) {
+ DEBUGOUT("NVM Read Error\n");
+ return ret_val;
+ } else if (data == IXGBE_PBANUM_PTR_GUARD) {
+ DEBUGOUT("NVM Not supported\n");
+ return IXGBE_NOT_IMPLEMENTED;
+ }