Merge branch 'verilator' of github.com:efabless/caravel into verilator

manifest

@@ -20,7 +20,7 @@ fa26aa34b4b382aacad9b7ac07a36b17172a401f  verilog/rtl/caravel.v
 1bbaa93405d4cb51429eacea4da40014231b11ed  verilog/rtl/caravel_motto.v
 ae07f0d87e69f4dd2026ed841e3a962facac847b  verilog/rtl/caravel_openframe.v
 d97cb60c8d125d6098111d4f0aa00410515770eb  verilog/rtl/caravel_power_routing.v
-e54c181033aa019f0edcaed5ffc71e54c3888970  verilog/rtl/chip_io.v
+322be4d9f6bb67b5692f8a34d7f9675664264be2  verilog/rtl/chip_io.v
 1088531d6a69d82b976d4aca7ae923423680a715  verilog/rtl/chip_io_alt.v
 b080fd6193e1aee1cd476d8a4c117d65ae1e1178  verilog/rtl/chip_io_openframe.v
 126aff02aa229dc346301c552d785dec76a4d68e  verilog/rtl/clock_div.v
@@ -49,10 +49,10 @@ e0c6ead5e35c1ba01d923c482e953c2af9691524  verilog/rtl/mprj_io_buffer.v
 5287821a0ed1994850a978ef0cd024fac51fb6e8  verilog/rtl/open_source.v
 189532aff9e5e2ebbd99befd05cbf50e948b14af  verilog/rtl/openframe_netlists.v
 b53c154e6acaf44e858c936c8027d0229608676e  verilog/rtl/pads.v
-669d16642d5dd5f6824812754db20db98c9fe17b  verilog/rtl/ring_osc2x13.v
+e4d388bb3116d86c669585698156460510078478  verilog/rtl/ring_osc2x13.v
 83937790b8f5dbcdd7e9a804b5e9bdf475c0ab7d  verilog/rtl/simple_por.v
 b9d6114a5067a04dd59cdd46fb988591c16743ce  verilog/rtl/spare_logic_block.v
-328d6212a394981a4e63a38748b99afaa403a0a0  verilog/rtl/toplevel_cocotb.v
+1767a1a5b32dcc6df34cc1cc6363beedd1d8208c  verilog/rtl/toplevel_cocotb.v
 8f0bec01c914efe790a09ffe62bbfe0781069e35  verilog/rtl/xres_buf.v
 256190717faa72005cf7656d8443c4c0693b3f78  scripts/set_user_id.py
 731116709a44d13225170acc83cd34ff9e00fa39  scripts/generate_fill.py