diff --git a/src/main/scala/RsSynd/RsSynd.scala b/src/main/scala/RsSynd/RsSynd.scala
index 615bac5..7d27eed 100644
--- a/src/main/scala/RsSynd/RsSynd.scala
+++ b/src/main/scala/RsSynd/RsSynd.scala
@@ -7,15 +7,15 @@ import chisel3.util._
 class RsSynd extends Module with GfParams {
   val io = IO(new Bundle {
     val sAxisIf = Input(Valid(new axisIf(axisWidth)))
-    val synd = Output(Valid(Vec(redundancy, UInt(symbWidth.W))))
+    val syndIf = Output(Valid(Vec(redundancy, UInt(symbWidth.W))))
   })
 
   for(i <- 0 until redundancy) {
-    val rsSyndRoot = Module(new RsSyndPolyEval)
-    rsSyndRoot.io.root := alphaToSymb(i.U)
+    val rsSyndRoot = Module(new RsSyndPolyEval)    
+    rsSyndRoot.io.root := alphaToSymb((firstConsecutiveRoot+i).U)
     rsSyndRoot.io.sAxisIf := io.sAxisIf
-    io.synd.bits(i) := rsSyndRoot.io.synd.bits
-    io.synd.valid := rsSyndRoot.io.synd.valid
+    io.syndIf.bits(i) := rsSyndRoot.io.syndIf.bits
+    io.syndIf.valid := rsSyndRoot.io.syndIf.valid
   }
 }
 
@@ -23,6 +23,6 @@ class RsSynd extends Module with GfParams {
 object GenSynd extends App {
   //ChiselStage.emitSystemVerilogFile(new RsSyndHorner(), Array())
   //ChiselStage.emitSystemVerilogFile(new GfPolyTermEval(), Array())
-  ChiselStage.emitSystemVerilogFile(new RsSyndPolyEval(), Array())
+  //ChiselStage.emitSystemVerilogFile(new RsSyndPolyEval(), Array())
   ChiselStage.emitSystemVerilogFile(new RsSynd(), Array())
 }