From fea448c73d5254e52c7f9a4d1149224f521c15ab Mon Sep 17 00:00:00 2001
From: egorman44 <easmirnov44@gmail.com>
Date: Sat, 11 May 2024 11:25:56 +0400
Subject: [PATCH] [RsChien] Substitute posArray(NumPosIf bundle) port with
 errPosIf(vecFfsIf bundle).

---
 src/main/scala/RsChien/RsChien.scala            | 8 ++++----
 src/main/scala/RsChien/RsChienBitPosToNum.scala | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/main/scala/RsChien/RsChien.scala b/src/main/scala/RsChien/RsChien.scala
index f7a9785..30f5016 100644
--- a/src/main/scala/RsChien/RsChien.scala
+++ b/src/main/scala/RsChien/RsChien.scala
@@ -12,7 +12,7 @@ import chisel3.util._
 class RsChien extends Module with GfParams{
   val io = IO(new Bundle {
     val errLocIf = Input(Valid(new vecFfsIf(tLen+1)))
-    val posArray = Output(new NumPosIf)
+    val errPosIf = Output(Valid(new vecFfsIf(tLen)))
     val chienErrDetect = Output(Bool())
   })
 
@@ -21,10 +21,10 @@ class RsChien extends Module with GfParams{
 
   rsChienErrBitPos.io.errLocIf <> io.errLocIf
   rsChienBitPosToNum.io.bitPos <> rsChienErrBitPos.io.bitPos
-  io.posArray <> rsChienBitPosToNum.io.posArray
+  io.errPosIf <> rsChienBitPosToNum.io.errPosIf
 
-  when(io.posArray.valid) {
-    io.chienErrDetect := (io.errLocIf.bits.ffs(tLen,1) ^ io.posArray.sel).orR
+  when(io.errPosIf.valid) {
+    io.chienErrDetect := (io.errLocIf.bits.ffs(tLen,1) ^ io.errPosIf.bits.ffs).orR
   }.otherwise {
     io.chienErrDetect := 0.U
   }
diff --git a/src/main/scala/RsChien/RsChienBitPosToNum.scala b/src/main/scala/RsChien/RsChienBitPosToNum.scala
index df33547..826ee89 100644
--- a/src/main/scala/RsChien/RsChienBitPosToNum.scala
+++ b/src/main/scala/RsChien/RsChienBitPosToNum.scala
@@ -12,7 +12,7 @@ import chisel3.util._
 class RsChienBitPosToNum extends Module with GfParams {
   val io = IO(new Bundle {
     val bitPos = Input(new BitPosIf)
-    val posArray = Output(new NumPosIf)
+    val errPosIf = Output(Valid(new vecFfsIf(tLen)))
   })
 
   val base = RegInit(UInt(symbWidth.W), 0.U)
@@ -87,15 +87,15 @@ class RsChienBitPosToNum extends Module with GfParams {
     for(k <- 0 until chienRootsPerCycle) {
       baseArray(k) := stageCapt(i).base + k.U
     }
-    io.posArray.pos(i) := nLen - 1 - Mux1H(stageCapt(i).pos, baseArray)
+    io.errPosIf.bits.vec(i) := nLen - 1 - Mux1H(stageCapt(i).pos, baseArray)
   }
 
   val ffs = Module(new FindFirstSetNew(width=tLen, lsbFirst=false))
   ffs.io.in := VecInit(stageCapt.map(_.valid)).asTypeOf(UInt(tLen.W))
 
-  io.posArray.sel := ffs.io.out
+  io.errPosIf.bits.ffs := ffs.io.out
 
-  io.posArray.valid := RegNext(lastComb(tLen-1))
+  io.errPosIf.valid := RegNext(lastComb(tLen-1))
 
 }