info.yaml

# Tiny Tapeout project information
project:
  title:        "PLL blocks"      # Project title
  author:       "Vipul Sharma"      # Your name
  discord:      "vks"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
  description:  "This design contains blocks used in PLL circuit"      # One line description of what your project does
  language:     "Analog" # other examples include Verilog, Amaranth, VHDL, etc
  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "1x2"          # Valid values: 1x1 (digital only), 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_vks_pll"
  
  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
  source_files:        
    - "project.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
  # Inputs
  ui[0]: "CP-1:QA"
  ui[1]: "CP-1:QB"
  ui[2]: "FD-2:Clk"
  ui[3]: "FD-3:fo"
  ui[4]: ""
  ui[5]: ""
  ui[6]: "ref"
  ui[7]: ""

  # Outputs
  uo[0]: "PFD-2:QA"
  uo[1]: "PFD-2:QB"
  uo[2]: "FD-2:fo_4"
  uo[3]: "FD-2:fo_8"
  uo[4]: "FD-3:fo_4"
  uo[5]: "FD-3:fo_8"
  uo[6]: "FD-4:Out_4"
  uo[7]: "FD-4:Out_8"

  # Bidirectional pins
  uio[0]: "FD-1:fo"
  uio[1]: "FD-1:fo_by_8"
  uio[2]: "PFD-1:A"
  uio[3]: "PFD-1:B"
  uio[4]: "PFD-1:QA"
  uio[5]: "PFD-1:QB"
  uio[6]: "PFD-2:A"
  uio[7]: "PFD-2:B"

  # Analog pins - you can add more if you use them, up to 8
  ua[0]: "CP_bias"
  ua[1]: "vout"
  ua[2]: "vctrl"
  ua[3]: "Osc_out"
  ua[4]: "cp_bias"
  ua[5]: "out"

# Do not change!
yaml_version: 6