From 9cffe392ea9a5ae2784fb4a546d83ddac759b04f Mon Sep 17 00:00:00 2001
From: Hans Baier <hansfbaier@gmail.com>
Date: Thu, 9 Nov 2023 10:28:39 +0700
Subject: [PATCH] add W9812G6JB SDRAM module

---
 litedram/modules.py | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index af517b168..f80de56c2 100755
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -553,6 +553,15 @@ class W9825G6KH6(SDRModule):
     technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
     speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 60), tFAW=None, tRAS=42)}
 
+class W9812G6JB(SDRModule):
+    # geometry
+    nbanks = 4
+    nrows  = 4096
+    ncols  = 512
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 12))
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=20, tRFC=(None, 60), tFAW=None, tRAS=42)}
+
 # DDR ----------------------------------------------------------------------------------------------
 
 class DDRModule(SDRAMModule):                     memtype = "DDR"