From ccf31af936adf052f772abf9d4716cb71b86619a Mon Sep 17 00:00:00 2001
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: Mon, 17 Jun 2024 13:34:20 +0100
Subject: [PATCH] soc/integration/soc.py: Fix creation of AHB2Wishbone bridge

Don't do bus_addressing_convert as it's being handled in AHB2Wishbone
logic.

Add addressing parameters for AHBInterface constructor as required
by soc code.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 litex/soc/integration/soc.py  | 6 ++++++
 litex/soc/interconnect/ahb.py | 5 +++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 85b0360c36..df5645dfeb 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -30,6 +30,7 @@
 from litex.soc.interconnect import stream
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect import axi
+from litex.soc.interconnect import ahb
 
 
 # Helpers ------------------------------------------------------------------------------------------
@@ -367,6 +368,9 @@ def bus_addressing_convert(interface, direction):
             # AXI/AXI-Lite interface, Bus-Addressing conversion already handled in Bus-Standard conversion.
             elif isinstance(interface, (axi.AXIInterface, axi.AXILiteInterface)):
                 return interface
+            # AHB to Wishbone, Bus-Addressing conversion already handled in Bus-Standard conversion.
+            elif isinstance(interface, (ahb.AHBInterface, wishbone.Interface)) and direction == "m2s":
+                return interface
             # Different Addressing: Return adapted interface.
             else:
                 interface_cls = type(interface)
@@ -419,6 +423,7 @@ def bus_standard_convert(interface, direction):
                     (axi.AXILiteInterface, axi.AXIInterface)    : axi.AXILite2AXI,
                     (axi.AXIInterface,     axi.AXILiteInterface): axi.AXI2AXILite,
                     (axi.AXIInterface,     wishbone.Interface)  : axi.AXI2Wishbone,
+                    (ahb.AHBInterface,     wishbone.Interface)  : ahb.AHB2Wishbone,
                 }[type(master), type(slave)]
                 bridge = bridge_cls(master, slave)
                 self.submodules += bridge
@@ -436,6 +441,7 @@ def bus_standard_convert(interface, direction):
                 wishbone.Interface:   "Wishbone",
                 axi.AXILiteInterface: "AXI-Lite",
                 axi.AXIInterface:     "AXI",
+                ahb.AHBInterface:     "AHB",
             }
             self.logger.info(fmt.format(
                 name      = colorer(name),
diff --git a/litex/soc/interconnect/ahb.py b/litex/soc/interconnect/ahb.py
index 178eeb3462..9935a4d676 100644
--- a/litex/soc/interconnect/ahb.py
+++ b/litex/soc/interconnect/ahb.py
@@ -41,11 +41,12 @@ def ahb_description(data_width, address_width):
 ]
 
 class AHBInterface(Record):
-    def __init__(self, data_width=32, address_width=32):
+    def __init__(self, data_width=32, address_width=32, addressing="byte"):
+        assert addressing == "byte"
         Record.__init__(self, ahb_description(data_width, address_width))
         self.data_width    = data_width
         self.address_width = address_width
-        self.addressing    = "byte"
+        self.addressing    = addressing
 
 # AHB to Wishbone  ---------------------------------------------------------------------------------