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comparch.micro.channels.md

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C++ links: computer architecture - microarchitectural channels

See also: Computer Architecture

  • Leakage channels: side channels (accidental), covert channels (deliberate).
  • Storage channels (functional behavior), timing channels (temporal behavior).
  • Timing-based channels (operations timing), access-based channels (direct information access), trace-based channels (program execution measurement).

Contents


General


Defense, Mitigation, Protection

Defense - Branch Predictor

Defense - Cache

Defense - Floating Point Unit (FPU)

Defense - Hardware Design & Verification

Defense - Software

Defense - Software - Compilation and Programming Languages

Defense - Speculation


Arithmetic Logic Unit (ALU)


Branch Predictor


Cache

Cache - Data-Direct I/O (DDIO)


DRAM


Electromagnetic (EM) Emanations


Floating Point Unit (FPU)


FPGA

FPGA remote attacks

(through (partial) access on configuration/bitstream)

FPGA local attacks

(with physical access or within close proximity)

FPGA attacks countermeasures


GPU


Interrupts


Keyboard


Magnetic


Memory Bus


Memory Order Buffer (MOB)


Memory Management Unit (MMU)


Power


Prefetch


Pseudo-Random Number Generator (PRNG)


Return Stack Buffer (RSB)


Trusted Execution Environments (TEEs)

Arm TrustZone

Intel SGX


SMT


Speculation

Transient execution attacks
Classification tree - http://transient.fail/
Proof-of-Concept Repository - https://github.com/IAIK/transientfail/


Store Buffer

  • Fallout: Reading Kernel Writes From User Space
    • 2019 arXiv
    • Marina Minkin, Daniel Moghimi, Moritz Lipp, Michael Schwarz, Jo Van Bulck, Daniel Genkin, Daniel Gruss, Frank Piessens, Berk Sunar, Yuval Yarom
    • https://arxiv.org/abs/1905.12701
    • CVE-2018-12126 - Microarchitectural Store Buffer Data Sampling (MSBDS) - Fallout

Thermal


Translation Lookaside Buffer (TLB)


TSX


Talks

2019

2018

2017

2016

2015

2014

2009