From 83674fbc90b9ab49c64a5b74a151d772c4a35085 Mon Sep 17 00:00:00 2001 From: ivmarkov Date: Wed, 18 Oct 2023 11:35:19 +0000 Subject: [PATCH] esp32c6 can use the PLL160M clock actually --- CHANGELOG.md | 2 +- src/i2s.rs | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index cd86bedcdb3..9035af17fa1 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,7 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 ## [0.42.1] - 2023-10-18 * Fix ambiguous name error #325 - a compilation issue when the NimBLE component is enabled in `esp-idf-sys` -* Fix compilation issues of the I2S driver for esp32h2, esp32c2 and esp32c6 +* Fix compilation issues of the I2S driver for esp32h2 and esp32c2 * Fix compilation issues of the ADC drivers when the ESP IDF `esp_adc` component is not enabled * Fix compilation issues of the GPIO driver for esp32c6 diff --git a/src/i2s.rs b/src/i2s.rs index c28adb5ade2..8aa14ade31a 100644 --- a/src/i2s.rs +++ b/src/i2s.rs @@ -95,7 +95,7 @@ pub mod config { #[derive(Clone, Copy, Debug, Eq, PartialEq, Default)] pub enum ClockSource { /// Use PLL_F160M as the source clock - #[cfg(not(any(esp32h2, esp32c2, esp32c6)))] + #[cfg(not(any(esp32h2, esp32c2)))] #[default] Pll160M, @@ -105,7 +105,7 @@ pub mod config { Pll60M, /// Use PLL_F64M as the source clock - #[cfg(any(esp32h2, esp32c6))] + #[cfg(esp32h2)] #[default] Pll64M, @@ -119,7 +119,7 @@ pub mod config { #[allow(clippy::unnecessary_cast)] pub(super) fn as_sdk(&self) -> i2s_clock_src_t { match self { - #[cfg(not(any(esp32h2, esp32c2, esp32c6)))] + #[cfg(not(any(esp32h2, esp32c2)))] Self::Pll160M => core::convert::TryInto::try_into( esp_idf_sys::soc_module_clk_t_SOC_MOD_CLK_PLL_F160M, ) @@ -129,7 +129,7 @@ pub mod config { esp_idf_sys::soc_module_clk_t_SOC_MOD_CLK_PLL_F60M, ) .unwrap(), - #[cfg(any(esp32h2, esp32c6))] + #[cfg(esp32h2)] Self::Pll64M => core::convert::TryInto::try_into( esp_idf_sys::soc_module_clk_t_SOC_MOD_CLK_PLL_F64M, )