From 0412e3bce34ba60e3f02436a800ceafabec6081f Mon Sep 17 00:00:00 2001 From: vchapuis Date: Mon, 19 Jun 2023 14:37:51 +0800 Subject: [PATCH 1/3] feature: expose C api `cs_pre_trans_delay` in `SpiDriver` --- src/spi.rs | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/spi.rs b/src/spi.rs index b4d20467a74..27d992c8f1f 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -233,6 +233,10 @@ pub mod config { pub duplex: Duplex, pub bit_order: BitOrder, pub cs_active_high: bool, + ///< Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). This only works on half-duplex transactions. + pub cs_pre_delay_us: Option, // u16 as per the C struct has a uint16_t, cf: esp-idf/components/driver/spi/include/driver/spi_master.h spi_device_interface_config_t + ///< Amount of SPI bit-cycles the cs should stay active after the transmission (0-16) + pub cs_post_delay_us: Option, // u8 as per the C struct had a uint8_t, cf: esp-idf/components/driver/spi/include/driver/spi_master.h spi_device_interface_config_t pub input_delay_ns: i32, } @@ -277,6 +281,22 @@ pub mod config { self } + /// Add an aditional Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). + /// This only works on half-duplex transactions. + #[must_use] + pub fn cs_pre_delay_us(mut self, delay_us: u16) -> Self { + self.cs_pre_delay_us = Some(delay_us); + self + } + + /// Add an aditional Amount of SPI bit-cycles the cs should be activated after the transmission (0-16). + /// This only works on half-duplex transactions. + #[must_use] + pub fn cs_post_delay_us(mut self, delay_us: u8) -> Self { + self.cs_post_delay_us = Some(delay_us); + self + } + #[must_use] pub fn input_delay_ns(mut self, input_delay_ns: i32) -> Self { self.input_delay_ns = input_delay_ns; @@ -293,6 +313,8 @@ pub mod config { cs_active_high: false, duplex: Duplex::Full, bit_order: BitOrder::MsbFirst, + cs_pre_delay_us: None, + cs_post_delay_us: None, input_delay_ns: 0, } } @@ -324,6 +346,8 @@ impl SpiBusDriver { 0_u32 } | config.duplex.as_flags() | config.bit_order.as_flags(), + cs_ena_pretrans: config.cs_pre_delay_us.unwrap_or(0), + cs_ena_posttrans: config.cs_post_delay_us.unwrap_or(0), ..Default::default() }; @@ -693,6 +717,8 @@ where 0_u32 } | config.duplex.as_flags() | config.bit_order.as_flags(), + cs_ena_pretrans: config.cs_pre_delay_us.unwrap_or(0), + cs_ena_posttrans: config.cs_post_delay_us.unwrap_or(0), ..Default::default() }; From 0e2807b1d6ee56061503ee8d6f7424a8d3f10bf1 Mon Sep 17 00:00:00 2001 From: vchapuis Date: Wed, 5 Jul 2023 19:57:51 +0800 Subject: [PATCH 2/3] docs: add explanation on Duplex specifities for cs pre-transaction delays --- src/spi.rs | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/spi.rs b/src/spi.rs index 27d992c8f1f..da76229b7b5 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -233,7 +233,8 @@ pub mod config { pub duplex: Duplex, pub bit_order: BitOrder, pub cs_active_high: bool, - ///< Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). This only works on half-duplex transactions. + /// On Half-Duplex transactions: `cs_pre_delay_us % 16` corresponds to the number of SPI bit-cycles cs should be activated before the transmission. + /// On Full-Duplex transactions: `cs_pre_delay_us != 0` will add 1 microsecond of cs activation before transmission pub cs_pre_delay_us: Option, // u16 as per the C struct has a uint16_t, cf: esp-idf/components/driver/spi/include/driver/spi_master.h spi_device_interface_config_t ///< Amount of SPI bit-cycles the cs should stay active after the transmission (0-16) pub cs_post_delay_us: Option, // u8 as per the C struct had a uint8_t, cf: esp-idf/components/driver/spi/include/driver/spi_master.h spi_device_interface_config_t @@ -281,8 +282,8 @@ pub mod config { self } - /// Add an aditional Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). - /// This only works on half-duplex transactions. + /// On Half-Duplex transactions: `cs_pre_delay_us % 16` corresponds to the number of SPI bit-cycles cs should be activated before the transmission + /// On Full-Duplex transactions: `cs_pre_delay_us != 0` will add 1 microsecond of cs activation before transmission #[must_use] pub fn cs_pre_delay_us(mut self, delay_us: u16) -> Self { self.cs_pre_delay_us = Some(delay_us); @@ -1119,8 +1120,8 @@ where }) } - /// Add an aditional delay of x in uSeconds before transaction - /// between chip select and first clk out + /// Add an aditional Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). + /// This only works on half-duplex transactions. pub fn cs_pre_delay_us(&mut self, delay_us: u32) -> &mut Self { self.pre_delay_us = Some(delay_us); From 3d918c58503ebaa95be7d71e4dd5184f3abaaa7e Mon Sep 17 00:00:00 2001 From: VChapuis Date: Wed, 15 Nov 2023 23:42:47 +0800 Subject: [PATCH 3/3] fix(spi): add missing pre transaction parameters for C config struct --- src/spi.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/spi.rs b/src/spi.rs index 1c86e8b3578..8e53862d7d3 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -822,6 +822,8 @@ where } | config.duplex.as_flags() | config.bit_order.as_flags(), post_cb: Some(spi_notify), + cs_ena_pretrans: config.cs_pre_delay_us.unwrap_or(0), + cs_ena_posttrans: config.cs_post_delay_us.unwrap_or(0), ..Default::default() };