From aaeacde547fc73be51975bec9802f64498e35f8f Mon Sep 17 00:00:00 2001 From: Marc CAPDEVILLE Date: Tue, 9 Jan 2024 15:45:09 +0100 Subject: [PATCH] fix(hal) : Fix rounding adc clock parameters This is to achieve good rounded clock value. --- components/hal/adc_hal.c | 2 +- components/hal/esp32s3/include/hal/adc_ll.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c index 46a35a2e3c9..edb470dcfbe 100644 --- a/components/hal/adc_hal.c +++ b/components/hal/adc_hal.c @@ -173,7 +173,7 @@ static adc_ll_digi_convert_mode_t get_convert_mode(adc_digi_convert_mode_t conve static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, adc_continuous_clk_src_t clk_src, uint32_t clk_src_freq_hz, uint32_t sample_freq_hz) { #if !CONFIG_IDF_TARGET_ESP32 - uint32_t interval = clk_src_freq_hz / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1) / 2 / sample_freq_hz; + uint32_t interval = ((long long)clk_src_freq_hz<<10) / (((long long)ADC_LL_CLKM_DIV_NUM_DEFAULT<<10) + ((long long)ADC_LL_CLKM_DIV_A_DEFAULT<<10) / ADC_LL_CLKM_DIV_B_DEFAULT + (1<<10)) / 2 / sample_freq_hz; //set sample interval adc_ll_digi_set_trigger_interval(interval); //Here we set the clock divider factor to make the digital clock to 5M Hz diff --git a/components/hal/esp32s3/include/hal/adc_ll.h b/components/hal/esp32s3/include/hal/adc_ll.h index 7e0f405e1fc..78f62ba5419 100644 --- a/components/hal/esp32s3/include/hal/adc_ll.h +++ b/components/hal/esp32s3/include/hal/adc_ll.h @@ -55,8 +55,8 @@ extern "C" { #define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1) #define ADC_LL_CLKM_DIV_NUM_DEFAULT 15 -#define ADC_LL_CLKM_DIV_B_DEFAULT 1 -#define ADC_LL_CLKM_DIV_A_DEFAULT 0 +#define ADC_LL_CLKM_DIV_B_DEFAULT 3 +#define ADC_LL_CLKM_DIV_A_DEFAULT 2 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 #define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10