From 6169404f1f499ec2d60b9a23013b8101f8d19586 Mon Sep 17 00:00:00 2001 From: LonerDan Date: Tue, 18 Jun 2024 12:49:43 +0200 Subject: [PATCH] fix(ulp): write output mode to the correct register Fixes register mixup. According to the ESP32-S3 TRM (pages 515-516), the output pin's mode is set in the RTC_GPIO_PINn_REG, bit RTC_GPIO_PINn_PAD_DRIVER not the RTC_IO_TOUCH_PADn_REG field RTC_IO_TOUCH_PADn_DRV, which instead controls the drive output strength. --- components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h index 11e486c2f6d2..504b2e0c9138 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h @@ -109,7 +109,7 @@ static inline uint8_t ulp_riscv_gpio_get_level(gpio_num_t gpio_num) static inline void ulp_riscv_gpio_set_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t mode) { - REG_SET_FIELD(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_DRV, mode); + REG_SET_FIELD(RTC_GPIO_PIN0_REG + gpio_num * 4, RTC_GPIO_PIN0_PAD_DRIVER, mode); } static inline void ulp_riscv_gpio_pullup(gpio_num_t gpio_num)