diff --git a/src/target/espressif/esp32c2.c b/src/target/espressif/esp32c2.c
index 212fc1ae17..06a8c3db5f 100644
--- a/src/target/espressif/esp32c2.c
+++ b/src/target/espressif/esp32c2.c
@@ -139,6 +139,8 @@ static int esp32c2_target_create(struct target *target, Jim_Interp *interp)
 	esp_riscv->print_reset_reason = &esp32c2_print_reset_reason;
 	esp_riscv->existent_csrs = NULL;
 	esp_riscv->existent_csr_size = 0;
+	esp_riscv->existent_ro_csrs = NULL;
+	esp_riscv->existent_ro_csr_size = 0;
 	esp_riscv->is_dram_address = esp32c2_is_dram_address;
 	esp_riscv->is_iram_address = esp32c2_is_iram_address;
 
diff --git a/src/target/espressif/esp32c3.c b/src/target/espressif/esp32c3.c
index b4528b7121..242ffd3f72 100644
--- a/src/target/espressif/esp32c3.c
+++ b/src/target/espressif/esp32c3.c
@@ -155,6 +155,8 @@ static int esp32c3_target_create(struct target *target, Jim_Interp *interp)
 	esp_riscv->print_reset_reason = &esp32c3_print_reset_reason;
 	esp_riscv->existent_csrs = NULL;
 	esp_riscv->existent_csr_size = 0;
+	esp_riscv->existent_ro_csrs = NULL;
+	esp_riscv->existent_ro_csr_size = 0;
 	esp_riscv->is_dram_address = esp32c3_is_dram_address;
 	esp_riscv->is_iram_address = esp32c3_is_iram_address;
 
diff --git a/src/target/espressif/esp32c5.c b/src/target/espressif/esp32c5.c
index e7c12af663..e410612418 100644
--- a/src/target/espressif/esp32c5.c
+++ b/src/target/espressif/esp32c5.c
@@ -132,7 +132,29 @@ static const struct esp_flash_breakpoint_ops esp32c5_flash_brp_ops = {
 };
 
 static const char *esp32c5_csrs[] = {
-	"mideleg", "medeleg", "mie", "mip",
+	"mideleg", "medeleg", "mie", "mip", "jvt", "mtvt",
+	"mintthresh", "mnxti", "mscratchcsw", "mscratchcswl",
+	"mcycle", "mcycleh", "minstret", "minstreth",
+	"mhpmevent8", "mhpmevent9", "mhpmevent13",
+	"mhpmcounter8", "mhpmcounter9", "mhpmcounter13", "mhpmcounter8h", "mhpmcounter9h", "mhpmcounter13h",
+	"mcounteren", "mcountinhibit",
+	/* custom exposed CSRs will start with 'csr_' prefix*/
+	"csr_pma_cfg0", "csr_pma_cfg1", "csr_pma_cfg2", "csr_pma_cfg3", "csr_pma_cfg4", "csr_pma_cfg5",
+	"csr_pma_cfg6", "csr_pma_cfg7", "csr_pma_cfg8", "csr_pma_cfg9", "csr_pma_cfg10", "csr_pma_cfg11",
+	"csr_pma_cfg12", "csr_pma_cfg13", "csr_pma_cfg14", "csr_pma_cfg15", "csr_pma_addr0", "csr_pma_addr1",
+	"csr_pma_addr2", "csr_pma_addr3", "csr_pma_addr4", "csr_pma_addr5", "csr_pma_addr6", "csr_pma_addr7",
+	"csr_pma_addr8", "csr_pma_addr9", "csr_pma_addr10", "csr_pma_addr11", "csr_pma_addr12", "csr_pma_addr13",
+	"csr_pma_addr14", "csr_pma_addr15", "csr_mxstatus", "csr_mhcr", "csr_mhint", "csr_mexstatus",
+	"csr_mclicbase", "csr_mraddr", "csr_mnmicause",
+};
+
+static const char *esp32c5_ro_csrs[] = {
+	/* read-only CSRs, cannot be save/restored as the write would fail */
+	"cycle", "time", "instreth", "cycleh", "instret", "timeh",
+	"hpmcounter8", "hpmcounter9", "hpmcounter13", "hpmcounter8h", "hpmcounter9h", "hpmcounter13h",
+	"mintstatus",
+	/* custom exposed CSRs will start with 'csr_' prefix*/
+	"csr_mcpuid",
 };
 
 static int esp32c5_target_create(struct target *target, Jim_Interp *interp)
@@ -153,6 +175,8 @@ static int esp32c5_target_create(struct target *target, Jim_Interp *interp)
 	esp_riscv->print_reset_reason = &esp32c5_print_reset_reason;
 	esp_riscv->existent_csrs = esp32c5_csrs;
 	esp_riscv->existent_csr_size = ARRAY_SIZE(esp32c5_csrs);
+	esp_riscv->existent_ro_csrs = esp32c5_ro_csrs;
+	esp_riscv->existent_ro_csr_size = ARRAY_SIZE(esp32c5_ro_csrs);
 	esp_riscv->is_dram_address = esp32c5_is_idram_address;
 	esp_riscv->is_iram_address = esp32c5_is_idram_address;
 
diff --git a/src/target/espressif/esp32c6.c b/src/target/espressif/esp32c6.c
index 7261e39463..059c71f179 100644
--- a/src/target/espressif/esp32c6.c
+++ b/src/target/espressif/esp32c6.c
@@ -169,6 +169,8 @@ static int esp32c6_target_create(struct target *target, Jim_Interp *interp)
 	esp_riscv->print_reset_reason = &esp32c6_print_reset_reason;
 	esp_riscv->existent_csrs = esp32c6_csrs;
 	esp_riscv->existent_csr_size = ARRAY_SIZE(esp32c6_csrs);
+	esp_riscv->existent_ro_csrs = NULL;
+	esp_riscv->existent_ro_csr_size = 0;
 	esp_riscv->is_dram_address = esp32c6_is_idram_address;
 	esp_riscv->is_iram_address = esp32c6_is_idram_address;
 
diff --git a/src/target/espressif/esp32c61.c b/src/target/espressif/esp32c61.c
index b89748393b..32f4aabcb3 100644
--- a/src/target/espressif/esp32c61.c
+++ b/src/target/espressif/esp32c61.c
@@ -153,6 +153,8 @@ static int esp32c61_target_create(struct target *target, Jim_Interp *interp)
 	esp_riscv->print_reset_reason = &esp32c61_print_reset_reason;
 	esp_riscv->existent_csrs = esp32c61_csrs;
 	esp_riscv->existent_csr_size = ARRAY_SIZE(esp32c61_csrs);
+	esp_riscv->existent_ro_csrs = NULL;
+	esp_riscv->existent_ro_csr_size = 0;
 	esp_riscv->is_dram_address = esp32c61_is_idram_address;
 	esp_riscv->is_iram_address = esp32c61_is_idram_address;
 
diff --git a/src/target/espressif/esp32h2.c b/src/target/espressif/esp32h2.c
index 62f603f521..aa37035273 100644
--- a/src/target/espressif/esp32h2.c
+++ b/src/target/espressif/esp32h2.c
@@ -161,6 +161,8 @@ static int esp32h2_target_create(struct target *target, Jim_Interp *interp)
 	esp_riscv->print_reset_reason = &esp32h2_print_reset_reason;
 	esp_riscv->existent_csrs = esp32h2_csrs;
 	esp_riscv->existent_csr_size = ARRAY_SIZE(esp32h2_csrs);
+	esp_riscv->existent_ro_csrs = NULL;
+	esp_riscv->existent_ro_csr_size = 0;
 	esp_riscv->is_dram_address = esp32h2_is_idram_address;
 	esp_riscv->is_iram_address = esp32h2_is_idram_address;
 
diff --git a/src/target/espressif/esp32p4.c b/src/target/espressif/esp32p4.c
index 615b34b49f..9a8260a919 100644
--- a/src/target/espressif/esp32p4.c
+++ b/src/target/espressif/esp32p4.c
@@ -214,6 +214,8 @@ static int esp32p4_target_create(struct target *target, Jim_Interp *interp)
 	esp_riscv->print_reset_reason = &esp32p4_print_reset_reason;
 	esp_riscv->existent_csrs = esp32p4_csrs;
 	esp_riscv->existent_csr_size = ARRAY_SIZE(esp32p4_csrs);
+	esp_riscv->existent_ro_csrs = NULL;
+	esp_riscv->existent_ro_csr_size = 0;
 	esp_riscv->is_dram_address = esp32p4_is_idram_address;
 	esp_riscv->is_iram_address = esp32p4_is_idram_address;
 
diff --git a/src/target/espressif/esp_riscv.c b/src/target/espressif/esp_riscv.c
index ce83e06e81..c93f54a2ee 100644
--- a/src/target/espressif/esp_riscv.c
+++ b/src/target/espressif/esp_riscv.c
@@ -265,6 +265,7 @@ int esp_riscv_examine(struct target *target)
 		{ esp_riscv_fprs, ARRAY_SIZE(esp_riscv_fprs), false },
 		{ esp_riscv_csrs, ARRAY_SIZE(esp_riscv_csrs), true },
 		{ esp_riscv_ro_csrs, ARRAY_SIZE(esp_riscv_ro_csrs), false },
+		{ esp_riscv->existent_ro_csrs, esp_riscv->existent_ro_csr_size, false }, /* chip specific RO CSRs */
 		{ esp_riscv->existent_csrs, esp_riscv->existent_csr_size, true } /* chip specific CSRs */
 	};
 
diff --git a/src/target/espressif/esp_riscv.h b/src/target/espressif/esp_riscv.h
index c3ff7a36f9..75835cc03d 100644
--- a/src/target/espressif/esp_riscv.h
+++ b/src/target/espressif/esp_riscv.h
@@ -36,6 +36,8 @@ struct esp_riscv_common {
 	bool was_reset;
 	const char **existent_csrs;
 	size_t existent_csr_size;
+	const char **existent_ro_csrs;
+	size_t existent_ro_csr_size;
 	bool (*is_iram_address)(target_addr_t addr);
 	bool (*is_dram_address)(target_addr_t addr);
 };
diff --git a/src/target/riscv/encoding.h b/src/target/riscv/encoding.h
index 3ac537c377..1be21a33ce 100644
--- a/src/target/riscv/encoding.h
+++ b/src/target/riscv/encoding.h
@@ -2903,7 +2903,8 @@
 #define CSR_SSCRATCHCSWL 0x149
 #define CSR_MTVT 0x307
 #define CSR_MNXTI 0x345
-#define CSR_MINTSTATUS 0x346
+#define CSR_MINTSTATUS 0xfb1
+#define CSR_MINTTHRESH 0x347
 #define CSR_MSCRATCHCSW 0x348
 #define CSR_MSCRATCHCSWL 0x349
 #define CSR_MSTATUS 0x300
@@ -4661,6 +4662,7 @@ DECLARE_CSR(sscratchcswl, CSR_SSCRATCHCSWL)
 DECLARE_CSR(mtvt, CSR_MTVT)
 DECLARE_CSR(mnxti, CSR_MNXTI)
 DECLARE_CSR(mintstatus, CSR_MINTSTATUS)
+DECLARE_CSR(mintthresh, CSR_MINTTHRESH)
 DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW)
 DECLARE_CSR(mscratchcswl, CSR_MSCRATCHCSWL)
 DECLARE_CSR(mstatus, CSR_MSTATUS)
diff --git a/tcl/target/esp32c5.cfg b/tcl/target/esp32c5.cfg
index a2d0643fe9..19f4846566 100644
--- a/tcl/target/esp32c5.cfg
+++ b/tcl/target/esp32c5.cfg
@@ -100,42 +100,43 @@ proc esp32c5_memprot_is_enabled { } {
 
 create_esp_target $_ESP_ARCH
 
-# TODO: OCD-980
-# $_TARGETNAME_0 riscv expose_csrs 2016=mpcer
-# $_TARGETNAME_0 riscv expose_csrs 2017=mpcmr
-# $_TARGETNAME_0 riscv expose_csrs 2018=mpccr
-# $_TARGETNAME_0 riscv expose_csrs 2051=cpu_gpio_oen
-# $_TARGETNAME_0 riscv expose_csrs 2052=cpu_gpio_in
-# $_TARGETNAME_0 riscv expose_csrs 2053=cpu_gpio_out
-# $_TARGETNAME_0 riscv expose_csrs 3008=pma_cfg0
-# $_TARGETNAME_0 riscv expose_csrs 3009=pma_cfg1
-# $_TARGETNAME_0 riscv expose_csrs 3010=pma_cfg2
-# $_TARGETNAME_0 riscv expose_csrs 3011=pma_cfg3
-# $_TARGETNAME_0 riscv expose_csrs 3012=pma_cfg4
-# $_TARGETNAME_0 riscv expose_csrs 3013=pma_cfg5
-# $_TARGETNAME_0 riscv expose_csrs 3014=pma_cfg6
-# $_TARGETNAME_0 riscv expose_csrs 3015=pma_cfg7
-# $_TARGETNAME_0 riscv expose_csrs 3016=pma_cfg8
-# $_TARGETNAME_0 riscv expose_csrs 3017=pma_cfg9
-# $_TARGETNAME_0 riscv expose_csrs 3018=pma_cfg10
-# $_TARGETNAME_0 riscv expose_csrs 3019=pma_cfg11
-# $_TARGETNAME_0 riscv expose_csrs 3020=pma_cfg12
-# $_TARGETNAME_0 riscv expose_csrs 3021=pma_cfg13
-# $_TARGETNAME_0 riscv expose_csrs 3022=pma_cfg14
-# $_TARGETNAME_0 riscv expose_csrs 3023=pma_cfg15
-# $_TARGETNAME_0 riscv expose_csrs 3024=pma_addr0
-# $_TARGETNAME_0 riscv expose_csrs 3025=pma_addr1
-# $_TARGETNAME_0 riscv expose_csrs 3026=pma_addr2
-# $_TARGETNAME_0 riscv expose_csrs 3027=pma_addr3
-# $_TARGETNAME_0 riscv expose_csrs 3028=pma_addr4
-# $_TARGETNAME_0 riscv expose_csrs 3029=pma_addr5
-# $_TARGETNAME_0 riscv expose_csrs 3030=pma_addr6
-# $_TARGETNAME_0 riscv expose_csrs 3031=pma_addr7
-# $_TARGETNAME_0 riscv expose_csrs 3032=pma_addr8
-# $_TARGETNAME_0 riscv expose_csrs 3033=pma_addr9
-# $_TARGETNAME_0 riscv expose_csrs 3034=pma_addr10
-# $_TARGETNAME_0 riscv expose_csrs 3035=pma_addr11
-# $_TARGETNAME_0 riscv expose_csrs 3036=pma_addr12
-# $_TARGETNAME_0 riscv expose_csrs 3037=pma_addr13
-# $_TARGETNAME_0 riscv expose_csrs 3038=pma_addr14
-# $_TARGETNAME_0 riscv expose_csrs 3039=pma_addr15
+$_TARGETNAME_0 riscv expose_csrs 848=mclicbase
+$_TARGETNAME_0 riscv expose_csrs 1984=mxstatus
+$_TARGETNAME_0 riscv expose_csrs 1985=mhcr
+$_TARGETNAME_0 riscv expose_csrs 1989=mhint
+$_TARGETNAME_0 riscv expose_csrs 2016=mraddr
+$_TARGETNAME_0 riscv expose_csrs 2017=mexstatus
+$_TARGETNAME_0 riscv expose_csrs 2018=mnmicause
+$_TARGETNAME_0 riscv expose_csrs 3008=pma_cfg0
+$_TARGETNAME_0 riscv expose_csrs 3009=pma_cfg1
+$_TARGETNAME_0 riscv expose_csrs 3010=pma_cfg2
+$_TARGETNAME_0 riscv expose_csrs 3011=pma_cfg3
+$_TARGETNAME_0 riscv expose_csrs 3012=pma_cfg4
+$_TARGETNAME_0 riscv expose_csrs 3013=pma_cfg5
+$_TARGETNAME_0 riscv expose_csrs 3014=pma_cfg6
+$_TARGETNAME_0 riscv expose_csrs 3015=pma_cfg7
+$_TARGETNAME_0 riscv expose_csrs 3016=pma_cfg8
+$_TARGETNAME_0 riscv expose_csrs 3017=pma_cfg9
+$_TARGETNAME_0 riscv expose_csrs 3018=pma_cfg10
+$_TARGETNAME_0 riscv expose_csrs 3019=pma_cfg11
+$_TARGETNAME_0 riscv expose_csrs 3020=pma_cfg12
+$_TARGETNAME_0 riscv expose_csrs 3021=pma_cfg13
+$_TARGETNAME_0 riscv expose_csrs 3022=pma_cfg14
+$_TARGETNAME_0 riscv expose_csrs 3023=pma_cfg15
+$_TARGETNAME_0 riscv expose_csrs 3024=pma_addr0
+$_TARGETNAME_0 riscv expose_csrs 3025=pma_addr1
+$_TARGETNAME_0 riscv expose_csrs 3026=pma_addr2
+$_TARGETNAME_0 riscv expose_csrs 3027=pma_addr3
+$_TARGETNAME_0 riscv expose_csrs 3028=pma_addr4
+$_TARGETNAME_0 riscv expose_csrs 3029=pma_addr5
+$_TARGETNAME_0 riscv expose_csrs 3030=pma_addr6
+$_TARGETNAME_0 riscv expose_csrs 3031=pma_addr7
+$_TARGETNAME_0 riscv expose_csrs 3032=pma_addr8
+$_TARGETNAME_0 riscv expose_csrs 3033=pma_addr9
+$_TARGETNAME_0 riscv expose_csrs 3034=pma_addr10
+$_TARGETNAME_0 riscv expose_csrs 3035=pma_addr11
+$_TARGETNAME_0 riscv expose_csrs 3036=pma_addr12
+$_TARGETNAME_0 riscv expose_csrs 3037=pma_addr13
+$_TARGETNAME_0 riscv expose_csrs 3038=pma_addr14
+$_TARGETNAME_0 riscv expose_csrs 3039=pma_addr15
+$_TARGETNAME_0 riscv expose_csrs 4032=mcpuid