Increase Clock input

[AnouarITI]

Hi,
Did anyone try to increase the input clock from 100MHz to 200MHz, for example, during the bitstream generation? It seems that the the PS clock output is never the same as requested. Any help or hints here?

[bo3z]

Which backend are you using? In Vivado and Vitis it should work.

Also, where are you checking the clock period? For Vivado / Vitis backend (i.e. AMD FPGAs), you need to run the full place and route to check if timing is met and to make use of the clock period. You can achieve this by modifying the tcl script when doing export. Let me know which backend you are using and how you are reporting the observed issue and maybe I can point which parts of the script you can modify to get the full timing analysis.

[AnouarITI]

I am using VivadoAccelerator Backend to generate a bitstream for ZCU104 (I added the support myself). I can see that the timing are met when using the default clock of 100 MHz for PL output (TNS and WNS are met). I would appreciate your telling me how to edit the design.tcl file to increase the output clock to 150 or 200 MHz (of course depending on the model complexity etc.)

[bo3z]

This is the line of code where the value is parsed from the config to the tcl scripts in the VivadoAccelerator backend:

hls4ml/hls4ml/writer/vivado_accelerator_writer.py

Line 391 in afed23b

f.write('variable clock_period\n')

.

You should be able to set in the config. The variables is ClockPeriod, so you can do something like hls_config['Model']['ClockPeriod'] = 5 or hls_config['ClockPeriod'] = 5 (I don't remember at what granularity this is). Otherwise you could go straight to the tcl file and modify the line of code that says set clock_period; it should be in the file project.tcl.

[AnouarITI]

There may be a misunderstanding. The solution you mentioned earlier is for the HLS synthesis. However, I meant the bitstream generation at a later step. For instance, in ZCU102 axi_stream_design.tcl file line 34-37 the pl_clk0 is set to 99 MHz, which i assume is based on the clock output of the PS. How can I increase that Frequency. is it even possible?

[bo3z]

It seems to be hard-coded in hls4ml, which is less than ideal. Have you tried changing the file itself to the target value (e.g. 150 or 200). Then this file be copied when you run hls4ml conversion and compilation, so it should pick up the new value. I haven't worked much with the Accelerator backend, so maybe someone else can also help.