bit file generation, part 7a

[parthasarathi1234]

I am building the MNIST dataset to deploy on the Pynq-Z2 board using Vitis 2024.1. However, I am encountering an error during bitstream generation: "Vivado HLS not found." What changes do I need to make to resolve this issue?

[bo3z]

The Vivado accelerator backend requires Vivado HLS (which was deprecated sometime around 2020 and replaced with Vitis HLS). In general, you have 3 options:

1. Install Vivado HLS (and make sure it's included in the path) and keep using the VivadoAccelerator backend
2. Use the "normal" backend (either Vivado or Vitis) to generate an IP core and integrate it into your application by hand, i.e. write some code to handle data movement etc. (this is exactly what the accelerator backends do, they handle data movement between the host CPU and the FPGA board)
3. Try out the experimental support for VitisAccelerator, in PR Vitis accelerator #991 (this has not been merged yet, so it might be buggy / work in progress)

[parthasarathi1234]

Thank you @bo3z.