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<!DOCTYPE html>
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<span class="post-meta-item-text">Posted on</span>
<time title="Created: 2020-06-28 13:13:37" itemprop="dateCreated datePublished" datetime="2020-06-28T13:13:37+08:00">2020-06-28</time>
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<a href="/categories/%E6%9D%82%E4%B8%83%E6%9D%82%E5%85%AB/" itemprop="url" rel="index"><span itemprop="name">杂七杂八</span></a>
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<span class="post-meta-item-text">Symbols count in article: </span>
<span>311</span>
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<span class="post-meta-item" title="Reading time">
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<span class="post-meta-item-text">Reading time ≈</span>
<span>1 mins.</span>
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<p>Welcome to my blog!</p>
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猫咖拍的可爱照骗～
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<p>我的文章将有以下几个分类「尽管学过信息组织，还是对分类感到非常头疼哈哈哈哈」</p>
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<a href="/2023/01/22/3-13-ramulator/" class="post-title-link" itemprop="url">Paper Review - Ramulator</a>
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<span class="post-meta-item-text">Posted on</span>
<time title="Created: 2023-01-23 00:08:25" itemprop="dateCreated datePublished" datetime="2023-01-23T00:08:25+08:00">2023-01-23</time>
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<a href="/categories/%E7%A7%91%E7%A0%94/" itemprop="url" rel="index"><span itemprop="name">科研</span></a>
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<span class="post-meta-item-text">Symbols count in article: </span>
<span>1.9k</span>
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<span class="post-meta-item-text">Reading time ≈</span>
<span>3 mins.</span>
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<p><a target="_blank" rel="noopener" href="https://people.inf.ethz.ch/omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf">Ramulator: A Fast and Extensible DRAM Simulator 🔗</a></p>
<blockquote>
<p>Ramulator is a fast and cycle-accurate DRAM simulator that is built for extensibility and supports a wide array of DRAM standards such as DDR3/4, LPDDR3/4, GDDR5, WIO1/2, HBM, and academic proposals such as SALP, AL-DRAM, TLDRAM, RowClone, and SARP. It’s 2.5x faster than the next fastest simulator and is released under a permissive BSD license.</p>
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<a href="/2023/01/22/4-3-bliss/" class="post-title-link" itemprop="url">Paper Review - BLISS</a>
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<time title="Created: 2023-01-22 17:29:00" itemprop="dateCreated datePublished" datetime="2023-01-22T17:29:00+08:00">2023-01-22</time>
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<i class="far fa-file-word"></i>
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<span class="post-meta-item-text">Symbols count in article: </span>
<span>2.4k</span>
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<span class="post-meta-item" title="Reading time">
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<span class="post-meta-item-text">Reading time ≈</span>
<span>4 mins.</span>
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<p><a target="_blank" rel="noopener" href="https://people.inf.ethz.ch/omutlu/pub/bliss-memory-scheduler_ieee-tpds16.pdf">BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling 🔗</a></p>
<blockquote>
<p>This paper introduces a new memory scheduler, called Blacklisting Memory Scheduler (BLISS), which separates applications into two groups, one containing applications that are vulnerable to interference and another containing applications that cause interference. It aims to achieve high system performance and fairness with low hardware cost and complexity. The design of BLISS is based on two observations, it is sufficient to separate applications into two groups instead of ranking them individually, and this grouping can be efficiently performed by counting the number of consecutive requests served from each application. The evaluation shows that BLISS performs better than previous schedulers while reducing the hardware complexity.</p>
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<a href="/2023/01/20/4-4-fst/" class="post-title-link" itemprop="url">Paper Review - FST</a>
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<time title="Created: 2023-01-20 11:54:14" itemprop="dateCreated datePublished" datetime="2023-01-20T11:54:14+08:00">2023-01-20</time>
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<p><a target="_blank" rel="noopener" href="https://people.inf.ethz.ch/omutlu/pub/fst_asplos10.pdf">Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems 🔗</a></p>
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<p>This paper proposes a new approach, Fairness via Source Throttling (FST), to provide fairness in the entire shared memory system of a chip-multiprocessor (CMP) system by eliminating the need for developing fairness mechanisms for each individual resource. FST ensures fairness decisions are made in tandem in the entire memory system, enforces thread priorities/weights, and allows system software to enforce different fairness objectives and fairness-performance tradeoffs in the memory system. The evaluations show that FST provides the best system fairness and performance compared to four systems with no fairness control and with state-of-the-art fairness mechanisms.</p>
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<a href="/2023/01/17/3-2-pcm/" class="post-title-link" itemprop="url">Paper Review - PCM</a>
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<time title="Created: 2023-01-17 14:13:14" itemprop="dateCreated datePublished" datetime="2023-01-17T14:13:14+08:00">2023-01-17</time>
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<p><a target="_blank" rel="noopener" href="https://people.inf.ethz.ch/omutlu/pub/pcm_isca09.pdf">Architecting Phase Change Memory as a Scalable DRAM Alternative 🔗</a></p>
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<p>The authors propose architectural enhancements to make Phase Change Memory (PCM) competitive with DRAM as a memory scaling alternative. The enhancements address limitations such as long latencies, high energy writes, and finite endurance. These enhancements result in significant improvements in performance and endurance.</p>
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<a href="/2023/01/16/3-1-rlmc/" class="post-title-link" itemprop="url">Paper Review - RLMC</a>
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<time title="Created: 2023-01-17 01:40:29" itemprop="dateCreated datePublished" datetime="2023-01-17T01:40:29+08:00">2023-01-17</time>
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<p><a target="_blank" rel="noopener" href="https://safari.ethz.ch/review/architecture22/doc.php/comparch-fs22-paper46.pdf">Self-Optimizing Memory Controllers: A Reinforcement Learning Approach 🔗</a></p>
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<p>The authors propose a new memory controller design that uses reinforcement learning to optimize performance and bandwidth utilization in chip multiprocessors. The controller adapts its scheduling policies on the fly to improve performance and results show significant improvement compared to current state-of-the-art controllers.</p>
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<time title="Created: 2023-01-16 22:57:54" itemprop="dateCreated datePublished" datetime="2023-01-16T22:57:54+08:00">2023-01-16</time>
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<p><a target="_blank" rel="noopener" href="https://safari.ethz.ch/review/architecture22/doc.php/comparch-fs22-paper26.pdf">RAIDR: Retention-Aware Intelligent DRAM Refresh 🔗</a></p>
<blockquote>
<p>This work proposed Retention-Aware Intelligent DRAM Refresh (RAIDR), a low-cost mechanism that can identify and skip unnecessary refreshes using knowledge of cell retention times. Our key idea is to group DRAM rows into retention time bins and apply a different refresh rate to each bin.</p>
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<p><a target="_blank" rel="noopener" href="https://safari.ethz.ch/review/architecture22/doc.php/comparch-fs22-paper48.pdf">Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture 🔗</a></p>
<blockquote>
<p>This work introduced Tiered-Latency DRAM (TL-DRAM), a DRAM architecture that provides both low latency and low cost-per-bit. This work presented mechanisms that take advantage of the TL-DRAM substrate by using its low-latency segment as a hardware-managed cache. It is shown that TL-DRAM significantly improve both system performance and energy efficiency across a variety of systems and workloads.</p>
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<p><a target="_blank" rel="noopener" href="https://safari.ethz.ch/review/architecture22/doc.php/comparch-fs22-paper25.pdf">BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows 🔗</a></p>
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<p>This work introduced Blockhammer, a rowhammer mitigation mechanism of both scalability with worsening rowhammer vulnerability and compatibility with commodity DRAM chips.</p>
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