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from AD's engineerzone
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Conversely, if you are running at 96 kHz, the MCLK frequency itself remains unchanged, and you're simply doubling the rate of the DSP core and converter filters. In that case, you only need to change a register setting, and no hardware changes are required.
In summary, the ADC_RES values for 48 kHz and 96 kHz should be the same, because the core clock frequencies are the same in both cases.
In retrospect, the datasheet does a poor job of explaining this. I will make this into a FAQ on EngineerZone in order to help clear up any confusion on the subject.
so the ADC is not running faster, it could be that the decimator is being adjusted, by my guess is that the decimator and postfilter is fixed and the 96k this signal is just doubly sampled.
the noise floor plot of the DAC out of a signal sampled by the ADC shows a 0-20khz elevated floor, then a lower DAC floor from 20-100khz and a residue at 48khz even when the processor is running at 96kHz.
(no source provided yet)
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