Avx512 and AMD (Zen 4)

[mert-kurttutan]

Hi,

From the API docs on crate (https://docs.rs/raw-cpuid/latest/raw_cpuid/struct.ExtendedFeatures.html#method.has_avx512f)

It says that Avx512f is not available (reserved) for AMD. But on wikichip.org, it is available for AMD Zen 4
https://en.wikichip.org/wiki/x86/avx-512

[gz]

Yes the crate is currently not up to date for the latest AMD cpus. Feel free to submit a patch that updates the documentation

[mert-kurttutan]

Great!
Out of curiosity, why did you decide avx512f bit was preserved for AMD?
Is there a documentation for this? ( because I could not find one )

[gz]

I think in the old AMD
documentation it used to be marked as reserved, but it
couldve been just a bug.

[mert-kurttutan]

For documentation purposes: two relevant links below (most up-to-update I can find) from AMD
https://www.amd.com/system/files/documents/4th-gen-epyc-processor-architecture-white-paper.pdf
https://community.amd.com/t5/epyc-discussions/amd64-architecture-programmer-s-manual-zen4/td-p/548184

As stated in the second link, AMD manuals does not mention anything about any of the AVX512 ISA, only the white paper mentions it.

[mert-kurttutan]

There is also a typo in one of the method names on extended features:
https://docs.rs/raw-cpuid/latest/raw_cpuid/struct.ExtendedFeatures.html#method.has_av512vbmi2

It should be avx512vbmi2 instead of av512vbmi2, I think.

I think we should fix with deprecated attribute.

[mert-kurttutan]

Also, the methods for 2 methods are not present (along with some others) are absent for Avx512 extension

• Avx512_bf16, Avx512_fp16,

I can put PR for these 2 since they are of interest to me.

[mert-kurttutan]

Also:
I just ran some quick test app to be absolutely sure, everything works as expected on Zen4 (C7a Instance from AWS):
Here the output of lscpu and my rust binary using raw_cpuid

lscpu:
fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl 
nonstop_tsc cpuid extd_apicid aperfmperf tsc_known_freq pni pclmulqdq monitor ssse3 fma cx16 pcid sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand hypervisor 
lahf_lm cr8_legacy abm sse4a misalignsse 3dnowprefetch topoext perfctr_core ssbd perfmon_v2 ibrs ibpb stibp ibrs_enhanced vmmcall fsgsbase bmi1 avx2 smep bmi2 invpcid 
avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves avx512_bf16 clzero xsaveerptr rdpru
wbnoinvd arat avx512vbmi pku ospke avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg avx512_vpopcntdq rdpid flush_l1d

Raw_cpuid Hello_world for Avx512:
Hello, world!
Avx512f is detected
Avx512vbmi2 is detected
Avx512ifma is detected
Avx512bitalg is detected
Avx512bw is detected
Avx512cd is detected
Avx512dq is detected
Avx512vl is detected
Avx512f is detected
Avx512vnni is detected
Avx512pocntdq is detected

[mert-kurttutan]

While preparing pr for new feature detections, I realized cargo test gives error since phf is dev dependency on only unix.

It works fine on windows as far as the tests are concerned.

Is there a reason why it is used only on unix systems?

[gz]

Agreed this seems like a bug to me. Feel free to move it in a general dev dependency section.

[mert-kurttutan]

While prepare PR for sub-leaf ecx=1,
I think I found an inconsistency between Wikipedia and intel manual about bit fields
The first bit of EAX=7, ECX=1: Extended Features on Wikipedia is sha512 and on Intel manual (latest version June 2024) it is reserved (I could not find info on AMD manual).
Do you have any insight on this issue?

For the time being, I am following Intel Manual

[gz]

I don't but following the Intel Manual seems like the right choice.

[mert-kurttutan]

I just found that it is mentioned in the manuals for future features:
https://www.intel.com/content/www/us/en/content-details/826290/intel-architecture-instruction-set-extensions-programming-reference.html
Searched for SHA512, and found it. It seems that they will be released for CPUs coming on 2nd of half of 2024.
How should I continue with regards to future features ?

[gz]

Yea I think that's fine if you want to put it in then if it's described in an Intel PDF

[mert-kurttutan]

I decided to put only comment regarding future features since it is not guaranteed that these features will be available according to Intel Manual.
And there is no use of it atm (unless you have a time machine :) )

[mert-kurttutan]

closed by #181 and #182