From de81cf01e097f33916c53a90fc621baeb8060e64 Mon Sep 17 00:00:00 2001 From: Ben Gamari Date: Fri, 24 Oct 2014 15:56:18 -0400 Subject: [PATCH 1/3] Replace GPIO with Gpio --- apps/app_blink.rs | 2 +- apps/app_blink_k20.rs | 4 +- apps/app_blink_k20_isr.rs | 4 +- apps/app_uart.rs | 2 +- src/zinc/drivers/dht22.rs | 6 +-- src/zinc/drivers/lcd/c12332.rs | 8 ++-- src/zinc/drivers/lcd/ili9341.rs | 8 ++-- src/zinc/hal/k20/pin.rs | 66 ++++++++++++++-------------- src/zinc/hal/lpc17xx/pin.rs | 50 ++++++++++----------- src/zinc/hal/lpc17xx/pin_pt.rs | 4 +- src/zinc/hal/lpc17xx/platformtree.rs | 2 +- src/zinc/hal/pin.rs | 10 ++--- src/zinc/hal/stm32f4/gpio.rs | 4 +- src/zinc/hal/stm32f4/pin.rs | 2 +- src/zinc/hal/stm32l1/pin.rs | 6 +-- 15 files changed, 89 insertions(+), 89 deletions(-) diff --git a/apps/app_blink.rs b/apps/app_blink.rs index c53256c8..ac0d15c3 100644 --- a/apps/app_blink.rs +++ b/apps/app_blink.rs @@ -46,7 +46,7 @@ platformtree!( ) fn run(args: &pt::run_args) { - use zinc::hal::pin::GPIO; + use zinc::hal::pin::Gpio; use zinc::hal::timer::Timer; args.led1.set_high(); diff --git a/apps/app_blink_k20.rs b/apps/app_blink_k20.rs index 27da4ece..baa4d6fa 100644 --- a/apps/app_blink_k20.rs +++ b/apps/app_blink_k20.rs @@ -7,7 +7,7 @@ extern crate zinc; use core::option::Some; use zinc::hal::k20::{pin, watchdog}; -use zinc::hal::pin::GPIO; +use zinc::hal::pin::{Gpio, High, Low}; use zinc::hal::cortex_m4::systick; /// Wait the given number of SysTick ticks @@ -34,7 +34,7 @@ pub unsafe fn main() { watchdog::init(watchdog::Disabled); // Pins for MC HCK (http://www.mchck.org/) - let led1 = pin::Pin::new(pin::PortB, 16, pin::GPIO, Some(zinc::hal::pin::Out)); + let led1 = pin::Pin::new(pin::PortB, 16, pin::Gpio, Some(zinc::hal::pin::Out)); systick::setup(systick::ten_ms().unwrap_or(480000)); systick::enable(); diff --git a/apps/app_blink_k20_isr.rs b/apps/app_blink_k20_isr.rs index 88679332..25e10761 100644 --- a/apps/app_blink_k20_isr.rs +++ b/apps/app_blink_k20_isr.rs @@ -10,7 +10,7 @@ use core::intrinsics::volatile_load; use core::option::Some; use zinc::hal::k20::{pin, watchdog}; -use zinc::hal::pin::GPIO; +use zinc::hal::pin::Gpio; use zinc::hal::cortex_m4::systick; use zinc::util::support::wfi; @@ -35,7 +35,7 @@ pub fn main() { watchdog::init(watchdog::Disabled); // Pins for MC HCK (http://www.mchck.org/) - let led1 = pin::Pin::new(pin::PortB, 16, pin::GPIO, Some(zinc::hal::pin::Out)); + let led1 = pin::Pin::new(pin::PortB, 16, pin::Gpio, Some(zinc::hal::pin::Out)); systick::setup(systick::ten_ms().unwrap_or(480000)); systick::enable(); diff --git a/apps/app_uart.rs b/apps/app_uart.rs index d01fb938..55660ba7 100644 --- a/apps/app_uart.rs +++ b/apps/app_uart.rs @@ -60,7 +60,7 @@ platformtree!( fn run(args: &pt::run_args) { use zinc::drivers::chario::CharIO; use zinc::hal::timer::Timer; - use zinc::hal::pin::GPIO; + use zinc::hal::pin::Gpio; args.uart.puts("Hello, world\n"); diff --git a/src/zinc/drivers/dht22.rs b/src/zinc/drivers/dht22.rs index 9c975f2f..0c1b5aff 100644 --- a/src/zinc/drivers/dht22.rs +++ b/src/zinc/drivers/dht22.rs @@ -18,7 +18,7 @@ use core::iter::range; use core::option::{Option, Some, None}; -use hal::pin::{GPIO, Low, High, In, Out, GPIOLevel}; +use hal::pin::{Gpio, Low, High, In, Out, GpioLevel}; use hal::timer::Timer; /// Basic DHT22 driver ported over from Arduino example. @@ -34,7 +34,7 @@ pub struct Measurements { pub temperature: f32, } -impl<'a, T: Timer, P: GPIO> DHT22<'a, T, P> { +impl<'a, T: Timer, P: Gpio> DHT22<'a, T, P> { /// Creates a new DHT22 driver based on I/O GPIO and a timer with 10us resolution. pub fn new(timer: &'a T, gpio: &'a P) -> DHT22<'a, T, P> { DHT22 { @@ -110,7 +110,7 @@ impl<'a, T: Timer, P: GPIO> DHT22<'a, T, P> { } } - fn wait_while(&self, level: GPIOLevel, timeout: uint) -> bool { + fn wait_while(&self, level: GpioLevel, timeout: uint) -> bool { for _ in range(0, timeout / 10) { self.timer.wait_us(10); if self.gpio.level() != level { diff --git a/src/zinc/drivers/lcd/c12332.rs b/src/zinc/drivers/lcd/c12332.rs index e00e5efe..95e1d52a 100644 --- a/src/zinc/drivers/lcd/c12332.rs +++ b/src/zinc/drivers/lcd/c12332.rs @@ -32,7 +32,7 @@ use super::font_small_7; use super::LCD; use drivers::chario::CharIO; use hal::timer::Timer; -use hal::pin::GPIO; +use hal::pin::Gpio; use hal::spi::SPI; /// C12332 driver. @@ -51,7 +51,7 @@ pub struct C12332<'a, S:'a, T:'a, P:'a> { char_y: cell::Cell, } -impl<'a, S: SPI, T: Timer, P: GPIO> C12332<'a, S, T, P> { +impl<'a, S: SPI, T: Timer, P: Gpio> C12332<'a, S, T, P> { /// Creates a new C12332 driver instance. pub fn new(spi: &'a S, timer: &'a T, dc: &'a P, cs: &'a P, reset: &'a P) -> C12332<'a, S, T, P> { @@ -183,7 +183,7 @@ impl<'a, S: SPI, T: Timer, P: GPIO> C12332<'a, S, T, P> { } } -impl<'a, S: SPI, T: Timer, P: GPIO> LCD for C12332<'a, S, T, P> { +impl<'a, S: SPI, T: Timer, P: Gpio> LCD for C12332<'a, S, T, P> { fn flush(&self) { let mut i: uint = 0; @@ -239,7 +239,7 @@ impl<'a, S: SPI, T: Timer, P: GPIO> LCD for C12332<'a, S, T, P> { } } -impl<'a, S: SPI, T: Timer, P: GPIO> CharIO for C12332<'a, S, T, P> { +impl<'a, S: SPI, T: Timer, P: Gpio> CharIO for C12332<'a, S, T, P> { fn putc(&self, value: char) { let height: u32 = 32; if value == '\n' { diff --git a/src/zinc/drivers/lcd/ili9341.rs b/src/zinc/drivers/lcd/ili9341.rs index 19183f2b..c4c9f5c5 100644 --- a/src/zinc/drivers/lcd/ili9341.rs +++ b/src/zinc/drivers/lcd/ili9341.rs @@ -20,7 +20,7 @@ use core::iter::range; use super::LCD; use drivers::chario::CharIO; use hal::timer::Timer; -use hal::pin::GPIO; +use hal::pin::Gpio; use hal::spi::SPI; /// ILI9341 driver. @@ -33,7 +33,7 @@ pub struct ILI9341<'a, S:'a, T:'a, P:'a> { // backlight: gpio::OutGPIO, } -impl<'a, S: SPI, T: Timer, P: GPIO> ILI9341<'a, S, T, P> { +impl<'a, S: SPI, T: Timer, P: Gpio> ILI9341<'a, S, T, P> { /// Creates a new ILI9341 driver instance. pub fn new(spi: &'a S, timer: &'a T, dc: &'a P, cs: &'a P, reset: &'a P) -> ILI9341<'a, S, T, P> { @@ -295,7 +295,7 @@ impl<'a, S: SPI, T: Timer, P: GPIO> ILI9341<'a, S, T, P> { } } -impl<'a, S: SPI, T: Timer, P: GPIO> LCD for ILI9341<'a, S, T, P> { +impl<'a, S: SPI, T: Timer, P: Gpio> LCD for ILI9341<'a, S, T, P> { fn clear(&self) { self.do_clear(); } @@ -305,7 +305,7 @@ impl<'a, S: SPI, T: Timer, P: GPIO> LCD for ILI9341<'a, S, T, P> { } } -impl<'a, S: SPI, T: Timer, P: GPIO> CharIO for ILI9341<'a, S, T, P> { +impl<'a, S: SPI, T: Timer, P: Gpio> CharIO for ILI9341<'a, S, T, P> { fn putc(&self, _: char) { // TODO(farcaller): implement } diff --git a/src/zinc/hal/k20/pin.rs b/src/zinc/hal/k20/pin.rs index 9c3c6c9f..accb18d0 100644 --- a/src/zinc/hal/k20/pin.rs +++ b/src/zinc/hal/k20/pin.rs @@ -47,7 +47,7 @@ pub enum Port { #[allow(missing_doc)] pub enum Function { Analog = 0, - GPIO = 1, + Gpio = 1, AltFunction2 = 2, AltFunction3 = 3, AltFunction4 = 4, @@ -81,7 +81,7 @@ pub enum SlewRate { impl Pin { /// Create and setup a Pin. pub fn new(port: Port, pin_index: u8, function: Function, - gpiodir: Option<::hal::pin::GPIODirection>) -> Pin { + gpiodir: Option<::hal::pin::GpioDirection>) -> Pin { let pin = Pin { port: port, pin: pin_index, @@ -93,7 +93,7 @@ impl Pin { } fn setup_regs(&self, function: Function, - gpiodir: Option<::hal::pin::GPIODirection>, + gpiodir: Option<::hal::pin::GpioDirection>, pull: PullConf, drive_strength: DriveStrength, slew_rate: SlewRate, filter: bool, open_drain: bool) { // enable port clock @@ -122,34 +122,34 @@ impl Pin { .set_dse(dse) .set_mux(function as u32); - if function == GPIO { - (self as &::hal::pin::GPIO).set_direction(gpiodir.unwrap()); + if function == Gpio { + (self as &::hal::pin::Gpio).set_direction(gpiodir.unwrap()); } } - fn gpioreg(&self) -> &'static reg::GPIO { + fn gpioreg(&self) -> &'static reg::Gpio { match self.port { - PortA => ®::GPIOA, - PortB => ®::GPIOB, - PortC => ®::GPIOC, - PortD => ®::GPIOD, - PortE => ®::GPIOE, + PortA => ®::GpioA, + PortB => ®::GpioB, + PortC => ®::GpioC, + PortD => ®::GpioD, + PortE => ®::GpioE, } } - fn pcr(&self) -> &'static reg::PORT_pcr { - let port: ®::PORT = match self.port { - PortA => ®::PORTA, - PortB => ®::PORTB, - PortC => ®::PORTC, - PortD => ®::PORTD, - PortE => ®::PORTE, + fn pcr(&self) -> &'static reg::Port_pcr { + let port: ®::Port = match self.port { + PortA => ®::PortA, + PortB => ®::PortB, + PortC => ®::PortC, + PortD => ®::PortD, + PortE => ®::PortE, }; return &port.pcr[self.pin as uint]; } } -impl ::hal::pin::GPIO for Pin { +impl ::hal::pin::Gpio for Pin { /// Sets output GPIO value to high. fn set_high(&self) { self.gpioreg().psor.set_ptso(self.pin as uint, true); @@ -161,7 +161,7 @@ impl ::hal::pin::GPIO for Pin { } /// Returns input GPIO level. - fn level(&self) -> ::hal::pin::GPIOLevel { + fn level(&self) -> ::hal::pin::GpioLevel { let reg = self.gpioreg(); match reg.pdir.pdi(self.pin as uint) { false => ::hal::pin::Low, @@ -170,7 +170,7 @@ impl ::hal::pin::GPIO for Pin { } /// Sets output GPIO direction. - fn set_direction(&self, new_mode: ::hal::pin::GPIODirection) { + fn set_direction(&self, new_mode: ::hal::pin::GpioDirection) { let reg = self.gpioreg(); let val = match new_mode { ::hal::pin::In => reg::INPUT, @@ -185,7 +185,7 @@ pub mod reg { use util::volatile_cell::VolatileCell; use core::ops::Drop; - ioregs!(PORT = { + ioregs!(Port = { /// Port control register 0x0 => reg32 pcr[32] { @@ -236,14 +236,14 @@ pub mod reg { }) extern { - #[link_name="k20_iomem_PORTA"] pub static PORTA: PORT; - #[link_name="k20_iomem_PORTB"] pub static PORTB: PORT; - #[link_name="k20_iomem_PORTC"] pub static PORTC: PORT; - #[link_name="k20_iomem_PORTD"] pub static PORTD: PORT; - #[link_name="k20_iomem_PORTE"] pub static PORTE: PORT; + #[link_name="k20_iomem_PORTA"] pub static PortA: Port; + #[link_name="k20_iomem_PORTB"] pub static PortB: Port; + #[link_name="k20_iomem_PORTC"] pub static PortC: Port; + #[link_name="k20_iomem_PORTD"] pub static PortD: Port; + #[link_name="k20_iomem_PORTE"] pub static PortE: Port; } - ioregs!(GPIO = { + ioregs!(Gpio = { 0x0 => reg32 pdo { //! port data output register 0..31 => pdo } @@ -273,10 +273,10 @@ pub mod reg { }) extern { - #[link_name="k20_iomem_GPIOA"] pub static GPIOA: GPIO; - #[link_name="k20_iomem_GPIOB"] pub static GPIOB: GPIO; - #[link_name="k20_iomem_GPIOC"] pub static GPIOC: GPIO; - #[link_name="k20_iomem_GPIOD"] pub static GPIOD: GPIO; - #[link_name="k20_iomem_GPIOE"] pub static GPIOE: GPIO; + #[link_name="k20_iomem_GPIOA"] pub static GpioA: Gpio; + #[link_name="k20_iomem_GPIOB"] pub static GpioB: Gpio; + #[link_name="k20_iomem_GPIOC"] pub static GpioC: Gpio; + #[link_name="k20_iomem_GPIOD"] pub static GpioD: Gpio; + #[link_name="k20_iomem_GPIOE"] pub static GpioE: Gpio; } } diff --git a/src/zinc/hal/lpc17xx/pin.rs b/src/zinc/hal/lpc17xx/pin.rs index 286aa736..f4b75817 100644 --- a/src/zinc/hal/lpc17xx/pin.rs +++ b/src/zinc/hal/lpc17xx/pin.rs @@ -39,7 +39,7 @@ pub enum Port { #[deriving(PartialEq)] #[allow(missing_doc)] pub enum Function { - GPIO = 0, + Gpio = 0, AltFunction1 = 1, AltFunction2 = 2, AltFunction3 = 3, @@ -56,7 +56,7 @@ pub struct Pin { impl Pin { /// Create and setup a Pin pub fn new(port: Port, pin_index: u8, function: Function, - gpiodir: Option<::hal::pin::GPIODirection>) -> Pin { + gpiodir: Option<::hal::pin::GpioDirection>) -> Pin { let pin = Pin { port: port, pin: pin_index, @@ -67,7 +67,7 @@ impl Pin { } fn setup_regs(&self, function: Function, - gpiodir: Option<::hal::pin::GPIODirection>) { + gpiodir: Option<::hal::pin::GpioDirection>) { let (offset, reg) = self.get_pinsel_reg_and_offset(); let fun_bits: u32 = function as u32 << (offset as uint * 2); @@ -77,18 +77,18 @@ impl Pin { let new_val = (val & mask_bits) | fun_bits; reg.set_value(new_val); - if function == GPIO { - (self as &::hal::pin::GPIO).set_direction(gpiodir.unwrap()); + if function == Gpio { + (self as &::hal::pin::Gpio).set_direction(gpiodir.unwrap()); } } - fn gpioreg(&self) -> ®::GPIO { + fn gpioreg(&self) -> ®::Gpio { match self.port { - Port0 => ®::GPIO0, - Port1 => ®::GPIO1, - Port2 => ®::GPIO2, - Port3 => ®::GPIO3, - Port4 => ®::GPIO4, + Port0 => ®::Gpio0, + Port1 => ®::Gpio1, + Port2 => ®::Gpio2, + Port3 => ®::Gpio3, + Port4 => ®::Gpio4, } } @@ -120,7 +120,7 @@ impl Pin { } } -impl ::hal::pin::GPIO for Pin { +impl ::hal::pin::Gpio for Pin { /// Sets output GPIO value to high. fn set_high(&self) { self.gpioreg().set_FIOSET(1 << (self.pin as uint)); @@ -132,7 +132,7 @@ impl ::hal::pin::GPIO for Pin { } /// Returns input GPIO level. - fn level(&self) -> ::hal::pin::GPIOLevel { + fn level(&self) -> ::hal::pin::GpioLevel { let bit: u32 = 1 << (self.pin as uint); let reg = self.gpioreg(); @@ -143,7 +143,7 @@ impl ::hal::pin::GPIO for Pin { } /// Sets output GPIO direction. - fn set_direction(&self, new_mode: ::hal::pin::GPIODirection) { + fn set_direction(&self, new_mode: ::hal::pin::GpioDirection) { let bit: u32 = 1 << (self.pin as uint); let mask: u32 = !bit; let reg = self.gpioreg(); @@ -180,18 +180,18 @@ mod reg { #[link_name="lpc17xx_iomem_PINSEL10"] pub static PINSEL10: PINSEL; } - ioreg_old!(GPIO: u32, FIODIR, _r0, _r1, _r2, FIOMASK, FIOPIN, FIOSET, FIOCLR) - reg_rw!(GPIO, u32, FIODIR, set_FIODIR, FIODIR) - reg_rw!(GPIO, u32, FIOMASK, set_FIOMASK, FIOMASK) - reg_rw!(GPIO, u32, FIOPIN, set_FIOPIN, FIOPIN) - reg_rw!(GPIO, u32, FIOSET, set_FIOSET, FIOSET) - reg_rw!(GPIO, u32, FIOCLR, set_FIOCLR, FIOCLR) + ioreg_old!(Gpio: u32, FIODIR, _r0, _r1, _r2, FIOMASK, FIOPIN, FIOSET, FIOCLR) + reg_rw!(Gpio, u32, FIODIR, set_FIODIR, FIODIR) + reg_rw!(Gpio, u32, FIOMASK, set_FIOMASK, FIOMASK) + reg_rw!(Gpio, u32, FIOPIN, set_FIOPIN, FIOPIN) + reg_rw!(Gpio, u32, FIOSET, set_FIOSET, FIOSET) + reg_rw!(Gpio, u32, FIOCLR, set_FIOCLR, FIOCLR) extern { - #[link_name="lpc17xx_iomem_GPIO0"] pub static GPIO0: GPIO; - #[link_name="lpc17xx_iomem_GPIO1"] pub static GPIO1: GPIO; - #[link_name="lpc17xx_iomem_GPIO2"] pub static GPIO2: GPIO; - #[link_name="lpc17xx_iomem_GPIO3"] pub static GPIO3: GPIO; - #[link_name="lpc17xx_iomem_GPIO4"] pub static GPIO4: GPIO; + #[link_name="lpc17xx_iomem_GPIO0"] pub static Gpio0: Gpio; + #[link_name="lpc17xx_iomem_GPIO1"] pub static Gpio1: Gpio; + #[link_name="lpc17xx_iomem_GPIO2"] pub static Gpio2: Gpio; + #[link_name="lpc17xx_iomem_GPIO3"] pub static Gpio3: Gpio; + #[link_name="lpc17xx_iomem_GPIO4"] pub static Gpio4: Gpio; } } diff --git a/src/zinc/hal/lpc17xx/pin_pt.rs b/src/zinc/hal/lpc17xx/pin_pt.rs index d495020c..94dd6090 100644 --- a/src/zinc/hal/lpc17xx/pin_pt.rs +++ b/src/zinc/hal/lpc17xx/pin_pt.rs @@ -156,7 +156,7 @@ mod test { "let p1 = zinc::hal::lpc17xx::pin::Pin::new( zinc::hal::lpc17xx::pin::Port0, 1u8, - zinc::hal::lpc17xx::pin::GPIO, + zinc::hal::lpc17xx::pin::Gpio, core::option::Some(zinc::hal::pin::In));"); }); } @@ -178,7 +178,7 @@ mod test { "let p2 = zinc::hal::lpc17xx::pin::Pin::new( zinc::hal::lpc17xx::pin::Port0, 2u8, - zinc::hal::lpc17xx::pin::GPIO, + zinc::hal::lpc17xx::pin::Gpio, core::option::Some(zinc::hal::pin::Out));"); }); } diff --git a/src/zinc/hal/lpc17xx/platformtree.rs b/src/zinc/hal/lpc17xx/platformtree.rs index e3d5b7dd..801ebac4 100644 --- a/src/zinc/hal/lpc17xx/platformtree.rs +++ b/src/zinc/hal/lpc17xx/platformtree.rs @@ -159,7 +159,7 @@ mod test { let led4 = zinc::hal::lpc17xx::pin::Pin::new( zinc::hal::lpc17xx::pin::Port1, 23u8, - zinc::hal::lpc17xx::pin::GPIO, + zinc::hal::lpc17xx::pin::Gpio, core::option::Some(zinc::hal::pin::Out)); loop { run(&pt::run_args{ diff --git a/src/zinc/hal/pin.rs b/src/zinc/hal/pin.rs index 333eedbf..0ac0b039 100644 --- a/src/zinc/hal/pin.rs +++ b/src/zinc/hal/pin.rs @@ -16,7 +16,7 @@ //! Common definitions for pin HAL. /// GPIO direction. -pub enum GPIODirection { +pub enum GpioDirection { /// Input mode. In, /// Output mode. @@ -25,7 +25,7 @@ pub enum GPIODirection { /// Logic levels. #[deriving(PartialEq)] -pub enum GPIOLevel { +pub enum GpioLevel { /// Logic low. Low, /// Logic high. @@ -33,7 +33,7 @@ pub enum GPIOLevel { } /// General Purpose I/O. -pub trait GPIO { +pub trait Gpio { /// Set to logic high. fn set_high(&self); @@ -41,9 +41,9 @@ pub trait GPIO { fn set_low(&self); /// Read current logic level. - fn level(&self) -> GPIOLevel; + fn level(&self) -> GpioLevel; /// Set direction mode to `In` or `Out`, /// for reading or writing respectively. - fn set_direction(&self, new_mode: GPIODirection); + fn set_direction(&self, new_mode: GpioDirection); } diff --git a/src/zinc/hal/stm32f4/gpio.rs b/src/zinc/hal/stm32f4/gpio.rs index aaa78f70..42ae45bf 100644 --- a/src/zinc/hal/stm32f4/gpio.rs +++ b/src/zinc/hal/stm32f4/gpio.rs @@ -16,7 +16,7 @@ //! HAL for STM32F4 GPIO peripheral. use hal::stm32f4::pin; -use hal::pin::{GPIODirection}; +use hal::pin::{GpioDirection}; #[path="../../util/ioreg.rs"] mod ioreg; @@ -27,7 +27,7 @@ pub struct GPIOConf { pub pin: pin::PinConf, /// Direction for GPIO, either `In` or `Out`. - pub direction: GPIODirection, + pub direction: GpioDirection, } impl GPIOConf { diff --git a/src/zinc/hal/stm32f4/pin.rs b/src/zinc/hal/stm32f4/pin.rs index ff478019..94926260 100644 --- a/src/zinc/hal/stm32f4/pin.rs +++ b/src/zinc/hal/stm32f4/pin.rs @@ -108,7 +108,7 @@ impl PinConf { } /// Returns input GPIO level. - pub fn level(&self) -> ::hal::pin::GPIOLevel { + pub fn level(&self) -> ::hal::pin::GpioLevel { let bit: u32 = 1 << (self.pin as uint); let reg = self.get_reg(); diff --git a/src/zinc/hal/stm32l1/pin.rs b/src/zinc/hal/stm32l1/pin.rs index 9be1181f..b8f8b412 100644 --- a/src/zinc/hal/stm32l1/pin.rs +++ b/src/zinc/hal/stm32l1/pin.rs @@ -144,7 +144,7 @@ impl Pin { } } -impl ::hal::pin::GPIO for Pin { +impl ::hal::pin::Gpio for Pin { fn set_high(&self) { let bit: u32 = 1 << self.index as uint; self.reg.bsrr.set_reset(bit); @@ -155,7 +155,7 @@ impl ::hal::pin::GPIO for Pin { self.reg.bsrr.set_reset(bit); } - fn level(&self) -> ::hal::pin::GPIOLevel { + fn level(&self) -> ::hal::pin::GpioLevel { let bit = 1u16 << (self.index as uint); match self.reg.idr.input() & bit { @@ -164,7 +164,7 @@ impl ::hal::pin::GPIO for Pin { } } - fn set_direction(&self, _new_mode: ::hal::pin::GPIODirection) { + fn set_direction(&self, _new_mode: ::hal::pin::GpioDirection) { //TODO(kvark) unsafe { abort() } } From d67d156c0354d0453e0923889611d19f39ec394d Mon Sep 17 00:00:00 2001 From: Ben Gamari Date: Thu, 28 Aug 2014 11:35:48 -0400 Subject: [PATCH 2/3] hal::k20: Add DSPI registers --- src/hal/k20/spi.rs | 171 ++++++++++++++++++++++++++++++++++++++++ src/zinc/hal/k20/mod.rs | 1 + 2 files changed, 172 insertions(+) create mode 100644 src/hal/k20/spi.rs diff --git a/src/hal/k20/spi.rs b/src/hal/k20/spi.rs new file mode 100644 index 00000000..345fc6b3 --- /dev/null +++ b/src/hal/k20/spi.rs @@ -0,0 +1,171 @@ +// Zinc, the bare metal stack for rust. +// Copyright 2014 Ben Gamari +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/*! +SPI peripheral +*/ + +/// Registers +pub mod reg { + use lib::volatile_cell::VolatileCell; + use core::ops::Drop; + + ioregs!(DSPI = { + 0x0 => reg32 mcr { //! Module configuration register + 0 => halt, //= Start/stop transfers + 8..9 => smpl_pt { //! How many clocks between SCK edge and SIN sample + 0x0 => SMPL_PT_0_CLKS, + 0x1 => SMPL_PT_1_CLKS, + 0x2 => SMPL_PT_2_CLKS, + } + 10 => clr_rxf, //= Flush RX FIFO + 11 => clr_txf, //= Flush TX FIFO + 12 => dis_rxf, //= Disable receive FIFO + 13 => dis_txf, //= Disable transmit FIFO + 14 => mdis, //= Disable module + 15 => doze, //= Doze enable + 16..20 => pcsis[5], //= Chip select inactive states + 24 => rooe, //= Receive FIFO overflow overwrite enable + 26 => mtfe, //= Modified timing format enable + 27 => frz, //= Freeze + 28..29 => dconf { //! Peripheral configuration + 0x0 => SPI, + } + 30 => cont_scke, //= Continuous SCK enable + 31 => mstr { //! Master/slave mode select + 0x0 => SLAVE, + 0x1 => MASTER, + } + } + + 0x8 => reg32 tcr { //! Transfer count register + 16..31 => tcnt, //= Number of frames transmitted + } + + 0xc => reg32 ctar[2] { //! Clock and transfer attributes + /// Baud rate scaler (master only) + /// + /// SCK baud rate = (f_sys / PBR) * (1 + DBR) / BR + 0..3 => br, + /// Delay after transfer scaler (master only) + /// + /// t_delay = (1/f_sys) * PDT * DT + 4..7 => dt, + /// After SCK delay scaler (master only) + /// + /// t_ASC = (1/f_sys) * PASC * ASC + 8..11 => asc, + /// CS to SCK delay scaler (master only) + 12..15 => cssck, + /// Baud rate prescaler (master only) + 17..16 => pbr { + 0x0 => PBR_2, + 0x1 => PBR_3, + 0x2 => PBR_5, + 0x3 => PBR_7, + } + /// Delay after transfer prescaler (master only) + 18..19 => pdt { + 0x0 => PDT_2, + 0x1 => PDT_3, + 0x2 => PDT_5, + 0x3 => PDT_7, + }, + /// After SCK delay prescaler (master only) + 20..21 => pasc { + 0x0 => PASC_2, + 0x1 => PASC_3, + 0x2 => PASC_5, + 0x3 => PASC_7, + }, + /// CS to SCK delay prescaler (master only) + 22..23 => pcssck { + 0x0 => PCSSCK_2, + 0x1 => PCSSCK_3, + 0x2 => PCSSCK_5, + 0x3 => PCSSCK_7, + }, + /// Transfer LSB first (master only) + 24 => lsbfe, + /// Clock phase + 25 => cpha, + /// Clock polarity + 26 => cpol, + /// Frame size + /// + /// Number of bits transferred per frame minus one. + /// In master mode the top bit of this field is the DBR, double + /// baud rate, flag + 27..31 => fmsz, + } + + 0x2c => reg32 sr { //! Status register + 0..3 => popnxtptr, //= Pop next pointer + 4..7 => rxctr, //= RX FIFO counter + 8..11 => txnxtptr, //= Transmit next pointer + 12..15 => txctr, //= TX FIFO counter + 17 => rfdf: set_to_clear, //= Receive FIFO drain flag + 19 => rfof: set_to_clear, //= Receive FIFO overflow flag + 25 => tfff: set_to_clear, //= Transmit FIFO fill flag + 27 => tfuf: set_to_clear, //= Transmit FIFO underflow flag + 28 => eoqf: set_to_clear, //= End of queue flag + 30 => rxrxs: set_to_clear, //= TX/RX running + 31 => tcf: set_to_clear, //= Transfer complete flag + } + + 0x30 => reg32 rser { //! DMA/interrupt request select and enable + /// Receive FIFO drain DMA/interrupt request select + 16 => rfdf_dirs { + 0x0 => RFDF_IRQ, + 0x1 => RFDF_DMA, + } + 17 => rfdf_re, //= Recieve FIFO drain request enable + 19 => rfof_re, //= Receive FIFO overflow request enable + /// Transmit FIFO fill DMA/interrupt request select + 24 => tfff_dirs { + 0x0 => TFFF_IRQ, + 0x1 => TFFF_DMA, + } + 25 => tfff_re, //= Transmit FIFO fill request enable + 27 => tfuf_re, //= Transmit FIFO underflow request enable + 28 => eoqf_re, //= End of Queue request enable + 31 => tcf_re, //= Transmission complete request enable + } + + 0x34 => reg32 pushr { //! TX FIFO register + 0..15 => txdata, //= Transmitted data + 16..21 => pcs[6], //= Chip select state (master only) + /// Clear transfer counter (`TCR.TCNT`) (master only) + 26 => ctcnt, + /// Set End of Queue flag (`SR.EOQF`) at end of transfer (master only) + 27 => eoq, + 28..30 => ctas, //= CTAR select (master only) + 31 => cont, //= Continuous CS enable (master only) + } + + 0x38 => reg32 popr { //! RX FIFO register + 0..31 => rxdata: ro, //= Received data + } + + 0x3c => reg32 txfr[4] { //! TX FIFO debug registers + 0..15 => txdata: ro, + 16..31 => txcmd_txdata: ro, + } + + 0x7c => reg32 rxfr[4] { //! RX FIFO debug registers + 0..31 => rxdata: ro, + } + }) +} diff --git a/src/zinc/hal/k20/mod.rs b/src/zinc/hal/k20/mod.rs index c861f3d7..db3d3b68 100644 --- a/src/zinc/hal/k20/mod.rs +++ b/src/zinc/hal/k20/mod.rs @@ -19,3 +19,4 @@ pub mod sim; pub mod pin; pub mod uart; pub mod watchdog; +pub mod spi; From ea47c0efde8273947eaa65913ae1b8e9994d8efc Mon Sep 17 00:00:00 2001 From: Ben Gamari Date: Thu, 28 Aug 2014 13:07:21 -0400 Subject: [PATCH 3/3] k20::spi: Add hal::SPI impl --- src/hal/k20/spi.rs | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/src/hal/k20/spi.rs b/src/hal/k20/spi.rs index 345fc6b3..79c938d5 100644 --- a/src/hal/k20/spi.rs +++ b/src/hal/k20/spi.rs @@ -17,6 +17,48 @@ SPI peripheral */ +use hal::spi; + +#[path="../../lib/wait_for.rs"] mod wait_for; + +pub enum ChipSelect { + CS0 = 0, + CS1 = 1, + CS2 = 2, + CS3 = 3, + CS4 = 4, + CS5 = 5, +} + +/// An SPI peripheral instance +pub struct DSPI { + reg: &'static reg::DSPI, + cs: ChipSelect, +} + +impl DSPI { + fn new(reg: &'static reg::DSPI, cs: ChipSelect) -> DSPI { + reg.mcr.set_halt(false); + DSPI {reg: reg, cs: cs} + } +} + +impl spi::SPI for DSPI { + fn write(&self, value: u8) { + wait_for!(self.reg.sr.tfff()); + self.reg.sr.clear_tfff(); + // TODO(bgamari): Need to ensure this doesn't read + self.reg.pushr + .set_txdata(value as u32) + .set_pcs(self.cs as u32); + } + + fn read(&self) -> u8 { + wait_for!(self.reg.sr.rfdf()); + self.reg.popr.rxdata() as u8 + } +} + /// Registers pub mod reg { use lib::volatile_cell::VolatileCell;