From 83b31154112d942cd796f85e4fdd2eb0d4dfabc8 Mon Sep 17 00:00:00 2001 From: heiso Date: Thu, 12 Dec 2024 00:22:12 +0100 Subject: [PATCH] wip: esp32 firmware --- .gitmodules | 10 +- .vscode/c_cpp_properties.json | 18 - .vscode/extensions.json | 4 +- .vscode/launch.json | 14 - .vscode/macrolev.code-workspace | 39 + .vscode/tasks.json | 29 - firmware/{Core/Inc => common/src}/DRV2605L.h | 0 firmware/{Core/Src => common/src}/config.c | 0 firmware/{Core/Inc => common/src}/config.h | 0 firmware/{Core/Src => common/src}/hid.c | 0 firmware/{Core/Inc => common/src}/hid.h | 0 firmware/{Core/Src => common/src}/keyboard.c | 0 firmware/{Core/Inc => common/src}/keyboard.h | 0 .../{Core/Inc => common/src}/tusb_config.h | 0 .../Src => common/src}/usb_descriptors.c | 0 .../Inc => common/src}/usb_descriptors.h | 0 firmware/common/tinyusb | 1 + .../esp32-s3/.clang-format | 0 .../esp32-s3/.vscode/c_cpp_properties.json | 17 + firmware/esp32-s3/.vscode/extensions.json | 3 + firmware/esp32-s3/.vscode/settings.json | 3 + firmware/esp32-s3/CMakeLists.txt | 6 + firmware/esp32-s3/README.md | 27 + firmware/esp32-s3/main/CMakeLists.txt | 4 + firmware/esp32-s3/main/DRV2605L.h | 196 ++ firmware/esp32-s3/main/config.c | 39 + firmware/esp32-s3/main/config.h | 22 + firmware/esp32-s3/main/hid.c | 341 +++ firmware/esp32-s3/main/hid.h | 22 + firmware/esp32-s3/main/keyboard.c | 320 +++ firmware/esp32-s3/main/keyboard.h | 109 + firmware/esp32-s3/main/main.c | 173 ++ firmware/esp32-s3/main/tusb_config.h | 109 + firmware/esp32-s3/main/usb_descriptors.c | 280 +++ firmware/esp32-s3/main/usb_descriptors.h | 44 + firmware/esp32-s3/sdkconfig | 2214 +++++++++++++++++ firmware/esp32-s3/sdkconfig.old | 2214 +++++++++++++++++ firmware/stm32f4xx/.clang-format | 1 + firmware/{ => stm32f4xx}/.cproject | 0 firmware/{ => stm32f4xx}/.mxproject | 0 firmware/{ => stm32f4xx}/.project | 0 .../com.st.stm32cube.ide.mcu.sfrview.prefs | 0 .../.settings/language.settings.xml | 0 .../.settings/stm32cubeide.project.prefs | 0 .../stm32f4xx/.vscode/c_cpp_properties.json | 18 + firmware/stm32f4xx/.vscode/extensions.json | 3 + firmware/stm32f4xx/.vscode/settings.json | 3 + firmware/stm32f4xx/Core/Inc/DRV2605L.h | 196 ++ firmware/stm32f4xx/Core/Inc/config.h | 22 + firmware/stm32f4xx/Core/Inc/hid.h | 22 + firmware/stm32f4xx/Core/Inc/keyboard.h | 109 + firmware/{ => stm32f4xx}/Core/Inc/main.h | 0 .../Core/Inc/stm32f4xx_hal_conf.h | 0 .../{ => stm32f4xx}/Core/Inc/stm32f4xx_it.h | 0 firmware/stm32f4xx/Core/Inc/tusb_config.h | 109 + firmware/stm32f4xx/Core/Inc/usb_descriptors.h | 44 + firmware/stm32f4xx/Core/Src/config.c | 39 + firmware/stm32f4xx/Core/Src/hid.c | 341 +++ firmware/stm32f4xx/Core/Src/keyboard.c | 313 +++ firmware/{ => stm32f4xx}/Core/Src/main.c | 0 .../Core/Src/stm32f4xx_hal_msp.c | 0 .../{ => stm32f4xx}/Core/Src/stm32f4xx_it.c | 0 firmware/{ => stm32f4xx}/Core/Src/syscalls.c | 0 firmware/{ => stm32f4xx}/Core/Src/sysmem.c | 0 .../Core/Src/system_stm32f4xx.c | 0 firmware/stm32f4xx/Core/Src/usb_descriptors.c | 280 +++ .../Core/Startup/startup_stm32f411ceux.s | 0 .../Device/ST/STM32F4xx/Include/stm32f411xe.h | 0 .../Device/ST/STM32F4xx/Include/stm32f4xx.h | 0 .../ST/STM32F4xx/Include/system_stm32f4xx.h | 0 .../CMSIS/Device/ST/STM32F4xx/LICENSE.txt | 0 .../Drivers/CMSIS/Include/cachel1_armv7.h | 0 .../Drivers/CMSIS/Include/cmsis_armcc.h | 0 .../Drivers/CMSIS/Include/cmsis_armclang.h | 0 .../CMSIS/Include/cmsis_armclang_ltm.h | 0 .../Drivers/CMSIS/Include/cmsis_compiler.h | 0 .../Drivers/CMSIS/Include/cmsis_gcc.h | 0 .../Drivers/CMSIS/Include/cmsis_iccarm.h | 0 .../Drivers/CMSIS/Include/cmsis_version.h | 0 .../Drivers/CMSIS/Include/core_armv81mml.h | 0 .../Drivers/CMSIS/Include/core_armv8mbl.h | 0 .../Drivers/CMSIS/Include/core_armv8mml.h | 0 .../Drivers/CMSIS/Include/core_cm0.h | 0 .../Drivers/CMSIS/Include/core_cm0plus.h | 0 .../Drivers/CMSIS/Include/core_cm1.h | 0 .../Drivers/CMSIS/Include/core_cm23.h | 0 .../Drivers/CMSIS/Include/core_cm3.h | 0 .../Drivers/CMSIS/Include/core_cm33.h | 0 .../Drivers/CMSIS/Include/core_cm35p.h | 0 .../Drivers/CMSIS/Include/core_cm4.h | 0 .../Drivers/CMSIS/Include/core_cm55.h | 0 .../Drivers/CMSIS/Include/core_cm7.h | 0 .../Drivers/CMSIS/Include/core_cm85.h | 0 .../Drivers/CMSIS/Include/core_sc000.h | 0 .../Drivers/CMSIS/Include/core_sc300.h | 0 .../Drivers/CMSIS/Include/core_starmc1.h | 0 .../Drivers/CMSIS/Include/mpu_armv7.h | 0 .../Drivers/CMSIS/Include/mpu_armv8.h | 0 .../Drivers/CMSIS/Include/pac_armv81.h | 0 .../Drivers/CMSIS/Include/pmu_armv8.h | 0 .../Drivers/CMSIS/Include/tz_context.h | 0 .../{ => stm32f4xx}/Drivers/CMSIS/LICENSE.txt | 0 .../Inc/Legacy/stm32_hal_legacy.h | 0 .../STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h | 0 .../Inc/stm32f4xx_hal_adc.h | 0 .../Inc/stm32f4xx_hal_adc_ex.h | 0 .../Inc/stm32f4xx_hal_cortex.h | 0 .../Inc/stm32f4xx_hal_def.h | 0 .../Inc/stm32f4xx_hal_dma.h | 0 .../Inc/stm32f4xx_hal_dma_ex.h | 0 .../Inc/stm32f4xx_hal_exti.h | 0 .../Inc/stm32f4xx_hal_flash.h | 0 .../Inc/stm32f4xx_hal_flash_ex.h | 0 .../Inc/stm32f4xx_hal_flash_ramfunc.h | 0 .../Inc/stm32f4xx_hal_gpio.h | 0 .../Inc/stm32f4xx_hal_gpio_ex.h | 0 .../Inc/stm32f4xx_hal_i2c.h | 0 .../Inc/stm32f4xx_hal_i2c_ex.h | 0 .../Inc/stm32f4xx_hal_pcd.h | 0 .../Inc/stm32f4xx_hal_pcd_ex.h | 0 .../Inc/stm32f4xx_hal_pwr.h | 0 .../Inc/stm32f4xx_hal_pwr_ex.h | 0 .../Inc/stm32f4xx_hal_rcc.h | 0 .../Inc/stm32f4xx_hal_rcc_ex.h | 0 .../Inc/stm32f4xx_hal_tim.h | 0 .../Inc/stm32f4xx_hal_tim_ex.h | 0 .../Inc/stm32f4xx_ll_adc.h | 0 .../Inc/stm32f4xx_ll_bus.h | 0 .../Inc/stm32f4xx_ll_cortex.h | 0 .../Inc/stm32f4xx_ll_dma.h | 0 .../Inc/stm32f4xx_ll_exti.h | 0 .../Inc/stm32f4xx_ll_gpio.h | 0 .../Inc/stm32f4xx_ll_i2c.h | 0 .../Inc/stm32f4xx_ll_pwr.h | 0 .../Inc/stm32f4xx_ll_rcc.h | 0 .../Inc/stm32f4xx_ll_system.h | 0 .../Inc/stm32f4xx_ll_usb.h | 0 .../Inc/stm32f4xx_ll_utils.h | 0 .../Drivers/STM32F4xx_HAL_Driver/LICENSE.txt | 0 .../STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c | 0 .../Src/stm32f4xx_hal_adc.c | 0 .../Src/stm32f4xx_hal_adc_ex.c | 0 .../Src/stm32f4xx_hal_cortex.c | 0 .../Src/stm32f4xx_hal_dma.c | 0 .../Src/stm32f4xx_hal_dma_ex.c | 0 .../Src/stm32f4xx_hal_exti.c | 0 .../Src/stm32f4xx_hal_flash.c | 0 .../Src/stm32f4xx_hal_flash_ex.c | 0 .../Src/stm32f4xx_hal_flash_ramfunc.c | 0 .../Src/stm32f4xx_hal_gpio.c | 0 .../Src/stm32f4xx_hal_i2c.c | 0 .../Src/stm32f4xx_hal_i2c_ex.c | 0 .../Src/stm32f4xx_hal_pcd.c | 0 .../Src/stm32f4xx_hal_pcd_ex.c | 0 .../Src/stm32f4xx_hal_pwr.c | 0 .../Src/stm32f4xx_hal_pwr_ex.c | 0 .../Src/stm32f4xx_hal_rcc.c | 0 .../Src/stm32f4xx_hal_rcc_ex.c | 0 .../Src/stm32f4xx_hal_tim.c | 0 .../Src/stm32f4xx_hal_tim_ex.c | 0 .../Src/stm32f4xx_ll_adc.c | 0 .../Src/stm32f4xx_ll_usb.c | 0 .../{ => stm32f4xx}/STM32F411CEUX_FLASH.ld | 0 firmware/{ => stm32f4xx}/STM32F411CEUX_RAM.ld | 0 .../{ => stm32f4xx}/macrolev Debug.launch | 0 .../{ => stm32f4xx}/macrolev Release.launch | 0 firmware/{ => stm32f4xx}/macrolev.ioc | 0 firmware/stm32f4xx/tinyusb | 1 + firmware/tinyusb | 1 - 169 files changed, 7693 insertions(+), 67 deletions(-) delete mode 100644 .vscode/c_cpp_properties.json create mode 100644 .vscode/macrolev.code-workspace delete mode 100644 .vscode/tasks.json rename firmware/{Core/Inc => common/src}/DRV2605L.h (100%) rename firmware/{Core/Src => common/src}/config.c (100%) rename firmware/{Core/Inc => common/src}/config.h (100%) rename firmware/{Core/Src => common/src}/hid.c (100%) rename firmware/{Core/Inc => common/src}/hid.h (100%) rename firmware/{Core/Src => common/src}/keyboard.c (100%) rename firmware/{Core/Inc => common/src}/keyboard.h (100%) rename firmware/{Core/Inc => common/src}/tusb_config.h (100%) rename firmware/{Core/Src => common/src}/usb_descriptors.c (100%) rename firmware/{Core/Inc => common/src}/usb_descriptors.h (100%) create mode 160000 firmware/common/tinyusb rename .clang-format => firmware/esp32-s3/.clang-format (100%) create mode 100644 firmware/esp32-s3/.vscode/c_cpp_properties.json create mode 100644 firmware/esp32-s3/.vscode/extensions.json create mode 100644 firmware/esp32-s3/.vscode/settings.json create mode 100644 firmware/esp32-s3/CMakeLists.txt create mode 100644 firmware/esp32-s3/README.md create mode 100644 firmware/esp32-s3/main/CMakeLists.txt create mode 100644 firmware/esp32-s3/main/DRV2605L.h create mode 100644 firmware/esp32-s3/main/config.c create mode 100644 firmware/esp32-s3/main/config.h create mode 100644 firmware/esp32-s3/main/hid.c create mode 100644 firmware/esp32-s3/main/hid.h create mode 100644 firmware/esp32-s3/main/keyboard.c create mode 100644 firmware/esp32-s3/main/keyboard.h create mode 100644 firmware/esp32-s3/main/main.c create mode 100644 firmware/esp32-s3/main/tusb_config.h create mode 100644 firmware/esp32-s3/main/usb_descriptors.c create mode 100644 firmware/esp32-s3/main/usb_descriptors.h create mode 100644 firmware/esp32-s3/sdkconfig create mode 100644 firmware/esp32-s3/sdkconfig.old create mode 100644 firmware/stm32f4xx/.clang-format rename firmware/{ => stm32f4xx}/.cproject (100%) rename firmware/{ => stm32f4xx}/.mxproject (100%) rename firmware/{ => stm32f4xx}/.project (100%) rename firmware/{ => stm32f4xx}/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs (100%) rename firmware/{ => stm32f4xx}/.settings/language.settings.xml (100%) rename firmware/{ => stm32f4xx}/.settings/stm32cubeide.project.prefs (100%) create mode 100644 firmware/stm32f4xx/.vscode/c_cpp_properties.json create mode 100644 firmware/stm32f4xx/.vscode/extensions.json create mode 100644 firmware/stm32f4xx/.vscode/settings.json create mode 100644 firmware/stm32f4xx/Core/Inc/DRV2605L.h create mode 100644 firmware/stm32f4xx/Core/Inc/config.h create mode 100644 firmware/stm32f4xx/Core/Inc/hid.h create mode 100644 firmware/stm32f4xx/Core/Inc/keyboard.h rename firmware/{ => stm32f4xx}/Core/Inc/main.h (100%) rename firmware/{ => stm32f4xx}/Core/Inc/stm32f4xx_hal_conf.h (100%) rename firmware/{ => stm32f4xx}/Core/Inc/stm32f4xx_it.h (100%) create mode 100644 firmware/stm32f4xx/Core/Inc/tusb_config.h create mode 100644 firmware/stm32f4xx/Core/Inc/usb_descriptors.h create mode 100644 firmware/stm32f4xx/Core/Src/config.c create mode 100644 firmware/stm32f4xx/Core/Src/hid.c create mode 100644 firmware/stm32f4xx/Core/Src/keyboard.c rename firmware/{ => stm32f4xx}/Core/Src/main.c (100%) rename firmware/{ => stm32f4xx}/Core/Src/stm32f4xx_hal_msp.c (100%) rename firmware/{ => stm32f4xx}/Core/Src/stm32f4xx_it.c (100%) rename firmware/{ => stm32f4xx}/Core/Src/syscalls.c (100%) rename firmware/{ => stm32f4xx}/Core/Src/sysmem.c (100%) rename firmware/{ => stm32f4xx}/Core/Src/system_stm32f4xx.c (100%) create mode 100644 firmware/stm32f4xx/Core/Src/usb_descriptors.c rename firmware/{ => stm32f4xx}/Core/Startup/startup_stm32f411ceux.s (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/cachel1_armv7.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/cmsis_armcc.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/cmsis_armclang.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/cmsis_armclang_ltm.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/cmsis_compiler.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/cmsis_gcc.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/cmsis_iccarm.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/cmsis_version.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_armv81mml.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_armv8mbl.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_armv8mml.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_cm0.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_cm0plus.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_cm1.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_cm23.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_cm3.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_cm33.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_cm35p.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_cm4.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_cm55.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_cm7.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_cm85.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_sc000.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_sc300.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/core_starmc1.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/mpu_armv7.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/mpu_armv8.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/pac_armv81.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/pmu_armv8.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/Include/tz_context.h (100%) rename firmware/{ => stm32f4xx}/Drivers/CMSIS/LICENSE.txt (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c (100%) rename firmware/{ => stm32f4xx}/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c (100%) rename firmware/{ => stm32f4xx}/STM32F411CEUX_FLASH.ld (100%) rename firmware/{ => stm32f4xx}/STM32F411CEUX_RAM.ld (100%) rename firmware/{ => stm32f4xx}/macrolev Debug.launch (100%) rename firmware/{ => stm32f4xx}/macrolev Release.launch (100%) rename firmware/{ => stm32f4xx}/macrolev.ioc (100%) create mode 160000 firmware/stm32f4xx/tinyusb delete mode 160000 firmware/tinyusb diff --git a/.gitmodules b/.gitmodules index f7640fb..e548b0c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,9 @@ -[submodule "firmware/tinyusb"] - path = firmware/tinyusb +[submodule "firmware/stm32f4xx/tinyusb"] + path = firmware/stm32f4xx/tinyusb + url = git@github.com:hathach/tinyusb.git +[submodule "firmware/esp32s3/esp-idf"] + path = firmware/esp32s3/esp-idf + url = git@github.com:espressif/esp-idf.git +[submodule "firmware/common/tinyusb"] + path = firmware/common/tinyusb url = git@github.com:hathach/tinyusb.git diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json deleted file mode 100644 index 505f36b..0000000 --- a/.vscode/c_cpp_properties.json +++ /dev/null @@ -1,18 +0,0 @@ -{ - "configurations": [ - { - "name": "Firmware", - "includePath": [ - "${workspaceFolder}/firmware/Core/Inc", - - "${workspaceFolder}/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/**", - "${workspaceFolder}/firmware/Drivers/CMSIS/Device/ST/STM32F4xx/Include", - "${workspaceFolder}/firmware/Drivers/CMSIS/Include", - - "${workspaceFolder}/firmware/tinyusb/src/**" - ], - "defines": ["USE_HAL_DRIVER", "STM32F411xE"] - } - ], - "version": 4 -} diff --git a/.vscode/extensions.json b/.vscode/extensions.json index e3c1da2..7e77aff 100644 --- a/.vscode/extensions.json +++ b/.vscode/extensions.json @@ -2,8 +2,6 @@ "recommendations": [ "bradlc.vscode-tailwindcss", "leathong.openscad-language-support", - "esbenp.prettier-vscode", - "ms-vscode.cpptools", - "xaver.clang-format" + "esbenp.prettier-vscode" ] } diff --git a/.vscode/launch.json b/.vscode/launch.json index e7d56e9..295193b 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -26,20 +26,6 @@ "enabled": true, "samplesPerSecond": 4 } - }, - { - "name": "Cortex Debug (no livewatch)", - "cwd": "${workspaceRoot}/firmware", - "executable": "${workspaceRoot}/firmware/build/${workspaceFolderBasename}.elf", - "request": "launch", - "type": "cortex-debug", - "servertype": "stlink", - "preLaunchTask": "flash", - "showDevDebugOutput": "raw", - "svdFile": "${workspaceRoot}/firmware/debug-files/STM32F411.svd", - "liveWatch": { - "enabled": false - } } ] } diff --git a/.vscode/macrolev.code-workspace b/.vscode/macrolev.code-workspace new file mode 100644 index 0000000..9455d87 --- /dev/null +++ b/.vscode/macrolev.code-workspace @@ -0,0 +1,39 @@ +{ + "folders": [ + { + "path": ".." + }, + { + "path": "../firmware/esp32-s3" + }, + { + "path": "../firmware/stm32f4xx" + }, + { + "path": "../firmware/common" + } + ], + "settings": { + "files.associations": { + "hid.h": "c", + "keyboard.h": "c", + "freertos.h": "c", + "task.h": "c", + "string.h": "c", + "stdio.h": "c", + "sdkconfig.h": "c", + "semphr.h": "c", + "freertosconfig.h": "c", + "portable.h": "c", + "adc_continuous.h": "c", + "stdlib.h": "c", + "soc_caps.h": "c", + "adc_cali_scheme.h": "c", + "adc_cali.h": "c", + "gpio.h": "c", + "drv2605l.h": "c", + "main.h": "c", + "adc_oneshot.h": "c" + } + } +} diff --git a/.vscode/tasks.json b/.vscode/tasks.json deleted file mode 100644 index 5d70b78..0000000 --- a/.vscode/tasks.json +++ /dev/null @@ -1,29 +0,0 @@ -{ - "version": "2.0.0", - "tasks": [ - { - "type": "shell", - "label": "build-debug", - "command": "make -C ${workspaceFolder}/firmware", - "group": { - "kind": "build", - "isDefault": true - } - }, - { - "type": "shell", - "label": "flash", - "command": "st-flash", - "args": ["write", "${workspaceFolderBasename}.bin", "0x8000000"], - "options": { - "cwd": "${workspaceFolder}/firmware/build" - }, - "dependsOn": "build-debug", - "problemMatcher": [], - "group": { - "kind": "build", - "isDefault": true - } - } - ] -} diff --git a/firmware/Core/Inc/DRV2605L.h b/firmware/common/src/DRV2605L.h similarity index 100% rename from firmware/Core/Inc/DRV2605L.h rename to firmware/common/src/DRV2605L.h diff --git a/firmware/Core/Src/config.c b/firmware/common/src/config.c similarity index 100% rename from firmware/Core/Src/config.c rename to firmware/common/src/config.c diff --git a/firmware/Core/Inc/config.h b/firmware/common/src/config.h similarity index 100% rename from firmware/Core/Inc/config.h rename to firmware/common/src/config.h diff --git a/firmware/Core/Src/hid.c b/firmware/common/src/hid.c similarity index 100% rename from firmware/Core/Src/hid.c rename to firmware/common/src/hid.c diff --git a/firmware/Core/Inc/hid.h b/firmware/common/src/hid.h similarity index 100% rename from firmware/Core/Inc/hid.h rename to firmware/common/src/hid.h diff --git a/firmware/Core/Src/keyboard.c b/firmware/common/src/keyboard.c similarity index 100% rename from firmware/Core/Src/keyboard.c rename to firmware/common/src/keyboard.c diff --git a/firmware/Core/Inc/keyboard.h b/firmware/common/src/keyboard.h similarity index 100% rename from firmware/Core/Inc/keyboard.h rename to firmware/common/src/keyboard.h diff --git a/firmware/Core/Inc/tusb_config.h b/firmware/common/src/tusb_config.h similarity index 100% rename from firmware/Core/Inc/tusb_config.h rename to firmware/common/src/tusb_config.h diff --git a/firmware/Core/Src/usb_descriptors.c b/firmware/common/src/usb_descriptors.c similarity index 100% rename from firmware/Core/Src/usb_descriptors.c rename to firmware/common/src/usb_descriptors.c diff --git a/firmware/Core/Inc/usb_descriptors.h b/firmware/common/src/usb_descriptors.h similarity index 100% rename from firmware/Core/Inc/usb_descriptors.h rename to firmware/common/src/usb_descriptors.h diff --git a/firmware/common/tinyusb b/firmware/common/tinyusb new file mode 160000 index 0000000..7c7b30f --- /dev/null +++ b/firmware/common/tinyusb @@ -0,0 +1 @@ +Subproject commit 7c7b30f0ae66a856ada3526cb947bd3a255567f8 diff --git a/.clang-format b/firmware/esp32-s3/.clang-format similarity index 100% rename from .clang-format rename to firmware/esp32-s3/.clang-format diff --git a/firmware/esp32-s3/.vscode/c_cpp_properties.json b/firmware/esp32-s3/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..18365b9 --- /dev/null +++ b/firmware/esp32-s3/.vscode/c_cpp_properties.json @@ -0,0 +1,17 @@ +{ + "configurations": [ + { + "name": "Firmware", + "includePath": [ + "${workspaceFolder}/main/**", + + "~/esp/esp-idf/components/**", + + // "${workspaceFolder}/../common/src/**", + + "${workspaceFolder}/../common/tinyusb/src/**" + ], + } + ], + "version": 4 +} diff --git a/firmware/esp32-s3/.vscode/extensions.json b/firmware/esp32-s3/.vscode/extensions.json new file mode 100644 index 0000000..48a680b --- /dev/null +++ b/firmware/esp32-s3/.vscode/extensions.json @@ -0,0 +1,3 @@ +{ + "recommendations": ["ms-vscode.cpptools", "xaver.clang-format"] +} diff --git a/firmware/esp32-s3/.vscode/settings.json b/firmware/esp32-s3/.vscode/settings.json new file mode 100644 index 0000000..ad92582 --- /dev/null +++ b/firmware/esp32-s3/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "editor.formatOnSave": true +} diff --git a/firmware/esp32-s3/CMakeLists.txt b/firmware/esp32-s3/CMakeLists.txt new file mode 100644 index 0000000..2fb3b96 --- /dev/null +++ b/firmware/esp32-s3/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following five lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(macrolev) diff --git a/firmware/esp32-s3/README.md b/firmware/esp32-s3/README.md new file mode 100644 index 0000000..d07e13f --- /dev/null +++ b/firmware/esp32-s3/README.md @@ -0,0 +1,27 @@ +## Configure the project + +Install idf.py cmd [https://docs.espressif.com/projects/esp-idf/en/latest/esp32/get-started/index.html] + +```bash +mkdir ~/esp +cd ~/esp +git clone git@github.com:espressif/esp-idf.git +cd esp-idf +git submodule update --init --recursive +./esp-idf/install.sh +``` + +Then in your project `. ~/esp/esp-idf/export.sh` + +Before project configuration and build, make sure to set the correct chip target using `idf.py set-target TARGET` command. + +## Erase the NVRAM + +Before flash it to the board, it is recommended to erase NVRAM if user doesn't want to keep the previous examples or other projects stored info +using `idf.py -p PORT erase-flash` + +## Build and Flash + +Build the project, flash it to the board, and start the monitor tool to view the serial output by running `idf.py -p PORT flash monitor`. + +(To exit the serial monitor, type `Ctrl-T + Ctrl-X`) diff --git a/firmware/esp32-s3/main/CMakeLists.txt b/firmware/esp32-s3/main/CMakeLists.txt new file mode 100644 index 0000000..36b72dd --- /dev/null +++ b/firmware/esp32-s3/main/CMakeLists.txt @@ -0,0 +1,4 @@ +idf_component_register( + SRCS "main.c" "keyboard.c" "config.c" "hid.c" + INCLUDE_DIRS "." "../../common/tinyusb/src" +) diff --git a/firmware/esp32-s3/main/DRV2605L.h b/firmware/esp32-s3/main/DRV2605L.h new file mode 100644 index 0000000..1116e28 --- /dev/null +++ b/firmware/esp32-s3/main/DRV2605L.h @@ -0,0 +1,196 @@ +#ifndef _DRV2605_H +#define _DRV2605_H + +#include + +#define DRV2605_ADDR 0x5A ///< Device I2C address + +#define DRV2605_REG_STATUS 0x00 ///< Status register +#define DRV2605_REG_MODE 0x01 ///< Mode register +#define DRV2605_MODE_INTTRIG 0x00 ///< Internal trigger mode +#define DRV2605_MODE_EXTTRIGEDGE 0x01 ///< External edge trigger mode +#define DRV2605_MODE_EXTTRIGLVL 0x02 ///< External level trigger mode +#define DRV2605_MODE_PWMANALOG 0x03 ///< PWM/Analog input mode +#define DRV2605_MODE_AUDIOVIBE 0x04 ///< Audio-to-vibe mode +#define DRV2605_MODE_REALTIME 0x05 ///< Real-time playback (RTP) mode +#define DRV2605_MODE_DIAGNOS 0x06 ///< Diagnostics mode +#define DRV2605_MODE_AUTOCAL 0x07 ///< Auto calibration mode + +#define DRV2605_REG_RTPIN 0x02 ///< Real-time playback input register +#define DRV2605_REG_LIBRARY 0x03 ///< Waveform library selection register +#define DRV2605_REG_WAVESEQ1 0x04 ///< Waveform sequence register 1 +#define DRV2605_REG_WAVESEQ2 0x05 ///< Waveform sequence register 2 +#define DRV2605_REG_WAVESEQ3 0x06 ///< Waveform sequence register 3 +#define DRV2605_REG_WAVESEQ4 0x07 ///< Waveform sequence register 4 +#define DRV2605_REG_WAVESEQ5 0x08 ///< Waveform sequence register 5 +#define DRV2605_REG_WAVESEQ6 0x09 ///< Waveform sequence register 6 +#define DRV2605_REG_WAVESEQ7 0x0A ///< Waveform sequence register 7 +#define DRV2605_REG_WAVESEQ8 0x0B ///< Waveform sequence register 8 + +#define DRV2605_REG_GO 0x0C ///< Go register +#define DRV2605_REG_OVERDRIVE 0x0D ///< Overdrive time offset register +#define DRV2605_REG_SUSTAINPOS 0x0E ///< Sustain time offset, positive register +#define DRV2605_REG_SUSTAINNEG 0x0F ///< Sustain time offset, negative register +#define DRV2605_REG_BREAK 0x10 ///< Brake time offset register +#define DRV2605_REG_AUDIOCTRL 0x11 ///< Audio-to-vibe control register +#define DRV2605_REG_AUDIOLVL 0x12 ///< Audio-to-vibe minimum input level register +#define DRV2605_REG_AUDIOMAX 0x13 ///< Audio-to-vibe maximum input level register +#define DRV2605_REG_AUDIOOUTMIN 0x14 ///< Audio-to-vibe minimum output drive register +#define DRV2605_REG_AUDIOOUTMAX 0x15 ///< Audio-to-vibe maximum output drive register +#define DRV2605_REG_RATEDV 0x16 ///< Rated voltage register +#define DRV2605_REG_CLAMPV 0x17 ///< Overdrive clamp voltage register +#define DRV2605_REG_AUTOCALCOMP 0x18 ///< Auto-calibration compensation result register +#define DRV2605_REG_AUTOCALEMP 0x19 ///< Auto-calibration back-EMF result register +#define DRV2605_REG_FEEDBACK 0x1A ///< Feedback control register +#define DRV2605_REG_CONTROL1 0x1B ///< Control1 Register +#define DRV2605_REG_CONTROL2 0x1C ///< Control2 Register +#define DRV2605_REG_CONTROL3 0x1D ///< Control3 Register +#define DRV2605_REG_CONTROL4 0x1E ///< Control4 Register +#define DRV2605_REG_VBAT 0x21 ///< Vbat voltage-monitor register +#define DRV2605_REG_LRARESON 0x22 ///< LRA resonance-period register + +// Effects: +// 1 − Strong Click - 100% +// 2 − Strong Click - 60% +// 3 − Strong Click - 30% +// 4 − Sharp Click - 100% +// 5 − Sharp Click - 60% +// 6 − Sharp Click - 30% +// 7 − Soft Bump - 100% +// 8 − Soft Bump - 60% +// 9 − Soft Bump - 30% +// 10 − Double Click - 100% +// 11 − Double Click - 60% +// 12 − Triple Click - 100% +// 13 − Soft Fuzz - 60% +// 14 − Strong Buzz - 100% +// 15 − 750 ms Alert 100% +// 16 − 1000 ms Alert 100% +// 17 − Strong Click 1 - 100% +// 18 − Strong Click 2 - 80% +// 19 − Strong Click 3 - 60% +// 20 − Strong Click 4 - 30% +// 21 − Medium Click 1 - 100% +// 22 − Medium Click 2 - 80% +// 23 − Medium Click 3 - 60% +// 24 − Sharp Tick 1 - 100% +// 25 − Sharp Tick 2 - 80% +// 26 − Sharp Tick 3 – 60% +// 27 − Short Double Click Strong 1 – 100% +// 28 − Short Double Click Strong 2 – 80% +// 29 − Short Double Click Strong 3 – 60% +// 30 − Short Double Click Strong 4 – 30% +// 31 − Short Double Click Medium 1 – 100% +// 32 − Short Double Click Medium 2 – 80% +// 33 − Short Double Click Medium 3 – 60% +// 34 − Short Double Sharp Tick 1 – 100% +// 35 − Short Double Sharp Tick 2 – 80% +// 36 − Short Double Sharp Tick 3 – 60% +// 37 − Long Double Sharp Click Strong 1 – 100% +// 38 − Long Double Sharp Click Strong 2 – 80% +// 39 − Long Double Sharp Click Strong 3 – 60% +// 40 − Long Double Sharp Click Strong 4 – 30% +// 41 − Long Double Sharp Click Medium 1 – 100% +// 42 − Long Double Sharp Click Medium 2 – 80% +// 43 − Long Double Sharp Click Medium 3 – 60% +// 44 − Long Double Sharp Tick 1 – 100% +// 45 − Long Double Sharp Tick 2 – 80% +// 46 − Long Double Sharp Tick 3 – 60% +// 47 − Buzz 1 – 100% +// 48 − Buzz 2 – 80% +// 49 − Buzz 3 – 60% +// 50 − Buzz 4 – 40% +// 51 − Buzz 5 – 20% +// 52 − Pulsing Strong 1 – 100% +// 53 − Pulsing Strong 2 – 60% +// 54 − Pulsing Medium 1 – 100% +// 55 − Pulsing Medium 2 – 60% +// 56 − Pulsing Sharp 1 – 100% +// 57 − Pulsing Sharp 2 – 60% +// 58 − Transition Click 1 – 100% +// 59 − Transition Click 2 – 80% +// 60 − Transition Click 3 – 60% +// 61 − Transition Click 4 – 40% +// 62 − Transition Click 5 – 20% +// 63 − Transition Click 6 – 10% +// 64 − Transition Hum 1 – 100% +// 65 − Transition Hum 2 – 80% +// 66 − Transition Hum 3 – 60% +// 67 − Transition Hum 4 – 40% +// 68 − Transition Hum 5 – 20% +// 69 − Transition Hum 6 – 10% +// 70 − Transition Ramp Down Long Smooth 1 – 100 to 0% +// 71 − Transition Ramp Down Long Smooth 2 – 100 to 0% +// 72 − Transition Ramp Down Medium Smooth 1 – 100 to 0% +// 73 − Transition Ramp Down Medium Smooth 2 – 100 to 0% +// 74 − Transition Ramp Down Short Smooth 1 – 100 to 0% +// 75 − Transition Ramp Down Short Smooth 2 – 100 to 0% +// 76 − Transition Ramp Down Long Sharp 1 – 100 to 0% +// 77 − Transition Ramp Down Long Sharp 2 – 100 to 0% +// 78 − Transition Ramp Down Medium Sharp 1 – 100 to 0% +// 79 − Transition Ramp Down Medium Sharp 2 – 100 to 0% +// 80 − Transition Ramp Down Short Sharp 1 – 100 to 0% +// 81 − Transition Ramp Down Short Sharp 2 – 100 to 0% +// 82 − Transition Ramp Up Long Smooth 1 – 0 to 100% +// 83 − Transition Ramp Up Long Smooth 2 – 0 to 100% +// 84 − Transition Ramp Up Medium Smooth 1 – 0 to 100% +// 85 − Transition Ramp Up Medium Smooth 2 – 0 to 100% +// 86 − Transition Ramp Up Short Smooth 1 – 0 to 100% +// 87 − Transition Ramp Up Short Smooth 2 – 0 to 100% +// 88 − Transition Ramp Up Long Sharp 1 – 0 to 100% +// 89 − Transition Ramp Up Long Sharp 2 – 0 to 100% +// 90 − Transition Ramp Up Medium Sharp 1 – 0 to 100% +// 91 − Transition Ramp Up Medium Sharp 2 – 0 to 100% +// 92 − Transition Ramp Up Short Sharp 1 – 0 to 100% +// 93 − Transition Ramp Up Short Sharp 2 – 0 to 100% +// 94 − Transition Ramp Down Long Smooth 1 – 50 to 0% +// 95 − Transition Ramp Down Long Smooth 2 – 50 to 0% +// 96 − Transition Ramp Down Medium Smooth 1 – 50 to 0% +// 97 − Transition Ramp Down Medium Smooth 2 – 50 to 0% +// 98 − Transition Ramp Down Short Smooth 1 – 50 to 0% +// 99 − Transition Ramp Down Short Smooth 2 – 50 to 0% +// 100 − Transition Ramp Down Long Sharp 1 – 50 to 0% +// 101 − Transition Ramp Down Long Sharp 2 – 50 to 0% +// 102 − Transition Ramp Down Medium Sharp 1 – 50 to 0% +// 103 − Transition Ramp Down Medium Sharp 2 – 50 to 0% +// 104 − Transition Ramp Down Short Sharp 1 – 50 to 0% +// 105 − Transition Ramp Down Short Sharp 2 – 50 to 0% +// 106 − Transition Ramp Up Long Smooth 1 – 0 to 50% +// 107 − Transition Ramp Up Long Smooth 2 – 0 to 50% +// 108 − Transition Ramp Up Medium Smooth 1 – 0 to 50% +// 109 − Transition Ramp Up Medium Smooth 2 – 0 to 50% +// 110 − Transition Ramp Up Short Smooth 1 – 0 to 50% +// 111 − Transition Ramp Up Short Smooth 2 – 0 to 50% +// 112 − Transition Ramp Up Long Sharp 1 – 0 to 50% +// 113 − Transition Ramp Up Long Sharp 2 – 0 to 50% +// 114 − Transition Ramp Up Medium Sharp 1 – 0 to 50% +// 115 − Transition Ramp Up Medium Sharp 2 – 0 to 50% +// 116 − Transition Ramp Up Short Sharp 1 – 0 to 50% +// 117 − Transition Ramp Up Short Sharp 2 – 0 to 50% +// 118 − Long buzz for programmatic stopping – 100% +// 119 − Smooth Hum 1 (No kick or brake pulse) – 50% +// 120 − Smooth Hum 2 (No kick or brake pulse) – 40% +// 121 − Smooth Hum 3 (No kick or brake pulse) – 30% +// 122 − Smooth Hum 4 (No kick or brake pulse) – 20% +// 123 − Smooth Hum 5 (No kick or brake pulse) – 10% + +/**************************************************************************/ +/*! + @brief The DRV2605 driver class. +*/ +/**************************************************************************/ +void drv2605l_init(); +void writeRegister8(uint8_t reg, uint8_t val); +uint8_t readRegister8(uint8_t reg); +void drv2605l_setWaveform(uint8_t slot, uint8_t w); +void drv2605l_selectLibrary(uint8_t lib); +void drv2605l_go(void); +void drv2605l_stop(void); +void drv2605l_setMode(uint8_t mode); +void drv2605l_setRealtimeValue(uint8_t rtp); +// Select ERM (Eccentric Rotating Mass) or LRA (Linear Resonant Actuator) +// vibration motor The default is ERM, which is more common +void drv2605l_useERM(); +void drv2605l_useLRA(); + +#endif diff --git a/firmware/esp32-s3/main/config.c b/firmware/esp32-s3/main/config.c new file mode 100644 index 0000000..2b99db6 --- /dev/null +++ b/firmware/esp32-s3/main/config.c @@ -0,0 +1,39 @@ +#include "config.h" +#include "DRV2605L.h" +#include "keyboard.h" +#include "stdlib.h" +#include + +const struct user_config keyboard_default_user_config = { + .trigger_offset = DEFAULT_TRIGGER_OFFSET, + .reset_threshold = DEFAULT_RESET_THRESHOLD, + .rapid_trigger_offset = DEFAULT_RAPID_TRIGGER_OFFSET, + .screaming_velocity_trigger = DEFAULT_SCREAMING_VELOCITY_TRIGGER, + .tap_timeout = DEFAULT_TAP_TIMEOUT, + .keymaps = { + // clang-format off + [_BASE_LAYER] = { + {HID_KEY_ESCAPE, HID_KEY_GRAVE, HID_KEY_1, HID_KEY_2, HID_KEY_3, HID_KEY_4, HID_KEY_5, HID_KEY_6, HID_KEY_7, HID_KEY_8, HID_KEY_9, HID_KEY_0, HID_KEY_MINUS, HID_KEY_EQUAL, HID_KEY_BACKSPACE}, + {SPECIAL(HID_USAGE_CONSUMER_VOLUME_INCREMENT), HID_KEY_TAB, HID_KEY_Q, HID_KEY_W, HID_KEY_E, HID_KEY_R, HID_KEY_T, HID_KEY_Y, HID_KEY_U, HID_KEY_I, HID_KEY_O, HID_KEY_P, HID_KEY_BRACKET_LEFT, HID_KEY_BRACKET_RIGHT, HID_KEY_ENTER}, + {SPECIAL(HID_USAGE_CONSUMER_VOLUME_DECREMENT), HID_KEY_CAPS_LOCK, HID_KEY_A, HID_KEY_S, HID_KEY_D, HID_KEY_F, HID_KEY_G, HID_KEY_H, HID_KEY_J, HID_KEY_K, HID_KEY_L, HID_KEY_SEMICOLON, HID_KEY_APOSTROPHE, HID_KEY_EUROPE_1, XXXX}, + {XXXX, HID_KEY_SHIFT_LEFT, HID_KEY_EUROPE_2, HID_KEY_Z, HID_KEY_X, HID_KEY_C, HID_KEY_V, HID_KEY_B, HID_KEY_N, HID_KEY_M, HID_KEY_COMMA, HID_KEY_PERIOD, HID_KEY_SLASH, HID_KEY_SHIFT_RIGHT, XXXX}, + {XXXX, HID_KEY_CONTROL_LEFT, HID_KEY_ALT_LEFT, HID_KEY_GUI_LEFT, XXXX, HID_KEY_SPACE, XXXX, HID_KEY_SPACE, XXXX, HID_KEY_GUI_RIGHT, HID_KEY_ALT_RIGHT, XXXX, HID_KEY_ARROW_LEFT, SPECIAL(HID_USAGE_CONSUMER_PLAY_PAUSE), HID_KEY_ARROW_RIGHT}, + }, + [_TAP_LAYER] = { + {____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____}, + {____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____}, + {____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, XXXX}, + {XXXX, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, HID_KEY_ARROW_UP, XXXX}, + {XXXX, ____, ____, ____, XXXX, ____, XXXX, ____, XXXX, ____, ____, XXXX, ____, HID_KEY_ARROW_DOWN, ____}, + }, + // clang-format on + }}; + +// {adc_channel, amux_channel} +const uint8_t channels_by_row_col[MATRIX_ROWS][MATRIX_COLS][2] = { + {{0, 10}, {0, 8}, {0, 7}, {0, 5}, {1, 9}, {1, 8}, {1, 6}, {2, 10}, {2, 9}, {2, 7}, {2, 6}, {3, 9}, {3, 8}, {3, 6}, {4, 2}}, + {{0, 11}, {0, 9}, {0, 6}, {0, 4}, {1, 10}, {1, 7}, {1, 5}, {2, 11}, {2, 8}, {2, 5}, {2, 4}, {3, 10}, {3, 7}, {3, 5}, {4, 1}}, + {{0, 12}, {0, 14}, {0, 2}, {1, 11}, {1, 14}, {1, 1}, {1, 4}, {2, 12}, {2, 15}, {2, 3}, {3, 11}, {3, 14}, {3, 1}, {3, 4}, {XXXX, XXXX}}, + {{XXXX, XXXX}, {0, 13}, {0, 0}, {0, 3}, {1, 13}, {1, 15}, {1, 2}, {1, 3}, {2, 14}, {2, 0}, {2, 2}, {3, 12}, {3, 15}, {3, 3}, {XXXX, XXXX}}, + {{XXXX, XXXX}, {0, 15}, {0, 1}, {1, 12}, {XXXX, XXXX}, {1, 0}, {XXXX, XXXX}, {2, 13}, {XXXX, XXXX}, {2, 1}, {3, 13}, {XXXX, XXXX}, {3, 0}, {3, 2}, {4, 0}}, +}; \ No newline at end of file diff --git a/firmware/esp32-s3/main/config.h b/firmware/esp32-s3/main/config.h new file mode 100644 index 0000000..55950ef --- /dev/null +++ b/firmware/esp32-s3/main/config.h @@ -0,0 +1,22 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define DEFAULT_TRIGGER_OFFSET 64 +#define DEFAULT_RESET_THRESHOLD 3 +#define DEFAULT_RAPID_TRIGGER_OFFSET 40 +#define DEFAULT_SCREAMING_VELOCITY_TRIGGER 45 +#define DEFAULT_TAP_TIMEOUT 200 + +#define ADC_CHANNEL_COUNT 5 +#define AMUX_SELECT_PINS_COUNT 4 +#define AMUX_CHANNEL_COUNT 16 + +#define MATRIX_ROWS 5 +#define MATRIX_COLS 15 + +extern const struct user_config keyboard_default_user_config; +extern const uint8_t channels_by_row_col[MATRIX_ROWS][MATRIX_COLS][2]; + +#endif /* __CONFIG_H */ diff --git a/firmware/esp32-s3/main/hid.c b/firmware/esp32-s3/main/hid.c new file mode 100644 index 0000000..fc01828 --- /dev/null +++ b/firmware/esp32-s3/main/hid.c @@ -0,0 +1,341 @@ +#include "tusb.h" +#include "usb_descriptors.h" +#include +#include +#include + +extern uint8_t const desc_ms_os_20[]; +extern struct key keyboard_keys[ADC_CHANNEL_COUNT][AMUX_CHANNEL_COUNT]; +extern struct user_config keyboard_user_config; +extern uint32_t keyboard_last_cycle_duration; + +static uint8_t should_send_consumer_report = 0; +static uint8_t should_send_keyboard_report = 0; + +static uint8_t modifiers = 0; +static uint8_t keycodes[6] = {0}; +// static uint8_t is_screaming = 0; +static uint8_t consumer_report = 0; + +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t usb_vendor_control_buffer[400]; + +void hid_init() { + tud_init(BOARD_TUD_RHPORT); +} + +void hid_task() { + tud_task(); + + if ((should_send_consumer_report || should_send_keyboard_report) && tud_hid_ready()) { + if (tud_suspended()) { + tud_remote_wakeup(); + } else { + if (should_send_consumer_report) { + should_send_consumer_report = 0; + tud_hid_report(REPORT_ID_CONSUMER_CONTROL, &consumer_report, 2); + } else if (should_send_keyboard_report) { + should_send_keyboard_report = 0; + tud_hid_keyboard_report(REPORT_ID_KEYBOARD, modifiers, keycodes); + } + } + } +} + +void hid_press_key(struct key *key, uint8_t layer) { + switch (key->layers[layer].type) { + case KEY_TYPE_MODIFIER: + modifiers |= key->layers[layer].value; + should_send_keyboard_report = 1; + break; + + case KEY_TYPE_NORMAL: + for (uint8_t i = 0; i < 6; i++) { + if (keycodes[i] == 0) { + keycodes[i] = key->layers[layer].value; + // if the key is violently pressed, automatically add the MAJ modifier :) + // if (is_screaming) { + // is_screaming = 0; + // modifiers &= ~get_bitmask_for_modifier(HID_KEY_SHIFT_LEFT); + // } else if (i == 0 && key->state.velocity > keyboard_user_config.screaming_velocity_trigger) { + // is_screaming = 1; + // modifiers |= get_bitmask_for_modifier(HID_KEY_SHIFT_LEFT); + // } + should_send_keyboard_report = 1; + break; + } + } + break; + + case KEY_TYPE_CONSUMER_CONTROL: + consumer_report = key->layers[layer].value; + should_send_consumer_report = 1; + break; + + default: + break; + } +} + +void hid_release_key(struct key *key, uint8_t layer) { + switch (key->layers[layer].type) { + case KEY_TYPE_MODIFIER: + modifiers &= ~key->layers[layer].value; + should_send_keyboard_report = 1; + break; + + case KEY_TYPE_NORMAL: + for (uint8_t i = 0; i < 6; i++) { + if (keycodes[i] == key->layers[layer].value) { + keycodes[i] = 0; + // if (is_screaming) { + // is_screaming = 0; + // modifiers &= ~get_bitmask_for_modifier(HID_KEY_SHIFT_LEFT); + // } + should_send_keyboard_report = 1; + break; + } + } + break; + + case KEY_TYPE_CONSUMER_CONTROL: + consumer_report = 0; + should_send_consumer_report = 1; + break; + + default: + break; + } +} + +// Invoked when received SET_PROTOCOL request +// protocol is either HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1) +void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol) { + (void)instance; + (void)protocol; + + // nothing to do since we use the same compatible boot report for both Boot and Report mode. + // TODO set a indicator for user +} + +// Invoked when sent REPORT successfully to host +// Application can use this to send the next report +// Note: For composite reports, report[0] is report ID +void tud_hid_report_complete_cb(uint8_t instance, uint8_t const *report, uint16_t len) { + (void)instance; + (void)report; + (void)len; +} + +// Invoked when received GET_REPORT control request +// Application must fill buffer report's content and return its length. +// Return zero will cause the stack to STALL request +uint16_t tud_hid_get_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t *buffer, uint16_t reqlen) { + // TODO not Implemented + (void)instance; + (void)report_id; + (void)report_type; + (void)buffer; + (void)reqlen; + + return 0; +} + +// Invoked when received SET_REPORT control request or +// received data on OUT endpoint ( Report ID = 0, Type = 0 ) +void tud_hid_set_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t const *buffer, uint16_t bufsize) { + (void)report_id; + // if (instance == 1 && report_id == 0) { + // keyboard_write_config(buffer, bufsize); + + // keyboard_init_keys(); + // } +} + +// // Invoked when cdc when line state changed e.g connected/disconnected +// void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) { +// (void)itf; + +// // connected +// if (dtr && rts) { +// // print initial message when connected +// tud_cdc_write(&keyboard_user_config, 3); +// tud_cdc_write_str('\r\n'); +// tud_cdc_write_flush(); +// } +// } + +// // Invoked when CDC interface received data from host +// void tud_cdc_rx_cb(uint8_t itf) { +// (void)itf; +// } + +// Invoked when a control transfer occurred on an interface of this class +// Driver response accordingly to the request and the transfer stage (setup/data/ack) +// return false to stall control endpoint (e.g unsupported request) +bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) { + switch (request->bmRequestType_bit.type) { + case TUSB_REQ_TYPE_VENDOR: { + switch (request->bRequest) { + + case VENDOR_REQUEST_CONFIG: { + switch (request->wValue) { + case VENDOR_VALUE_GET_LENGTH: { + if (stage == CONTROL_STAGE_SETUP) { + uint16_t size = sizeof(keyboard_user_config); + return tud_control_xfer(rhport, request, &size, request->wLength); + } + + break; + } + + case VENDOR_VALUE_GET: { + if (stage == CONTROL_STAGE_SETUP) { + return tud_control_xfer(rhport, request, &keyboard_user_config, request->wLength); + } + + break; + } + + case VENDOR_VALUE_SET: { + if (stage == CONTROL_STAGE_SETUP) { + return tud_control_xfer(rhport, request, usb_vendor_control_buffer, request->wLength); + } else if (stage == CONTROL_STAGE_DATA) { + if (!keyboard_write_config(&usb_vendor_control_buffer, 0, request->wLength)) { + return false; + } + keyboard_read_config(); + keyboard_init_keys(); + } + + break; + } + + default: + break; + } + } + + case VENDOR_REQUEST_RESET_CONFIG: { + if (request->wValue == VENDOR_VALUE_SET) { + if (stage == CONTROL_STAGE_SETUP) { + if (!keyboard_write_config(&keyboard_default_user_config, 0, sizeof keyboard_default_user_config)) { + return false; + } + keyboard_read_config(); + keyboard_init_keys(); + return tud_control_status(rhport, request); + } + + break; + } + } + + case VENDOR_REQUEST_DFU_MODE: { + if (request->wValue == VENDOR_VALUE_SET) { + if (stage == CONTROL_STAGE_SETUP) { + return tud_control_status(rhport, request); + } + + break; + } + } + + case VENDOR_REQUEST_KEYS: { + switch (request->wValue) { + case VENDOR_VALUE_GET_LENGTH: { + if (stage == CONTROL_STAGE_SETUP) { + uint16_t size = sizeof(keyboard_keys); + return tud_control_xfer(rhport, request, &size, request->wLength); + } + + break; + } + + case VENDOR_VALUE_GET: { + if (stage == CONTROL_STAGE_SETUP) { + return tud_control_xfer(rhport, request, &keyboard_keys, request->wLength); + } + + break; + } + + default: + break; + } + } + + case VENDOR_REQUEST_CYCLE_DURATION: { + switch (request->wValue) { + case VENDOR_VALUE_GET_LENGTH: { + if (stage == CONTROL_STAGE_SETUP) { + uint16_t size = sizeof(keyboard_last_cycle_duration); + return tud_control_xfer(rhport, request, &size, request->wLength); + } + + break; + } + + case VENDOR_VALUE_GET: { + if (stage == CONTROL_STAGE_SETUP) { + return tud_control_xfer(rhport, request, &keyboard_last_cycle_duration, request->wLength); + } + + break; + } + + default: + break; + } + } + + case VENDOR_REQUEST_WEBUSB: { + if (stage == CONTROL_STAGE_SETUP) { + return tud_control_status(rhport, request); + } + + break; + } + + case VENDOR_REQUEST_MICROSOFT: { + if (stage == CONTROL_STAGE_SETUP) { + if (request->wIndex == 7) { + // Get Microsoft OS 2.0 compatible descriptor + uint16_t total_len; + memcpy(&total_len, desc_ms_os_20 + 8, 2); + + return tud_control_xfer(rhport, request, (void *)(uintptr_t)desc_ms_os_20, total_len); + } + + return false; + } + + break; + } + + default: + break; + } + } + + case TUSB_REQ_TYPE_CLASS: { + if (stage == CONTROL_STAGE_SETUP) { + if (request->bRequest == 0x22) { + // response with status OK + return tud_control_status(rhport, request); + } + + return false; + } + + break; + } + + default: + break; + } + + if (stage != CONTROL_STAGE_SETUP) { + return true; + } + return false; +} \ No newline at end of file diff --git a/firmware/esp32-s3/main/hid.h b/firmware/esp32-s3/main/hid.h new file mode 100644 index 0000000..201dae5 --- /dev/null +++ b/firmware/esp32-s3/main/hid.h @@ -0,0 +1,22 @@ +#ifndef __HID_H +#define __HID_H + +#include "keyboard.h" +#include + +#define VENDOR_REQUEST_KEYS 0xfe +#define VENDOR_REQUEST_CONFIG 0xff +#define VENDOR_REQUEST_RESET_CONFIG 0xfd +#define VENDOR_REQUEST_DFU_MODE 0xfc +#define VENDOR_REQUEST_CYCLE_DURATION 0xfb + +#define VENDOR_VALUE_GET_LENGTH 0x00 +#define VENDOR_VALUE_GET 0x01 +#define VENDOR_VALUE_SET 0x02 + +void hid_init(); +void hid_task(); +void hid_press_key(struct key *key, uint8_t layer); +void hid_release_key(struct key *key, uint8_t layer); + +#endif /* __HID_H */ diff --git a/firmware/esp32-s3/main/keyboard.c b/firmware/esp32-s3/main/keyboard.c new file mode 100644 index 0000000..535d974 --- /dev/null +++ b/firmware/esp32-s3/main/keyboard.c @@ -0,0 +1,320 @@ +#include "keyboard.h" +#include "DRV2605L.h" +#include "esp_log.h" +#include "hid.h" +#include +#include + +const static char *TAG = "MACROLEV"; + +struct key keyboard_keys[ADC_CHANNEL_COUNT][AMUX_CHANNEL_COUNT] = {0}; + +struct user_config keyboard_user_config = {0}; + +uint32_t keyboard_last_cycle_duration = 0; + +static uint8_t key_triggered = 0; + +uint8_t get_bitmask_for_modifier(uint8_t keycode) { + switch (keycode) { + case HID_KEY_CONTROL_LEFT: + return 0b00000001; + case HID_KEY_SHIFT_LEFT: + return 0b00000010; + case HID_KEY_ALT_LEFT: + return 0b00000100; + case HID_KEY_GUI_LEFT: + return 0b00001000; + case HID_KEY_CONTROL_RIGHT: + return 0b00010000; + case HID_KEY_SHIFT_RIGHT: + return 0b00100000; + case HID_KEY_ALT_RIGHT: + return 0b01000000; + case HID_KEY_GUI_RIGHT: + return 0b10000000; + default: + return 0b00000000; + } +} + +uint16_t get_usage_consumer_control(uint16_t value) { + if (value > 0xFF) { + return value & 0b0111111111111111; + } else { + return 0; + } +} + +void init_key(uint8_t adc_channel, uint8_t amux_channel, uint8_t row, uint8_t column) { + struct key *key = &keyboard_keys[adc_channel][amux_channel]; + + key->is_enabled = 1; + key->is_idle = 0; + key->row = row; + key->column = column; + + key->calibration.cycles_count = 0; + key->calibration.idle_value = IDLE_VALUE_APPROX; + key->calibration.max_distance = MAX_DISTANCE_APPROX; + + key->actuation.status = STATUS_RESET; + key->actuation.trigger_offset = keyboard_user_config.trigger_offset; + key->actuation.reset_offset = keyboard_user_config.trigger_offset - keyboard_user_config.reset_threshold; + key->actuation.rapid_trigger_offset = keyboard_user_config.rapid_trigger_offset; + key->actuation.is_continuous_rapid_trigger_enabled = 0; + + for (uint8_t i = 0; i < LAYERS_COUNT; i++) { + if (keyboard_user_config.keymaps[i][row][column] != ____) { + uint16_t usage_consumer_control = get_usage_consumer_control(keyboard_user_config.keymaps[i][row][column]); + if (usage_consumer_control) { + key->layers[i].type = KEY_TYPE_CONSUMER_CONTROL; + key->layers[i].value = usage_consumer_control; + } else { + uint8_t bitmask = get_bitmask_for_modifier(keyboard_user_config.keymaps[i][row][column]); + if (bitmask) { + key->layers[i].type = KEY_TYPE_MODIFIER; + key->layers[i].value = bitmask; + } else { + key->layers[i].type = KEY_TYPE_NORMAL; + key->layers[i].value = keyboard_user_config.keymaps[i][row][column]; + } + } + } + } +} + +uint8_t update_key_state(struct key *key) { + struct state state; + + // Get a reading + state.value = keyboard_read_adc(); + if (key->row == 0 && key->column == 0) { + ESP_LOGI(TAG, "Row: %d, Col: %d, Value: %x", key->row, key->column, state.value); + } + + if (key->calibration.cycles_count < CALIBRATION_CYCLES) { + // Calibrate idle value + float delta = 0.6; + key->calibration.idle_value = (1 - delta) * state.value + delta * key->calibration.idle_value; + key->calibration.cycles_count++; + + return 0; + } + + // Calibrate idle value + if (state.value > key->calibration.idle_value) { + // opti possible sur float + float delta = 0.8; + key->calibration.idle_value = (1 - delta) * state.value + delta * key->calibration.idle_value; + state.value = key->calibration.idle_value; + } + + // Do nothing if key is idle + if (key->state.distance == 0 && state.value >= key->calibration.idle_value - IDLE_VALUE_OFFSET) { + if (key->idle_counter >= IDLE_CYCLES_UNTIL_SLEEP) { + key->is_idle = 1; + return 0; + } + key->idle_counter++; + } + + // Get distance from top + if (state.value >= key->calibration.idle_value - IDLE_VALUE_OFFSET) { + state.distance = 0; + key->actuation.direction_changed_point = 0; + } else { + state.distance = key->calibration.idle_value - IDLE_VALUE_OFFSET - state.value; + key->is_idle = 0; + key->idle_counter = 0; + } + + // Calibrate max distance value + if (state.distance > key->calibration.max_distance) { + key->calibration.max_distance = state.distance; + } + + // Limit max distance + if (state.distance >= key->calibration.max_distance - MAX_DISTANCE_OFFSET) { + state.distance = key->calibration.max_distance; + } + + // Map distance in percentages + state.distance_8bits = (state.distance * 0xff) / key->calibration.max_distance; + + float delta = 0.8; + state.filtered_distance = (1 - delta) * state.distance_8bits + delta * key->state.filtered_distance; + state.filtered_distance_8bits = state.filtered_distance; + + // Update velocity + state.velocity = state.filtered_distance_8bits - key->state.filtered_distance_8bits; + + // Update direction + if (key->state.velocity > 0 && state.velocity > 0 && key->actuation.direction != GOING_DOWN) { + key->actuation.direction = GOING_DOWN; + if (key->actuation.direction_changed_point != 0) { + key->actuation.direction_changed_point = key->state.filtered_distance_8bits; + } + } else if (key->state.velocity < 0 && state.velocity < 0 && key->actuation.direction != GOING_UP) { + key->actuation.direction = GOING_UP; + if (key->actuation.direction_changed_point != 255) { + key->actuation.direction_changed_point = key->state.filtered_distance_8bits; + } + } + + key->state = state; + return 1; +} + +void update_key_actuation(struct key *key) { + /** + * https://www.youtube.com/watch?v=_Sl-T6iQr8U&t + * + * ----- |--------| - + * | | | | + * is_before_reset_offset | | | | + * | | | | Continuous rapid trigger domain (deactivated when full_reset) + * ----- | ------ | <- reset_offset | + * | | | | + * ----- | ------ | <- trigger_offset - + * | | | | + * | | | | + * is_after_trigger_offset | | | | Rapid trigger domain + * | | | | + * | | | | + * ----- |--------| - + * + */ + + // if rapid trigger enable, move trigger and reset offsets according to the distance taht began the trigger + + uint32_t now = keyboard_get_time(); + uint8_t is_after_trigger_offset = key->state.distance_8bits > key->actuation.trigger_offset; + uint8_t is_before_reset_offset = key->state.distance_8bits < key->actuation.reset_offset; + uint8_t has_rapid_trigger = key->actuation.rapid_trigger_offset != 0; + uint8_t is_after_rapid_trigger_offset = key->state.distance_8bits > key->actuation.direction_changed_point - key->actuation.rapid_trigger_offset + keyboard_user_config.reset_threshold; + uint8_t is_before_rapid_reset_offset = key->state.distance_8bits < key->actuation.direction_changed_point - key->actuation.rapid_trigger_offset; + + switch (key->actuation.status) { + + case STATUS_RESET: + // if reset, can be triggered or tap + if (is_after_trigger_offset) { + if (key->layers[_TAP_LAYER].value) { + key->actuation.status = STATUS_MIGHT_BE_TAP; + // key_triggered = 1; + } else { + key->actuation.status = STATUS_TRIGGERED; + key_triggered = 1; + hid_press_key(key, _BASE_LAYER); + } + key->actuation.triggered_at = now; + } + break; + + case STATUS_RAPID_TRIGGER_RESET: + if (!has_rapid_trigger) { + key->actuation.status = STATUS_RESET; + break; + } + // if reset, can be triggered or tap + if (is_after_trigger_offset && key->actuation.direction == GOING_DOWN && is_after_rapid_trigger_offset) { + if (key->layers[_TAP_LAYER].value) { + key->actuation.status = STATUS_MIGHT_BE_TAP; + key_triggered = 1; + } else { + key->actuation.status = STATUS_TRIGGERED; + key_triggered = 1; + hid_press_key(key, _BASE_LAYER); + } + key->actuation.triggered_at = now; + } else if (is_before_reset_offset) { + key->actuation.status = STATUS_RESET; + } + break; + + case STATUS_TAP: + // if tap, can be reset + key->actuation.status = STATUS_RESET; + hid_release_key(key, _TAP_LAYER); + break; + + case STATUS_TRIGGERED: + // if triggered, can be reset + if (is_before_reset_offset) { + key->actuation.status = STATUS_RESET; + hid_release_key(key, _BASE_LAYER); + } else if (has_rapid_trigger && key->actuation.direction == GOING_UP && is_before_rapid_reset_offset) { + key->actuation.status = STATUS_RAPID_TRIGGER_RESET; + hid_release_key(key, _BASE_LAYER); + } + break; + + default: + break; + } +} + +void update_key(struct key *key) { + if (!update_key_state(key)) { + return; + } + + update_key_actuation(key); +} + +void keyboard_init_keys() { + // keyboard_read_config(); + + for (uint8_t row = 0; row < MATRIX_ROWS; row++) { + for (uint8_t col = 0; col < MATRIX_COLS; col++) { + if (channels_by_row_col[row][col][0] != XXXX) { + init_key(channels_by_row_col[row][col][0], channels_by_row_col[row][col][1], row, col); + } + } + } +} + +void keyboard_task() { + uint32_t started_at = keyboard_get_time(); + key_triggered = 0; + + for (uint8_t amux_channel = 0; amux_channel < AMUX_CHANNEL_COUNT; amux_channel++) { + keyboard_select_amux(amux_channel); + + for (uint8_t adc_channel = 0; adc_channel < ADC_CHANNEL_COUNT; adc_channel++) { + if (keyboard_keys[adc_channel][amux_channel].is_enabled == 0) { + continue; + } + keyboard_select_adc(adc_channel); + + update_key(&keyboard_keys[adc_channel][amux_channel]); + + keyboard_close_adc(); + } + } + + // If a key might be tap and a non tap key has been triggered, then the might be tap key is a normal trigger + for (uint8_t amux_channel = 0; amux_channel < AMUX_CHANNEL_COUNT; amux_channel++) { + for (uint8_t adc_channel = 0; adc_channel < ADC_CHANNEL_COUNT; adc_channel++) { + if (keyboard_keys[adc_channel][amux_channel].is_enabled == 0 || keyboard_keys[adc_channel][amux_channel].actuation.status != STATUS_MIGHT_BE_TAP) { + continue; + } + + struct key *key = &keyboard_keys[adc_channel][amux_channel]; + uint8_t is_before_reset_offset = key->state.distance_8bits < key->actuation.reset_offset; + uint8_t is_before_timeout = keyboard_get_time() - key->actuation.triggered_at <= keyboard_user_config.tap_timeout; + + // if might be tap, can be tap or triggered + if (is_before_reset_offset && is_before_timeout) { + key->actuation.status = STATUS_TAP; + hid_press_key(key, _TAP_LAYER); + } else if (!is_before_timeout || key_triggered) { + key->actuation.status = STATUS_TRIGGERED; + hid_press_key(key, _BASE_LAYER); + } + } + } + + keyboard_last_cycle_duration = keyboard_get_time() - started_at; +} diff --git a/firmware/esp32-s3/main/keyboard.h b/firmware/esp32-s3/main/keyboard.h new file mode 100644 index 0000000..3bfd07d --- /dev/null +++ b/firmware/esp32-s3/main/keyboard.h @@ -0,0 +1,109 @@ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __KEYBOARD_H +#define __KEYBOARD_H + +#include "config.h" +#include + +#define CALIBRATION_CYCLES 20 + +#define IDLE_VALUE_APPROX 1800 +#define MAX_DISTANCE_APPROX 500 +#define IDLE_VALUE_OFFSET 10 +#define MAX_DISTANCE_OFFSET 60 +#define IDLE_CYCLES_UNTIL_SLEEP 15 + +#define XXXX 0xff +#define ____ 0x00 + +#define SPECIAL(X) (0b1000000000000000 | X) + +struct __attribute__((__packed__)) calibration { + uint16_t cycles_count; + uint16_t idle_value; + uint16_t max_distance; +}; + +enum direction { + GOING_UP, + GOING_DOWN, +}; + +struct __attribute__((__packed__)) state { + uint16_t value; + uint16_t distance; + uint8_t distance_8bits; + float filtered_distance; + int8_t velocity; + uint8_t filtered_distance_8bits; +}; + +enum actuation_status { + STATUS_MIGHT_BE_TAP, + STATUS_TAP, + STATUS_TRIGGERED, + STATUS_RESET, + STATUS_RAPID_TRIGGER_RESET +}; + +struct __attribute__((__packed__)) actuation { + enum direction direction; + uint8_t direction_changed_point; + enum actuation_status status; + uint8_t reset_offset; + uint8_t trigger_offset; + uint8_t rapid_trigger_offset; + uint8_t is_continuous_rapid_trigger_enabled; + uint32_t triggered_at; +}; + +enum key_type { + KEY_TYPE_EMPTY, + KEY_TYPE_NORMAL, + KEY_TYPE_MODIFIER, + KEY_TYPE_CONSUMER_CONTROL, +}; + +struct __attribute__((__packed__)) layer { + enum key_type type; + uint16_t value; +}; + +enum { + _BASE_LAYER, + _TAP_LAYER, + LAYERS_COUNT +}; + +struct __attribute__((__packed__)) key { + uint8_t is_enabled; + uint8_t row; + uint8_t column; + uint8_t idle_counter; + uint8_t is_idle; + struct layer layers[LAYERS_COUNT]; + struct calibration calibration; + struct state state; + struct actuation actuation; +}; + +struct user_config { + uint8_t trigger_offset; + uint8_t reset_threshold; + uint8_t rapid_trigger_offset; + uint8_t screaming_velocity_trigger; + uint16_t tap_timeout; + uint16_t keymaps[LAYERS_COUNT][MATRIX_ROWS][MATRIX_COLS]; +}; + +void keyboard_task(); +void keyboard_init_keys(); +extern void keyboard_read_config(); +extern uint8_t keyboard_write_config(uint8_t *buffer, uint16_t offset, uint16_t size); +extern void keyboard_select_amux(uint8_t amux_channel); +extern void keyboard_select_adc(uint8_t adc_channel); +extern uint16_t keyboard_read_adc(); +extern void keyboard_close_adc(); +extern uint32_t keyboard_get_time(); + +#endif /* __KEYBOARD_H */ diff --git a/firmware/esp32-s3/main/main.c b/firmware/esp32-s3/main/main.c new file mode 100644 index 0000000..4787180 --- /dev/null +++ b/firmware/esp32-s3/main/main.c @@ -0,0 +1,173 @@ +#include "config.h" +#include "driver/gpio.h" +#include "esp_adc/adc_cali.h" +#include "esp_adc/adc_cali_scheme.h" +#include "esp_adc/adc_oneshot.h" +#include "esp_log.h" +#include "esp_timer.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "hid.h" +#include "keyboard.h" +#include "soc/soc_caps.h" +#include +#include +#include + +const static char *TAG = "MACROLEV"; + +#define CONFIG_ADDRESS 0x42000000 + +#define GPIO_SELECT_0 5 +#define GPIO_SELECT_1 6 +#define GPIO_SELECT_2 9 +#define GPIO_SELECT_3 10 +/* + * Let's say, GPIO_SELECT_0=18, GPIO_SELECT_1=19 + * In binary representation, + * 1ULL<> i) & 1); + } +} + +void keyboard_select_adc(uint8_t _adc_channel) { + adc_channel = _adc_channel; +} + +uint16_t keyboard_read_adc() { + static int out_raw; + ESP_ERROR_CHECK(adc_oneshot_read(adc_handle, adc_channel, &out_raw)); + return out_raw; +} + +void keyboard_close_adc() { +} + +uint32_t keyboard_get_time() { + return esp_timer_get_time(); +} \ No newline at end of file diff --git a/firmware/esp32-s3/main/tusb_config.h b/firmware/esp32-s3/main/tusb_config.h new file mode 100644 index 0000000..3e450af --- /dev/null +++ b/firmware/esp32-s3/main/tusb_config.h @@ -0,0 +1,109 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef _TUSB_CONFIG_H_ +#define _TUSB_CONFIG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------+ +// Board Specific Configuration +//--------------------------------------------------------------------+ + +// RHPort number used for device can be defined by board.mk, default to port 0 +#ifndef BOARD_TUD_RHPORT +#define BOARD_TUD_RHPORT 0 +#endif + +// RHPort max operational speed can defined by board.mk +#ifndef BOARD_TUD_MAX_SPEED +#define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED +#endif + +//-------------------------------------------------------------------- +// COMMON CONFIGURATION +//-------------------------------------------------------------------- + +#define CFG_TUSB_MCU OPT_MCU_STM32F4 + +#ifndef CFG_TUSB_OS +#define CFG_TUSB_OS OPT_OS_NONE +#endif + +#ifndef CFG_TUSB_DEBUG +#define CFG_TUSB_DEBUG 0 +#endif + +// Enable Device stack +#define CFG_TUD_ENABLED 1 + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED + +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUSB_MEM_SECTION +#define CFG_TUSB_MEM_SECTION +#endif + +#ifndef CFG_TUSB_MEM_ALIGN +#define CFG_TUSB_MEM_ALIGN __attribute__((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// DEVICE CONFIGURATION +//-------------------------------------------------------------------- + +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 +#endif + +//------------- CLASS -------------// +#define CFG_TUD_HID 1 +#define CFG_TUD_CDC 0 +#define CFG_TUD_MSC 0 +#define CFG_TUD_MIDI 0 +#define CFG_TUD_VENDOR 1 + +// HID buffer size Should be sufficient to hold ID (if any) + Data +#define CFG_TUD_HID_EP_BUFSIZE 16 + +// Vendor FIFO size of TX and RX +// If not configured vendor endpoints will not be buffered +#define CFG_TUD_VENDOR_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_VENDOR_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) + +#ifdef __cplusplus +} +#endif + +#endif /* _TUSB_CONFIG_H_ */ diff --git a/firmware/esp32-s3/main/usb_descriptors.c b/firmware/esp32-s3/main/usb_descriptors.c new file mode 100644 index 0000000..0ab79f9 --- /dev/null +++ b/firmware/esp32-s3/main/usb_descriptors.c @@ -0,0 +1,280 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "usb_descriptors.h" +#include "tusb.h" + +/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug. + * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC. + * + * Auto ProductID layout's Bitmap: + * [MSB] HID | MSC | CDC [LSB] + */ +#define _PID_MAP(itf, n) ((CFG_TUD_##itf) << (n)) +#define USB_PID (0x5000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ + _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4)) + +//--------------------------------------------------------------------+ +// Device Descriptors +//--------------------------------------------------------------------+ +tusb_desc_device_t const desc_device = + { + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = 0x0210, // at least 2.1 or 3.x for BOS & webUSB + + // Use Interface Association Descriptor (IAD) for CDC + // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + + .idVendor = 0xCafe, + .idProduct = USB_PID + 11, + .bcdDevice = 0x0100, + + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, + + .bNumConfigurations = 0x01, +}; + +// Invoked when received GET DEVICE DESCRIPTOR +// Application return pointer to descriptor +uint8_t const *tud_descriptor_device_cb(void) { + return (uint8_t const *)&desc_device; +} + +//--------------------------------------------------------------------+ +// HID Report Descriptor +//--------------------------------------------------------------------+ + +uint8_t const desc_hid_keyboard_report[] = + { + TUD_HID_REPORT_DESC_KEYBOARD(HID_REPORT_ID(REPORT_ID_KEYBOARD)), + TUD_HID_REPORT_DESC_CONSUMER(HID_REPORT_ID(REPORT_ID_CONSUMER_CONTROL)), +}; + +// Invoked when received GET HID REPORT DESCRIPTOR +// Application return pointer to descriptor +// Descriptor contents must exist long enough for transfer to complete +uint8_t const *tud_hid_descriptor_report_cb(uint8_t instance) { + if (instance == ITF_NUM_KEYBOARD) { + return desc_hid_keyboard_report; + } + + return NULL; +} + +//--------------------------------------------------------------------+ +// Configuration Descriptor +//--------------------------------------------------------------------+ + +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_HID_DESC_LEN + TUD_VENDOR_DESC_LEN) + +#define EPNUM_KEYBOARD 1 +#define EPNUM_VENDOR_IN 2 +#define EPNUM_VENDOR_OUT 2 + +uint8_t const desc_configuration[] = + { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + + // Interface number, string index, protocol, report descriptor len, EP In address, size & polling interval + TUD_HID_DESCRIPTOR(ITF_NUM_KEYBOARD, 6, HID_ITF_PROTOCOL_KEYBOARD, sizeof(desc_hid_keyboard_report), 0x80 | EPNUM_KEYBOARD, CFG_TUD_HID_EP_BUFSIZE, 10), + + // Interface number, string index, EP Out & IN address, EP size + TUD_VENDOR_DESCRIPTOR(ITF_NUM_VENDOR, 5, EPNUM_VENDOR_OUT, 0x80 | EPNUM_VENDOR_IN, TUD_OPT_HIGH_SPEED ? 512 : 64), +}; + +// Invoked when received GET CONFIGURATION DESCRIPTOR +// Application return pointer to descriptor +// Descriptor contents must exist long enough for transfer to complete +uint8_t const *tud_descriptor_configuration_cb(uint8_t index) { + (void)index; // for multiple configurations + return desc_configuration; +} + +//--------------------------------------------------------------------+ +// BOS Descriptor +//--------------------------------------------------------------------+ + +/* Microsoft OS 2.0 registry property descriptor +Per MS requirements https://msdn.microsoft.com/en-us/library/windows/hardware/hh450799(v=vs.85).aspx +device should create DeviceInterfaceGUIDs. It can be done by driver and +in case of real PnP solution device should expose MS "Microsoft OS 2.0 +registry property descriptor". Such descriptor can insert any record +into Windows registry per device/configuration/interface. In our case it +will insert "DeviceInterfaceGUIDs" multistring property. + +GUID is freshly generated and should be OK to use. + +https://developers.google.com/web/fundamentals/native-hardware/build-for-webusb/ +(Section Microsoft OS compatibility descriptors) +*/ + +#define BOS_TOTAL_LEN (TUD_BOS_DESC_LEN + TUD_BOS_WEBUSB_DESC_LEN + TUD_BOS_MICROSOFT_OS_DESC_LEN) + +#define MS_OS_20_DESC_LEN 0xB2 + +// BOS Descriptor is required for webUSB +uint8_t const desc_bos[] = + { + // total length, number of device caps + TUD_BOS_DESCRIPTOR(BOS_TOTAL_LEN, 2), + + // Vendor Code, iLandingPage + TUD_BOS_WEBUSB_DESCRIPTOR(VENDOR_REQUEST_WEBUSB, 1), + + // Microsoft OS 2.0 descriptor + TUD_BOS_MS_OS_20_DESCRIPTOR(MS_OS_20_DESC_LEN, VENDOR_REQUEST_MICROSOFT)}; + +uint8_t const *tud_descriptor_bos_cb(void) { + return desc_bos; +} + +uint8_t const desc_ms_os_20[] = + { + // Set header: length, type, windows version, total length + U16_TO_U8S_LE(0x000A), U16_TO_U8S_LE(MS_OS_20_SET_HEADER_DESCRIPTOR), U32_TO_U8S_LE(0x06030000), U16_TO_U8S_LE(MS_OS_20_DESC_LEN), + + // Configuration subset header: length, type, configuration index, reserved, configuration total length + U16_TO_U8S_LE(0x0008), U16_TO_U8S_LE(MS_OS_20_SUBSET_HEADER_CONFIGURATION), 0, 0, U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A), + + // Function Subset header: length, type, first interface, reserved, subset length + U16_TO_U8S_LE(0x0008), U16_TO_U8S_LE(MS_OS_20_SUBSET_HEADER_FUNCTION), ITF_NUM_VENDOR, 0, U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A - 0x08), + + // MS OS 2.0 Compatible ID descriptor: length, type, compatible ID, sub compatible ID + U16_TO_U8S_LE(0x0014), U16_TO_U8S_LE(MS_OS_20_FEATURE_COMPATBLE_ID), 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // sub-compatible + + // MS OS 2.0 Registry property descriptor: length, type + U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A - 0x08 - 0x08 - 0x14), U16_TO_U8S_LE(MS_OS_20_FEATURE_REG_PROPERTY), + U16_TO_U8S_LE(0x0007), U16_TO_U8S_LE(0x002A), // wPropertyDataType, wPropertyNameLength and PropertyName "DeviceInterfaceGUIDs\0" in UTF-16 + 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, + 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, 'U', 0x00, 'I', 0x00, 'D', 0x00, 's', 0x00, 0x00, 0x00, + U16_TO_U8S_LE(0x0050), // wPropertyDataLength + // bPropertyData: “{975F44D9-0D08-43FD-8B3E-127CA8AFFF9D}”. + '{', 0x00, '9', 0x00, '7', 0x00, '5', 0x00, 'F', 0x00, '4', 0x00, '4', 0x00, 'D', 0x00, '9', 0x00, '-', 0x00, + '0', 0x00, 'D', 0x00, '0', 0x00, '8', 0x00, '-', 0x00, '4', 0x00, '3', 0x00, 'F', 0x00, 'D', 0x00, '-', 0x00, + '8', 0x00, 'B', 0x00, '3', 0x00, 'E', 0x00, '-', 0x00, '1', 0x00, '2', 0x00, '7', 0x00, 'C', 0x00, 'A', 0x00, + '8', 0x00, 'A', 0x00, 'F', 0x00, 'F', 0x00, 'F', 0x00, '9', 0x00, 'D', 0x00, '}', 0x00, 0x00, 0x00, 0x00, 0x00}; + +TU_VERIFY_STATIC(sizeof(desc_ms_os_20) == MS_OS_20_DESC_LEN, "Incorrect size"); + +//--------------------------------------------------------------------+ +// String Descriptors +//--------------------------------------------------------------------+ + +// String Descriptor Index +enum { + STRID_LANGID = 0, + STRID_MANUFACTURER, + STRID_PRODUCT, + STRID_SERIAL, +}; + +// array of pointer to string descriptors +char const *string_desc_arr[] = + { + (const char[]){0x09, 0x04}, // 0: is supported language is English (0x0409) + "Heiso", // 1: Manufacturer + "Macrolev", // 2: Product + "345678", // 3: Serials will use unique ID if possible + "WebUSB Interface", // 5: Interface 2 String + "Keyboard Interface", // 6: Interface 3 String +}; + +static uint16_t _desc_str[32 + 1]; + +// Invoked when received GET STRING DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { + (void)langid; + size_t chr_count; + + if (index == 0) { + memcpy(&_desc_str[1], string_desc_arr[0], 2); + chr_count = 1; + } else { + // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. + // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors + + if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) + return NULL; + + const char *str = string_desc_arr[index]; + + // Cap at max char + chr_count = strlen(str); + if (chr_count > 31) + chr_count = 31; + + // Convert ASCII string into UTF-16 + for (uint8_t i = 0; i < chr_count; i++) { + _desc_str[1 + i] = str[i]; + } + } + + switch (index) { + case STRID_LANGID: + memcpy(&_desc_str[1], string_desc_arr[0], 2); + chr_count = 1; + break; + + case STRID_SERIAL: + chr_count = 10; + break; + + default: + // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. + // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors + + if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) + return NULL; + + const char *str = string_desc_arr[index]; + + // Cap at max char + chr_count = strlen(str); + size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type + if (chr_count > max_count) + chr_count = max_count; + + // Convert ASCII string into UTF-16 + for (size_t i = 0; i < chr_count; i++) { + _desc_str[1 + i] = str[i]; + } + break; + } + + // first byte is length (including header), second byte is string type + _desc_str[0] = (uint16_t)((TUSB_DESC_STRING << 8) | (2 * chr_count + 2)); + + return _desc_str; +} diff --git a/firmware/esp32-s3/main/usb_descriptors.h b/firmware/esp32-s3/main/usb_descriptors.h new file mode 100644 index 0000000..bd4536f --- /dev/null +++ b/firmware/esp32-s3/main/usb_descriptors.h @@ -0,0 +1,44 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef USB_DESCRIPTORS_H_ +#define USB_DESCRIPTORS_H_ + +enum { + REPORT_ID_KEYBOARD = 1, + REPORT_ID_CONSUMER_CONTROL, +}; + +enum { + VENDOR_REQUEST_WEBUSB = 1, + VENDOR_REQUEST_MICROSOFT = 2 +}; + +enum { + ITF_NUM_KEYBOARD = 0, + ITF_NUM_VENDOR, + ITF_NUM_TOTAL +}; + +#endif /* USB_DESCRIPTORS_H_ */ diff --git a/firmware/esp32-s3/sdkconfig b/firmware/esp32-s3/sdkconfig new file mode 100644 index 0000000..2667e7a --- /dev/null +++ b/firmware/esp32-s3/sdkconfig @@ -0,0 +1,2214 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) 5.3.2 Project Configuration +# +CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000 +CONFIG_SOC_MPU_REGIONS_MAX_NUM=8 +CONFIG_SOC_ADC_SUPPORTED=y +CONFIG_SOC_UART_SUPPORTED=y +CONFIG_SOC_PCNT_SUPPORTED=y +CONFIG_SOC_PHY_SUPPORTED=y +CONFIG_SOC_WIFI_SUPPORTED=y +CONFIG_SOC_TWAI_SUPPORTED=y +CONFIG_SOC_GDMA_SUPPORTED=y +CONFIG_SOC_AHB_GDMA_SUPPORTED=y +CONFIG_SOC_GPTIMER_SUPPORTED=y +CONFIG_SOC_LCDCAM_SUPPORTED=y +CONFIG_SOC_LCDCAM_I80_LCD_SUPPORTED=y +CONFIG_SOC_LCDCAM_RGB_LCD_SUPPORTED=y +CONFIG_SOC_MCPWM_SUPPORTED=y +CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y +CONFIG_SOC_CACHE_SUPPORT_WRAP=y +CONFIG_SOC_ULP_SUPPORTED=y +CONFIG_SOC_ULP_FSM_SUPPORTED=y +CONFIG_SOC_RISCV_COPROC_SUPPORTED=y +CONFIG_SOC_BT_SUPPORTED=y +CONFIG_SOC_USB_OTG_SUPPORTED=y +CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y +CONFIG_SOC_CCOMP_TIMER_SUPPORTED=y +CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y +CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y +CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y +CONFIG_SOC_EFUSE_SUPPORTED=y +CONFIG_SOC_SDMMC_HOST_SUPPORTED=y +CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y +CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED=y +CONFIG_SOC_RTC_MEM_SUPPORTED=y +CONFIG_SOC_PSRAM_DMA_CAPABLE=y +CONFIG_SOC_XT_WDT_SUPPORTED=y +CONFIG_SOC_I2S_SUPPORTED=y +CONFIG_SOC_RMT_SUPPORTED=y +CONFIG_SOC_SDM_SUPPORTED=y +CONFIG_SOC_GPSPI_SUPPORTED=y +CONFIG_SOC_LEDC_SUPPORTED=y +CONFIG_SOC_I2C_SUPPORTED=y +CONFIG_SOC_SYSTIMER_SUPPORTED=y +CONFIG_SOC_SUPPORT_COEXISTENCE=y +CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y +CONFIG_SOC_AES_SUPPORTED=y +CONFIG_SOC_MPI_SUPPORTED=y +CONFIG_SOC_SHA_SUPPORTED=y +CONFIG_SOC_HMAC_SUPPORTED=y +CONFIG_SOC_DIG_SIGN_SUPPORTED=y +CONFIG_SOC_FLASH_ENC_SUPPORTED=y +CONFIG_SOC_SECURE_BOOT_SUPPORTED=y +CONFIG_SOC_MEMPROT_SUPPORTED=y +CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y +CONFIG_SOC_BOD_SUPPORTED=y +CONFIG_SOC_CLK_TREE_SUPPORTED=y +CONFIG_SOC_MPU_SUPPORTED=y +CONFIG_SOC_WDT_SUPPORTED=y +CONFIG_SOC_SPI_FLASH_SUPPORTED=y +CONFIG_SOC_RNG_SUPPORTED=y +CONFIG_SOC_LIGHT_SLEEP_SUPPORTED=y +CONFIG_SOC_DEEP_SLEEP_SUPPORTED=y +CONFIG_SOC_LP_PERIPH_SHARE_INTERRUPT=y +CONFIG_SOC_PM_SUPPORTED=y +CONFIG_SOC_XTAL_SUPPORT_40M=y +CONFIG_SOC_APPCPU_HAS_CLOCK_GATING_BUG=y +CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_ARBITER_SUPPORTED=y +CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y +CONFIG_SOC_ADC_MONITOR_SUPPORTED=y +CONFIG_SOC_ADC_DMA_SUPPORTED=y +CONFIG_SOC_ADC_PERIPH_NUM=2 +CONFIG_SOC_ADC_MAX_CHANNEL_NUM=10 +CONFIG_SOC_ADC_ATTEN_NUM=4 +CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=2 +CONFIG_SOC_ADC_PATT_LEN_MAX=24 +CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4 +CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4 +CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2 +CONFIG_SOC_ADC_DIGI_MONITOR_NUM=2 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611 +CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y +CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y +CONFIG_SOC_ADC_SHARED_POWER=y +CONFIG_SOC_APB_BACKUP_DMA=y +CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y +CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED=y +CONFIG_SOC_CACHE_FREEZE_SUPPORTED=y +CONFIG_SOC_CPU_CORES_NUM=2 +CONFIG_SOC_CPU_INTR_NUM=32 +CONFIG_SOC_CPU_HAS_FPU=y +CONFIG_SOC_HP_CPU_HAS_MULTIPLE_CORES=y +CONFIG_SOC_CPU_BREAKPOINTS_NUM=2 +CONFIG_SOC_CPU_WATCHPOINTS_NUM=2 +CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE=64 +CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=4096 +CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16 +CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100 +CONFIG_SOC_AHB_GDMA_VERSION=1 +CONFIG_SOC_GDMA_NUM_GROUPS_MAX=1 +CONFIG_SOC_GDMA_PAIRS_PER_GROUP=5 +CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX=5 +CONFIG_SOC_AHB_GDMA_SUPPORT_PSRAM=y +CONFIG_SOC_GPIO_PORT=1 +CONFIG_SOC_GPIO_PIN_COUNT=49 +CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y +CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y +CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT=y +CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y +CONFIG_SOC_GPIO_VALID_GPIO_MASK=0x1FFFFFFFFFFFF +CONFIG_SOC_GPIO_IN_RANGE_MAX=48 +CONFIG_SOC_GPIO_OUT_RANGE_MAX=48 +CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x0001FFFFFC000000 +CONFIG_SOC_GPIO_CLOCKOUT_BY_IO_MUX=y +CONFIG_SOC_GPIO_CLOCKOUT_CHANNEL_NUM=3 +CONFIG_SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP=y +CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_GPIO_OUT_AUTO_ENABLE=y +CONFIG_SOC_I2C_NUM=2 +CONFIG_SOC_HP_I2C_NUM=2 +CONFIG_SOC_I2C_FIFO_LEN=32 +CONFIG_SOC_I2C_CMD_REG_NUM=8 +CONFIG_SOC_I2C_SUPPORT_SLAVE=y +CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y +CONFIG_SOC_I2C_SUPPORT_XTAL=y +CONFIG_SOC_I2C_SUPPORT_RTC=y +CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR=y +CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST=y +CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS=y +CONFIG_SOC_I2S_NUM=2 +CONFIG_SOC_I2S_HW_VERSION_2=y +CONFIG_SOC_I2S_SUPPORTS_XTAL=y +CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y +CONFIG_SOC_I2S_SUPPORTS_PCM=y +CONFIG_SOC_I2S_SUPPORTS_PDM=y +CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y +CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2 +CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y +CONFIG_SOC_I2S_PDM_MAX_RX_LINES=4 +CONFIG_SOC_I2S_SUPPORTS_TDM=y +CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y +CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y +CONFIG_SOC_LEDC_CHANNEL_NUM=8 +CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14 +CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y +CONFIG_SOC_MCPWM_GROUPS=2 +CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3 +CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3 +CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3 +CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y +CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3 +CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3 +CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE=y +CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1 +CONFIG_SOC_MMU_PERIPH_NUM=1 +CONFIG_SOC_PCNT_GROUPS=1 +CONFIG_SOC_PCNT_UNITS_PER_GROUP=4 +CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2 +CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2 +CONFIG_SOC_RMT_GROUPS=1 +CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=4 +CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=4 +CONFIG_SOC_RMT_CHANNELS_PER_GROUP=8 +CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48 +CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y +CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y +CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y +CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y +CONFIG_SOC_RMT_SUPPORT_XTAL=y +CONFIG_SOC_RMT_SUPPORT_RC_FAST=y +CONFIG_SOC_RMT_SUPPORT_APB=y +CONFIG_SOC_RMT_SUPPORT_DMA=y +CONFIG_SOC_LCD_I80_SUPPORTED=y +CONFIG_SOC_LCD_RGB_SUPPORTED=y +CONFIG_SOC_LCD_I80_BUSES=1 +CONFIG_SOC_LCD_RGB_PANELS=1 +CONFIG_SOC_LCD_I80_BUS_WIDTH=16 +CONFIG_SOC_LCD_RGB_DATA_WIDTH=16 +CONFIG_SOC_LCD_SUPPORT_RGB_YUV_CONV=y +CONFIG_SOC_LCDCAM_I80_NUM_BUSES=1 +CONFIG_SOC_LCDCAM_I80_BUS_WIDTH=16 +CONFIG_SOC_LCDCAM_RGB_NUM_PANELS=1 +CONFIG_SOC_LCDCAM_RGB_DATA_WIDTH=16 +CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128 +CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=549 +CONFIG_SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH=128 +CONFIG_SOC_RTCIO_PIN_COUNT=22 +CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y +CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y +CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y +CONFIG_SOC_SDM_GROUPS=y +CONFIG_SOC_SDM_CHANNELS_PER_GROUP=8 +CONFIG_SOC_SDM_CLK_SUPPORT_APB=y +CONFIG_SOC_SPI_PERIPH_NUM=3 +CONFIG_SOC_SPI_MAX_CS_NUM=6 +CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64 +CONFIG_SOC_SPI_SUPPORT_DDRCLK=y +CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y +CONFIG_SOC_SPI_SUPPORT_CD_SIG=y +CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y +CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y +CONFIG_SOC_SPI_SUPPORT_CLK_APB=y +CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y +CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y +CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y +CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16 +CONFIG_SOC_SPI_SUPPORT_OCT=y +CONFIG_SOC_SPI_SCT_SUPPORTED=y +CONFIG_SOC_SPI_SCT_REG_NUM=14 +CONFIG_SOC_SPI_SCT_BUFFER_NUM_MAX=y +CONFIG_SOC_SPI_SCT_CONF_BITLEN_MAX=0x3FFFA +CONFIG_SOC_MEMSPI_SRC_FREQ_120M=y +CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y +CONFIG_SOC_SPIRAM_SUPPORTED=y +CONFIG_SOC_SPIRAM_XIP_SUPPORTED=y +CONFIG_SOC_SYSTIMER_COUNTER_NUM=2 +CONFIG_SOC_SYSTIMER_ALARM_NUM=3 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20 +CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y +CONFIG_SOC_SYSTIMER_INT_LEVEL=y +CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y +CONFIG_SOC_TIMER_GROUPS=2 +CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=2 +CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54 +CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y +CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y +CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=4 +CONFIG_SOC_TOUCH_SENSOR_VERSION=2 +CONFIG_SOC_TOUCH_SENSOR_NUM=15 +CONFIG_SOC_TOUCH_SUPPORT_SLEEP_WAKEUP=y +CONFIG_SOC_TOUCH_SUPPORT_WATERPROOF=y +CONFIG_SOC_TOUCH_SUPPORT_PROX_SENSING=y +CONFIG_SOC_TOUCH_PROXIMITY_CHANNEL_NUM=3 +CONFIG_SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED=y +CONFIG_SOC_TOUCH_SAMPLE_CFG_NUM=1 +CONFIG_SOC_TWAI_CONTROLLER_NUM=1 +CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y +CONFIG_SOC_TWAI_BRP_MIN=2 +CONFIG_SOC_TWAI_BRP_MAX=16384 +CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y +CONFIG_SOC_UART_NUM=3 +CONFIG_SOC_UART_HP_NUM=3 +CONFIG_SOC_UART_FIFO_LEN=128 +CONFIG_SOC_UART_BITRATE_MAX=5000000 +CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y +CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y +CONFIG_SOC_UART_SUPPORT_APB_CLK=y +CONFIG_SOC_UART_SUPPORT_RTC_CLK=y +CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y +CONFIG_SOC_USB_OTG_PERIPH_NUM=1 +CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968 +CONFIG_SOC_SHA_SUPPORT_DMA=y +CONFIG_SOC_SHA_SUPPORT_RESUME=y +CONFIG_SOC_SHA_GDMA=y +CONFIG_SOC_SHA_SUPPORT_SHA1=y +CONFIG_SOC_SHA_SUPPORT_SHA224=y +CONFIG_SOC_SHA_SUPPORT_SHA256=y +CONFIG_SOC_SHA_SUPPORT_SHA384=y +CONFIG_SOC_SHA_SUPPORT_SHA512=y +CONFIG_SOC_SHA_SUPPORT_SHA512_224=y +CONFIG_SOC_SHA_SUPPORT_SHA512_256=y +CONFIG_SOC_SHA_SUPPORT_SHA512_T=y +CONFIG_SOC_MPI_MEM_BLOCKS_NUM=4 +CONFIG_SOC_MPI_OPERATIONS_NUM=3 +CONFIG_SOC_RSA_MAX_BIT_LEN=4096 +CONFIG_SOC_AES_SUPPORT_DMA=y +CONFIG_SOC_AES_GDMA=y +CONFIG_SOC_AES_SUPPORT_AES_128=y +CONFIG_SOC_AES_SUPPORT_AES_256=y +CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_CPU_PD=y +CONFIG_SOC_PM_SUPPORT_TAGMEM_PD=y +CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y +CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y +CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y +CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y +CONFIG_SOC_PM_SUPPORT_MODEM_PD=y +CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED=y +CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY=y +CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL=y +CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA=y +CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y +CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y +CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y +CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y +CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y +CONFIG_SOC_EFUSE_DIS_DOWNLOAD_DCACHE=y +CONFIG_SOC_EFUSE_HARD_DIS_JTAG=y +CONFIG_SOC_EFUSE_DIS_USB_JTAG=y +CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y +CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y +CONFIG_SOC_EFUSE_DIS_ICACHE=y +CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y +CONFIG_SOC_SECURE_BOOT_V2_RSA=y +CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3 +CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y +CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y +CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=64 +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_256=y +CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16 +CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=256 +CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21 +CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192 +CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12 +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y +CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_OPI_MODE=y +CONFIG_SOC_SPI_MEM_SUPPORT_TIMING_TUNING=y +CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y +CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y +CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY=y +CONFIG_SOC_MEMSPI_CORE_CLK_SHARED_WITH_PSRAM=y +CONFIG_SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP=y +CONFIG_SOC_COEX_HW_PTI=y +CONFIG_SOC_EXTERNAL_COEX_LEADER_TX_LINE=y +CONFIG_SOC_SDMMC_USE_GPIO_MATRIX=y +CONFIG_SOC_SDMMC_NUM_SLOTS=2 +CONFIG_SOC_SDMMC_SUPPORT_XTAL_CLOCK=y +CONFIG_SOC_SDMMC_DELAY_PHASE_NUM=4 +CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y +CONFIG_SOC_WIFI_HW_TSF=y +CONFIG_SOC_WIFI_FTM_SUPPORT=y +CONFIG_SOC_WIFI_GCMP_SUPPORT=y +CONFIG_SOC_WIFI_WAPI_SUPPORT=y +CONFIG_SOC_WIFI_CSI_SUPPORT=y +CONFIG_SOC_WIFI_MESH_SUPPORT=y +CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y +CONFIG_SOC_WIFI_PHY_NEEDS_USB_WORKAROUND=y +CONFIG_SOC_BLE_SUPPORTED=y +CONFIG_SOC_BLE_MESH_SUPPORTED=y +CONFIG_SOC_BLE_50_SUPPORTED=y +CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y +CONFIG_SOC_BLUFI_SUPPORTED=y +CONFIG_SOC_ULP_HAS_ADC=y +CONFIG_SOC_PHY_COMBO_MODULE=y +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TOOLCHAIN="gcc" +CONFIG_IDF_TARGET_ARCH_XTENSA=y +CONFIG_IDF_TARGET_ARCH="xtensa" +CONFIG_IDF_TARGET="esp32s3" +CONFIG_IDF_INIT_VERSION="5.3.2" +CONFIG_IDF_TARGET_ESP32S3=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0009 + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# CONFIG_APP_REPRODUCIBLE_BUILD is not set +# CONFIG_APP_NO_BLOBS is not set +# end of Build type + +# +# Bootloader config +# + +# +# Bootloader manager +# +CONFIG_BOOTLOADER_COMPILE_TIME_DATE=y +CONFIG_BOOTLOADER_PROJECT_VER=1 +# end of Bootloader manager + +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0 +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set +CONFIG_BOOTLOADER_LOG_LEVEL=3 + +# +# Serial Flash Configurations +# +# CONFIG_BOOTLOADER_FLASH_DC_AWARE is not set +CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y +# end of Serial Flash Configurations + +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +# end of Bootloader config + +# +# Security features +# +CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y +CONFIG_SECURE_BOOT_V2_PREFERRED=y +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT is not set +# CONFIG_SECURE_FLASH_ENC_ENABLED is not set +CONFIG_SECURE_ROM_DL_MODE_ENABLED=y +# end of Security features + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=9 +# end of Application manager + +CONFIG_ESP_ROM_HAS_CRC_LE=y +CONFIG_ESP_ROM_HAS_CRC_BE=y +CONFIG_ESP_ROM_HAS_MZ_CRC32=y +CONFIG_ESP_ROM_HAS_JPEG_DECODE=y +CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y +CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y +CONFIG_ESP_ROM_USB_OTG_NUM=3 +CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=4 +CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG=y +CONFIG_ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV=y +CONFIG_ESP_ROM_GET_CLK_FREQ=y +CONFIG_ESP_ROM_HAS_HAL_WDT=y +CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y +CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y +CONFIG_ESP_ROM_HAS_SPI_FLASH=y +CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y +CONFIG_ESP_ROM_HAS_NEWLIB=y +CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y +CONFIG_ESP_ROM_HAS_NEWLIB_32BIT_TIME=y +CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y +CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y +CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG=y +CONFIG_ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG=y +CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG=y +CONFIG_ESP_ROM_HAS_SW_FLOAT=y +CONFIG_ESP_ROM_HAS_VERSION=y +CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB=y + +# +# Boot ROM Behavior +# +CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y +# CONFIG_BOOT_ROM_LOG_ALWAYS_OFF is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW is not set +# end of Boot ROM Behavior + +# +# Serial flasher config +# +# CONFIG_ESPTOOLPY_NO_STUB is not set +# CONFIG_ESPTOOLPY_OCT_FLASH is not set +CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT=y +# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y +CONFIG_ESPTOOLPY_FLASHMODE="dio" +# CONFIG_ESPTOOLPY_FLASHFREQ_120M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_80M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y +CONFIG_ESPTOOLPY_FLASHFREQ="80m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_32MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="2MB" +# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 +# end of Serial flasher config + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP=y +# CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +# CONFIG_PARTITION_TABLE_CUSTOM is not set +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Compiler options +# +CONFIG_COMPILER_OPTIMIZATION_DEBUG=y +# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set +# CONFIG_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_COMPILER_OPTIMIZATION_NONE is not set +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set +CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set +CONFIG_COMPILER_HIDE_PATHS_MACROS=y +# CONFIG_COMPILER_CXX_EXCEPTIONS is not set +# CONFIG_COMPILER_CXX_RTTI is not set +CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set +# CONFIG_COMPILER_DISABLE_GCC13_WARNINGS is not set +# CONFIG_COMPILER_DUMP_RTL_FILES is not set +CONFIG_COMPILER_RT_LIB_GCCLIB=y +CONFIG_COMPILER_RT_LIB_NAME="gcc" +# CONFIG_COMPILER_ORPHAN_SECTIONS_WARNING is not set +CONFIG_COMPILER_ORPHAN_SECTIONS_PLACE=y +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_JTAG is not set +CONFIG_APPTRACE_DEST_NONE=y +# CONFIG_APPTRACE_DEST_UART1 is not set +# CONFIG_APPTRACE_DEST_UART2 is not set +# CONFIG_APPTRACE_DEST_USB_CDC is not set +CONFIG_APPTRACE_DEST_UART_NONE=y +CONFIG_APPTRACE_UART_TASK_PRIO=1 +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +# +# Bluetooth +# +# CONFIG_BT_ENABLED is not set +CONFIG_BT_ALARM_MAX_NUM=50 +# end of Bluetooth + +# +# Console Library +# +# CONFIG_CONSOLE_SORTED_HELP is not set +# end of Console Library + +# +# Driver Configurations +# + +# +# TWAI Configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y +# end of TWAI Configuration + +# +# Legacy ADC Driver Configuration +# +# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set + +# +# Legacy ADC Calibration Configuration +# +# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy ADC Calibration Configuration +# end of Legacy ADC Driver Configuration + +# +# Legacy MCPWM Driver Configurations +# +# CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy MCPWM Driver Configurations + +# +# Legacy Timer Group Driver Configurations +# +# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy Timer Group Driver Configurations + +# +# Legacy RMT Driver Configurations +# +# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy RMT Driver Configurations + +# +# Legacy I2S Driver Configurations +# +# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy I2S Driver Configurations + +# +# Legacy PCNT Driver Configurations +# +# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy PCNT Driver Configurations + +# +# Legacy SDM Driver Configurations +# +# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy SDM Driver Configurations + +# +# Legacy Temperature Sensor Driver Configurations +# +# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy Temperature Sensor Driver Configurations +# end of Driver Configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +CONFIG_EFUSE_MAX_BLK_LEN=256 +# end of eFuse Bit Manager + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y +# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set +# CONFIG_ESP_TLS_SERVER_SESSION_TICKETS is not set +# CONFIG_ESP_TLS_SERVER_CERT_SELECT_HOOK is not set +# CONFIG_ESP_TLS_SERVER_MIN_AUTH_MODE_OPTIONAL is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# CONFIG_ESP_TLS_INSECURE is not set +# end of ESP-TLS + +# +# ADC and ADC Calibration +# +# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set +# CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set +# CONFIG_ADC_ENABLE_DEBUG_LOG is not set +# end of ADC and ADC Calibration + +# +# Wireless Coexistence +# +CONFIG_ESP_COEX_ENABLED=y +# CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set +# CONFIG_ESP_COEX_GPIO_DEBUG is not set +# end of Wireless Coexistence + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +# end of Common ESP-related + +# +# ESP-Driver:GPIO Configurations +# +# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set +# end of ESP-Driver:GPIO Configurations + +# +# ESP-Driver:GPTimer Configurations +# +CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM=y +# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set +# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:GPTimer Configurations + +# +# ESP-Driver:I2C Configurations +# +# CONFIG_I2C_ISR_IRAM_SAFE is not set +# CONFIG_I2C_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:I2C Configurations + +# +# ESP-Driver:I2S Configurations +# +# CONFIG_I2S_ISR_IRAM_SAFE is not set +# CONFIG_I2S_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:I2S Configurations + +# +# ESP-Driver:LEDC Configurations +# +# CONFIG_LEDC_CTRL_FUNC_IN_IRAM is not set +# end of ESP-Driver:LEDC Configurations + +# +# ESP-Driver:MCPWM Configurations +# +# CONFIG_MCPWM_ISR_IRAM_SAFE is not set +# CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:MCPWM Configurations + +# +# ESP-Driver:PCNT Configurations +# +# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_PCNT_ISR_IRAM_SAFE is not set +# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:PCNT Configurations + +# +# ESP-Driver:RMT Configurations +# +# CONFIG_RMT_ISR_IRAM_SAFE is not set +# CONFIG_RMT_RECV_FUNC_IN_IRAM is not set +# CONFIG_RMT_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:RMT Configurations + +# +# ESP-Driver:Sigma Delta Modulator Configurations +# +# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_SDM_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:Sigma Delta Modulator Configurations + +# +# ESP-Driver:SPI Configurations +# +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# end of ESP-Driver:SPI Configurations + +# +# ESP-Driver:Touch Sensor Configurations +# +# CONFIG_TOUCH_CTRL_FUNC_IN_IRAM is not set +# CONFIG_TOUCH_ISR_IRAM_SAFE is not set +# CONFIG_TOUCH_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:Touch Sensor Configurations + +# +# ESP-Driver:Temperature Sensor Configurations +# +# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:Temperature Sensor Configurations + +# +# ESP-Driver:UART Configurations +# +# CONFIG_UART_ISR_IN_IRAM is not set +# end of ESP-Driver:UART Configurations + +# +# ESP-Driver:USB Serial/JTAG Configuration +# +CONFIG_USJ_ENABLE_USB_SERIAL_JTAG=y +# end of ESP-Driver:USB Serial/JTAG Configuration + +# +# Ethernet +# +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_SPI_ETHERNET=y +# CONFIG_ETH_SPI_ETHERNET_DM9051 is not set +# CONFIG_ETH_SPI_ETHERNET_W5500 is not set +# CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set +# CONFIG_ETH_USE_OPENETH is not set +# CONFIG_ETH_TRANSMIT_MUTEX is not set +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y +# end of Event Loop Library + +# +# GDB Stub +# +CONFIG_ESP_GDBSTUB_ENABLED=y +# CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set +CONFIG_ESP_GDBSTUB_SUPPORT_TASKS=y +CONFIG_ESP_GDBSTUB_MAX_TASKS=32 +# end of GDB Stub + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +# CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH is not set +# CONFIG_ESP_HTTP_CLIENT_ENABLE_CUSTOM_TRANSPORT is not set +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set +# CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set +# end of ESP HTTPS server + +# +# Hardware Settings +# + +# +# Chip revision +# +CONFIG_ESP32S3_REV_MIN_0=y +# CONFIG_ESP32S3_REV_MIN_1 is not set +# CONFIG_ESP32S3_REV_MIN_2 is not set +CONFIG_ESP32S3_REV_MIN_FULL=0 +CONFIG_ESP_REV_MIN_FULL=0 + +# +# Maximum Supported ESP32-S3 Revision (Rev v0.99) +# +CONFIG_ESP32S3_REV_MAX_FULL=99 +CONFIG_ESP_REV_MAX_FULL=99 +CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL=0 +CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL=199 + +# +# Maximum Supported ESP32-S3 eFuse Block Revision (eFuse Block Rev v1.99) +# +# end of Chip revision + +# +# MAC Config +# +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y +CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y +CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES=4 +# CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO is not set +CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR=y +CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES=4 +# CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC is not set +# end of MAC Config + +# +# Sleep Config +# +# CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set +CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y +CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU=y +CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y +CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=y +CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY=2000 +# CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION is not set +# CONFIG_ESP_SLEEP_DEBUG is not set +CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS=y +# end of Sleep Config + +# +# RTC Clock Config +# +CONFIG_RTC_CLK_SRC_INT_RC=y +# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_RTC_CLK_CAL_CYCLES=1024 +# end of RTC Clock Config + +# +# Peripheral Control +# +CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y +# end of Peripheral Control + +# +# GDMA Configurations +# +CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y +# CONFIG_GDMA_ISR_IRAM_SAFE is not set +# CONFIG_GDMA_ENABLE_DEBUG_LOG is not set +# end of GDMA Configurations + +# +# Main XTAL Config +# +CONFIG_XTAL_FREQ_40=y +CONFIG_XTAL_FREQ=40 +# end of Main XTAL Config + +CONFIG_ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM=y +# end of Hardware Settings + +# +# LCD and Touch Panel +# + +# +# LCD Touch Drivers are maintained in the IDF Component Registry +# + +# +# LCD Peripheral Configuration +# +# CONFIG_LCD_ENABLE_DEBUG_LOG is not set +# CONFIG_LCD_RGB_ISR_IRAM_SAFE is not set +# CONFIG_LCD_RGB_RESTART_IN_VSYNC is not set +# end of LCD Peripheral Configuration +# end of LCD and Touch Panel + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y +# CONFIG_ESP_NETIF_RECEIVE_REPORT_ERRORS is not set +# CONFIG_ESP_NETIF_L2_TAP is not set +# CONFIG_ESP_NETIF_BRIDGE_EN is not set +# CONFIG_ESP_NETIF_SET_DNS_PER_DEFAULT_NETIF is not set +# end of ESP NETIF Adapter + +# +# Partition API Configuration +# +# end of Partition API Configuration + +# +# PHY +# +CONFIG_ESP_PHY_ENABLED=y +CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP_PHY_MAX_TX_POWER=20 +# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set +CONFIG_ESP_PHY_ENABLE_USB=y +# CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set +CONFIG_ESP_PHY_RF_CAL_PARTIAL=y +# CONFIG_ESP_PHY_RF_CAL_NONE is not set +# CONFIG_ESP_PHY_RF_CAL_FULL is not set +CONFIG_ESP_PHY_CALIBRATION_MODE=0 +# CONFIG_ESP_PHY_PLL_TRACK_DEBUG is not set +# end of PHY + +# +# Power Management +# +# CONFIG_PM_ENABLE is not set +# CONFIG_PM_SLP_IRAM_OPT is not set +CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y +CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP=y +# end of Power Management + +# +# ESP PSRAM +# +# CONFIG_SPIRAM is not set +# end of ESP PSRAM + +# +# ESP Ringbuf +# +# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set +# end of ESP Ringbuf + +# +# ESP System Settings +# +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160 + +# +# Cache config +# +CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y +# CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE=0x4000 +# CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS=y +CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS=8 +# CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B=y +CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE=32 +# CONFIG_ESP32S3_DATA_CACHE_16KB is not set +CONFIG_ESP32S3_DATA_CACHE_32KB=y +# CONFIG_ESP32S3_DATA_CACHE_64KB is not set +CONFIG_ESP32S3_DATA_CACHE_SIZE=0x8000 +# CONFIG_ESP32S3_DATA_CACHE_4WAYS is not set +CONFIG_ESP32S3_DATA_CACHE_8WAYS=y +CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS=8 +# CONFIG_ESP32S3_DATA_CACHE_LINE_16B is not set +CONFIG_ESP32S3_DATA_CACHE_LINE_32B=y +# CONFIG_ESP32S3_DATA_CACHE_LINE_64B is not set +CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32 +# end of Cache config + +# +# Memory +# +# CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM is not set +# CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE is not set +# end of Memory + +# +# Trace memory +# +# CONFIG_ESP32S3_TRAX is not set +CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0 +# end of Trace memory + +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0 +CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y +CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y + +# +# Memory protection +# +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y +# end of Memory protection + +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y +# CONFIG_ESP_MAIN_TASK_AFFINITY_CPU1 is not set +# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_ESP_MAIN_TASK_AFFINITY=0x0 +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +CONFIG_ESP_CONSOLE_UART_DEFAULT=y +# CONFIG_ESP_CONSOLE_USB_CDC is not set +# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG is not set +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_NONE is not set +# CONFIG_ESP_CONSOLE_SECONDARY_NONE is not set +CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG=y +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED=y +CONFIG_ESP_CONSOLE_UART=y +CONFIG_ESP_CONSOLE_UART_NUM=0 +CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM=0 +CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ESP_INT_WDT=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 +CONFIG_ESP_INT_WDT_CHECK_CPU1=y +CONFIG_ESP_TASK_WDT_EN=y +CONFIG_ESP_TASK_WDT_INIT=y +# CONFIG_ESP_TASK_WDT_PANIC is not set +CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set +# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP_DEBUG_OCDAWARE=y +CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y + +# +# Brownout Detector +# +CONFIG_ESP_BROWNOUT_DET=y +CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_ESP_BROWNOUT_DET_LVL=7 +# end of Brownout Detector + +CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y +CONFIG_ESP_SYSTEM_BBPLL_RECALIB=y +# end of ESP System Settings + +# +# IPC (Inter-Processor Call) +# +CONFIG_ESP_IPC_TASK_STACK_SIZE=1280 +CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y +CONFIG_ESP_IPC_ISR_ENABLE=y +# end of IPC (Inter-Processor Call) + +# +# ESP Timer (High Resolution Timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y +CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y +CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1 +# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set +CONFIG_ESP_TIMER_TASK_AFFINITY=0x0 +CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y +CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y +# CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set +CONFIG_ESP_TIMER_IMPL_SYSTIMER=y +# end of ESP Timer (High Resolution Timer) + +# +# Wi-Fi +# +CONFIG_ESP_WIFI_ENABLED=y +CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP_WIFI_STATIC_TX_BUFFER is not set +CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER=y +CONFIG_ESP_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +CONFIG_ESP_WIFI_STATIC_RX_MGMT_BUFFER=y +# CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUFFER is not set +CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUF=0 +CONFIG_ESP_WIFI_RX_MGMT_BUF_NUM_DEF=5 +# CONFIG_ESP_WIFI_CSI_ENABLED is not set +CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP_WIFI_TX_BA_WIN=6 +CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP_WIFI_RX_BA_WIN=6 +CONFIG_ESP_WIFI_NVS_ENABLED=y +CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_0=y +# CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_1 is not set +CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP_WIFI_IRAM_OPT=y +# CONFIG_ESP_WIFI_EXTRA_IRAM_OPT is not set +CONFIG_ESP_WIFI_RX_IRAM_OPT=y +CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y +CONFIG_ESP_WIFI_ENABLE_SAE_PK=y +CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y +CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y +# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set +CONFIG_ESP_WIFI_SLP_DEFAULT_MIN_ACTIVE_TIME=50 +CONFIG_ESP_WIFI_SLP_DEFAULT_MAX_ACTIVE_TIME=10 +CONFIG_ESP_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME=15 +# CONFIG_ESP_WIFI_FTM_ENABLE is not set +CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE=y +# CONFIG_ESP_WIFI_GCMP_SUPPORT is not set +CONFIG_ESP_WIFI_GMAC_SUPPORT=y +CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y +# CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set +CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7 +CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y +CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y +# CONFIG_ESP_WIFI_WAPI_PSK is not set +# CONFIG_ESP_WIFI_SUITE_B_192 is not set +# CONFIG_ESP_WIFI_11KV_SUPPORT is not set +# CONFIG_ESP_WIFI_MBO_SUPPORT is not set +# CONFIG_ESP_WIFI_DPP_SUPPORT is not set +# CONFIG_ESP_WIFI_11R_SUPPORT is not set +# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set + +# +# WPS Configuration Options +# +# CONFIG_ESP_WIFI_WPS_STRICT is not set +# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set +# end of WPS Configuration Options + +# CONFIG_ESP_WIFI_DEBUG_PRINT is not set +# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set +CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT=y +# CONFIG_ESP_WIFI_ENT_FREE_DYNAMIC_BUFFER is not set +# end of Wi-Fi + +# +# Core dump +# +# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y +# end of Core dump + +# +# FAT Filesystem support +# +CONFIG_FATFS_VOLUME_COUNT=2 +CONFIG_FATFS_LFN_NONE=y +# CONFIG_FATFS_LFN_HEAP is not set +# CONFIG_FATFS_LFN_STACK is not set +# CONFIG_FATFS_SECTOR_512 is not set +CONFIG_FATFS_SECTOR_4096=y +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +# CONFIG_FATFS_USE_FASTSEEK is not set +CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0 +# CONFIG_FATFS_IMMEDIATE_FSYNC is not set +# CONFIG_FATFS_USE_LABEL is not set +CONFIG_FATFS_LINK_LOCK=y +# end of FAT Filesystem support + +# +# FreeRTOS +# + +# +# Kernel +# +# CONFIG_FREERTOS_SMP is not set +# CONFIG_FREERTOS_UNICORE is not set +CONFIG_FREERTOS_HZ=100 +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +# CONFIG_FREERTOS_USE_IDLE_HOOK is not set +# CONFIG_FREERTOS_USE_TICK_HOOK is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set +CONFIG_FREERTOS_TIMER_SERVICE_TASK_NAME="Tmr Svc" +# CONFIG_FREERTOS_TIMER_TASK_AFFINITY_CPU0 is not set +# CONFIG_FREERTOS_TIMER_TASK_AFFINITY_CPU1 is not set +CONFIG_FREERTOS_TIMER_TASK_NO_AFFINITY=y +CONFIG_FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1 +# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set +# CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +# CONFIG_FREERTOS_USE_APPLICATION_TASK_TAG is not set +# end of Kernel + +# +# Port +# +CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y +# CONFIG_FREERTOS_TASK_PRE_DELETION_HOOK is not set +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y +CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y +# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set +CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y +# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +# end of Port + +CONFIG_FREERTOS_PORT=y +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y +CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH=y +CONFIG_FREERTOS_NUMBER_OF_CORES=2 +# end of FreeRTOS + +# +# Hardware Abstraction Layer (HAL) and Low Level (LL) +# +CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y +# CONFIG_HAL_ASSERTION_DISABLE is not set +# CONFIG_HAL_ASSERTION_SILENT is not set +# CONFIG_HAL_ASSERTION_ENABLE is not set +CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2 +CONFIG_HAL_WDT_USE_ROM_IMPL=y +CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y +CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y +# CONFIG_HAL_ECDSA_GEN_SIG_CM is not set +# end of Hardware Abstraction Layer (HAL) and Low Level (LL) + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +# CONFIG_HEAP_POISONING_LIGHT is not set +# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set +CONFIG_HEAP_TRACING_OFF=y +# CONFIG_HEAP_TRACING_STANDALONE is not set +# CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_USE_HOOKS is not set +# CONFIG_HEAP_TASK_TRACKING is not set +# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set +# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set +# end of Heap memory debugging + +# +# Log output +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y +# CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set +# CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set +CONFIG_LOG_MAXIMUM_LEVEL=3 +# CONFIG_LOG_MASTER_LEVEL is not set +CONFIG_LOG_COLORS=y +CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set +# end of Log output + +# +# LWIP +# +CONFIG_LWIP_ENABLE=y +CONFIG_LWIP_LOCAL_HOSTNAME="espressif" +# CONFIG_LWIP_NETIF_API is not set +CONFIG_LWIP_TCPIP_TASK_PRIO=18 +# CONFIG_LWIP_TCPIP_CORE_LOCKING is not set +# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +# CONFIG_LWIP_EXTRA_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_ND6=y +# CONFIG_LWIP_FORCE_ROUTER_FORWARDING is not set +CONFIG_LWIP_MAX_SOCKETS=10 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +# CONFIG_LWIP_SO_LINGER is not set +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +# CONFIG_LWIP_SO_RCVBUF is not set +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP_DEFAULT_TTL=64 +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set +CONFIG_LWIP_IP_REASS_MAX_PBUFS=10 +# CONFIG_LWIP_IP_FORWARD is not set +# CONFIG_LWIP_STATS is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_ESP_MLDV6_REPORT=y +CONFIG_LWIP_MLDV6_TMR_INTERVAL=40 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set +CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCP_OPTIONS_LEN=68 +CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0 +CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1 + +# +# DHCP server +# +CONFIG_LWIP_DHCPS=y +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +CONFIG_LWIP_DHCPS_STATIC_ENTRIES=y +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_IPV4=y +CONFIG_LWIP_IPV6=y +# CONFIG_LWIP_IPV6_AUTOCONFIG is not set +CONFIG_LWIP_IPV6_NUM_ADDRESSES=3 +# CONFIG_LWIP_IPV6_FORWARD is not set +# CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=12 +CONFIG_LWIP_TCP_MSS=1440 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT=20000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5760 +CONFIG_LWIP_TCP_WND_DEFAULT=5760 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 +CONFIG_LWIP_TCP_ACCEPTMBOX_SIZE=6 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +CONFIG_LWIP_TCP_OOSEQ_TIMEOUT=6 +CONFIG_LWIP_TCP_OOSEQ_MAX_PBUFS=4 +# CONFIG_LWIP_TCP_SACK_OUT is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=1500 +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +# +# Checksums +# +# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set +# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set +CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y +# end of Checksums + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF +CONFIG_LWIP_IPV6_ND6_NUM_PREFIXES=5 +CONFIG_LWIP_IPV6_ND6_NUM_ROUTERS=3 +CONFIG_LWIP_IPV6_ND6_NUM_DESTINATIONS=10 +# CONFIG_LWIP_PPP_SUPPORT is not set +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 +# CONFIG_LWIP_SLIP_SUPPORT is not set + +# +# ICMP +# +CONFIG_LWIP_ICMP=y +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_SNTP_MAX_SERVERS=1 +# CONFIG_LWIP_DHCP_GET_NTP_SRV is not set +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +CONFIG_LWIP_SNTP_STARTUP_DELAY=y +CONFIG_LWIP_SNTP_MAXIMUM_STARTUP_DELAY=5000 +# end of SNTP + +# +# DNS +# +CONFIG_LWIP_DNS_MAX_HOST_IP=1 +CONFIG_LWIP_DNS_MAX_SERVERS=3 +# CONFIG_LWIP_FALLBACK_DNS_SERVER_SUPPORT is not set +# CONFIG_LWIP_DNS_SETSERVER_WITH_NETIF is not set +# end of DNS + +CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7 +CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Hooks +# +# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set +CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y +# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y +# CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set +# CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE=y +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM is not set +CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +CONFIG_LWIP_HOOK_DNS_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_DNS_EXT_RESOLVE_CUSTOM is not set +# CONFIG_LWIP_HOOK_IP6_INPUT_NONE is not set +CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT=y +# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set +# end of Hooks + +# CONFIG_LWIP_DEBUG is not set +# end of LWIP + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 +# CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set +# CONFIG_MBEDTLS_DEBUG is not set + +# +# mbedTLS v3.x related +# +# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set +# CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set +# CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set +# CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set +CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y +CONFIG_MBEDTLS_PKCS7_C=y +# end of mbedTLS v3.x related + +# +# Certificate Bundle +# +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set +# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEPRECATED_LIST is not set +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200 +# end of Certificate Bundle + +# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set +CONFIG_MBEDTLS_CMAC_C=y +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_AES_USE_INTERRUPT=y +CONFIG_MBEDTLS_AES_INTERRUPT_LEVEL=0 +CONFIG_MBEDTLS_GCM_SUPPORT_NON_AES_CIPHER=y +CONFIG_MBEDTLS_HARDWARE_MPI=y +# CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set +CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y +CONFIG_MBEDTLS_MPI_INTERRUPT_LEVEL=0 +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_ROM_MD5=y +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set +CONFIG_MBEDTLS_HAVE_TIME=y +# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set +# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set +CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y +CONFIG_MBEDTLS_SHA512_C=y +# CONFIG_MBEDTLS_SHA3_C is not set +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +# CONFIG_MBEDTLS_DES_C is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +# CONFIG_MBEDTLS_XTEA_C is not set +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_NIST_KW_C is not set +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C is not set + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +# CONFIG_MBEDTLS_DHM_C is not set +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +# CONFIG_MBEDTLS_ECJPAKE_C is not set +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +# CONFIG_MBEDTLS_ECP_FIXED_POINT_OPTIM is not set +# CONFIG_MBEDTLS_POLY1305_C is not set +# CONFIG_MBEDTLS_CHACHA20_C is not set +# CONFIG_MBEDTLS_HKDF_C is not set +# CONFIG_MBEDTLS_THREADING_C is not set +CONFIG_MBEDTLS_ERROR_STRINGS=y +CONFIG_MBEDTLS_FS_IO=y +# end of mbedTLS + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +# CONFIG_MQTT_PROTOCOL_5 is not set +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set +# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set +# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y +# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set +# end of Newlib + +# +# NVS +# +# CONFIG_NVS_ENCRYPTION is not set +# CONFIG_NVS_ASSERT_ERROR_CHECK is not set +# CONFIG_NVS_LEGACY_DUP_KEYS_COMPATIBILITY is not set +# end of NVS + +# +# OpenThread +# +# CONFIG_OPENTHREAD_ENABLED is not set + +# +# Thread Operational Dataset +# +CONFIG_OPENTHREAD_NETWORK_NAME="OpenThread-ESP" +CONFIG_OPENTHREAD_MESH_LOCAL_PREFIX="fd00:db8:a0:0::/64" +CONFIG_OPENTHREAD_NETWORK_CHANNEL=15 +CONFIG_OPENTHREAD_NETWORK_PANID=0x1234 +CONFIG_OPENTHREAD_NETWORK_EXTPANID="dead00beef00cafe" +CONFIG_OPENTHREAD_NETWORK_MASTERKEY="00112233445566778899aabbccddeeff" +CONFIG_OPENTHREAD_NETWORK_PSKC="104810e2315100afd6bc9215a6bfac53" +# end of Thread Operational Dataset + +CONFIG_OPENTHREAD_XTAL_ACCURACY=130 +# CONFIG_OPENTHREAD_SPINEL_ONLY is not set +CONFIG_OPENTHREAD_RX_ON_WHEN_IDLE=y + +# +# Thread Address Query Config +# +# end of Thread Address Query Config +# end of OpenThread + +# +# Protocomm +# +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y +# end of Protocomm + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY=y +# CONFIG_PTHREAD_DEFAULT_CORE_0 is not set +# CONFIG_PTHREAD_DEFAULT_CORE_1 is not set +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# MMU Config +# +CONFIG_MMU_PAGE_SIZE_64KB=y +CONFIG_MMU_PAGE_MODE="64KB" +CONFIG_MMU_PAGE_SIZE=0x10000 +# end of MMU Config + +# +# Main Flash configuration +# + +# +# SPI Flash behavior when brownout +# +CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y +CONFIG_SPI_FLASH_BROWNOUT_RESET=y +# end of SPI Flash behavior when brownout + +# +# Optional and Experimental Features (READ DOCS FIRST) +# + +# +# Features here require specific hardware (READ DOCS FIRST!) +# +# CONFIG_SPI_FLASH_HPM_ENA is not set +CONFIG_SPI_FLASH_HPM_AUTO=y +# CONFIG_SPI_FLASH_HPM_DIS is not set +CONFIG_SPI_FLASH_HPM_ON=y +CONFIG_SPI_FLASH_HPM_DC_AUTO=y +# CONFIG_SPI_FLASH_HPM_DC_DISABLE is not set +CONFIG_SPI_FLASH_SUSPEND_QVL_SUPPORTED=y +# CONFIG_SPI_FLASH_AUTO_SUSPEND is not set +CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US=50 +# CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND is not set +# end of Optional and Experimental Features (READ DOCS FIRST) +# end of Main Flash configuration + +# +# SPI Flash driver +# +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +# CONFIG_SPI_FLASH_ROM_IMPL is not set +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 +# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set +# CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED=y +CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_TH_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP=y +# end of Auto-detect flash chips + +CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TCP Transport +# + +# +# Websocket +# +CONFIG_WS_TRANSPORT=y +CONFIG_WS_BUFFER_SIZE=1024 +# CONFIG_WS_DYNAMIC_BUFFER is not set +# end of Websocket +# end of TCP Transport + +# +# Ultra Low Power (ULP) Co-processor +# +# CONFIG_ULP_COPROC_ENABLED is not set + +# +# ULP Debugging Options +# +# end of ULP Debugging Options +# end of Ultra Low Power (ULP) Co-processor + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_64BIT is not set +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# USB-OTG +# +CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=256 +CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED=y +# CONFIG_USB_HOST_HW_BUFFER_BIAS_IN is not set +# CONFIG_USB_HOST_HW_BUFFER_BIAS_PERIODIC_OUT is not set + +# +# Hub Driver Configuration +# + +# +# Root Port configuration +# +CONFIG_USB_HOST_DEBOUNCE_DELAY_MS=250 +CONFIG_USB_HOST_RESET_HOLD_MS=30 +CONFIG_USB_HOST_RESET_RECOVERY_MS=30 +CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS=10 +# end of Root Port configuration + +# CONFIG_USB_HOST_HUBS_SUPPORTED is not set +# end of Hub Driver Configuration + +# CONFIG_USB_HOST_ENABLE_ENUM_FILTER_CALLBACK is not set +CONFIG_USB_OTG_SUPPORTED=y +# end of USB-OTG + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +CONFIG_VFS_SUPPORT_SELECT=y +CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y +# CONFIG_VFS_SELECT_IN_RAM is not set +CONFIG_VFS_SUPPORT_TERMIOS=y +CONFIG_VFS_MAX_COUNT=8 + +# +# Host File System I/O (Semihosting) +# +CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# end of Host File System I/O (Semihosting) +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y +# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set +# end of Wi-Fi Provisioning Manager +# end of Component config + +# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set + +# Deprecated options for backward compatibility +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +# CONFIG_NO_BLOBS is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set +CONFIG_LOG_BOOTLOADER_LEVEL=3 +# CONFIG_APP_ROLLBACK_ENABLE is not set +# CONFIG_FLASH_ENCRYPTION_ENABLED is not set +# CONFIG_FLASHMODE_QIO is not set +# CONFIG_FLASHMODE_QOUT is not set +CONFIG_FLASHMODE_DIO=y +# CONFIG_FLASHMODE_DOUT is not set +CONFIG_MONITOR_BAUD=115200 +CONFIG_OPTIMIZATION_LEVEL_DEBUG=y +CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y +CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y +# CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set +# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set +CONFIG_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_CXX_EXCEPTIONS is not set +CONFIG_STACK_CHECK_NONE=y +# CONFIG_STACK_CHECK_NORM is not set +# CONFIG_STACK_CHECK_STRONG is not set +# CONFIG_STACK_CHECK_ALL is not set +# CONFIG_WARN_WRITE_STRINGS is not set +# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +# CONFIG_EXTERNAL_COEX_ENABLE is not set +# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set +# CONFIG_MCPWM_ISR_IN_IRAM is not set +# CONFIG_EVENT_LOOP_PROFILING is not set +CONFIG_POST_EVENTS_FROM_ISR=y +CONFIG_POST_EVENTS_FROM_IRAM_ISR=y +CONFIG_GDBSTUB_SUPPORT_TASKS=y +CONFIG_GDBSTUB_MAX_TASKS=32 +# CONFIG_OTA_ALLOW_HTTP is not set +# CONFIG_ESP_SYSTEM_PD_FLASH is not set +CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 +# CONFIG_REDUCE_PHY_TX_POWER is not set +# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set +CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y +CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP=y +# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set +# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_80 is not set +CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160=y +# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240 is not set +CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ=160 +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_CONSOLE_UART_DEFAULT=y +# CONFIG_CONSOLE_UART_CUSTOM is not set +# CONFIG_CONSOLE_UART_NONE is not set +# CONFIG_ESP_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART=y +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_INT_WDT_CHECK_CPU1=y +CONFIG_TASK_WDT=y +CONFIG_ESP_TASK_WDT=y +# CONFIG_TASK_WDT_PANIC is not set +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP32S3_DEBUG_OCDAWARE=y +CONFIG_BROWNOUT_DET=y +CONFIG_ESP32S3_BROWNOUT_DET=y +CONFIG_ESP32S3_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_7=y +CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_BROWNOUT_DET_LVL=7 +CONFIG_ESP32S3_BROWNOUT_DET_LVL=7 +CONFIG_IPC_TASK_STACK_SIZE=1280 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP32_WIFI_ENABLED=y +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_WIFI_RX_IRAM_OPT=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y +CONFIG_WPA_MBEDTLS_CRYPTO=y +CONFIG_WPA_MBEDTLS_TLS_CLIENT=y +# CONFIG_WPA_WAPI_PSK is not set +# CONFIG_WPA_SUITE_B_192 is not set +# CONFIG_WPA_11KV_SUPPORT is not set +# CONFIG_WPA_MBO_SUPPORT is not set +# CONFIG_WPA_DPP_SUPPORT is not set +# CONFIG_WPA_11R_SUPPORT is not set +# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set +# CONFIG_WPA_WPS_STRICT is not set +# CONFIG_WPA_DEBUG_PRINT is not set +# CONFIG_WPA_TESTING_OPTIONS is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set +# CONFIG_HAL_ASSERTION_SILIENT is not set +# CONFIG_L2_TO_L3_COPY is not set +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=12 +CONFIG_TCP_MSS=1440 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5760 +CONFIG_TCP_WND_DEFAULT=5760 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +CONFIG_TCP_OVERSIZE_MSS=y +# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_TCP_OVERSIZE_DISABLE is not set +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set +# CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_PPP_SUPPORT is not set +CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_SYSTIMER=y +CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1=y +# CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_SYSTIMER is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_FRC1 is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_ESP32_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0 is not set +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y +CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# End of deprecated options diff --git a/firmware/esp32-s3/sdkconfig.old b/firmware/esp32-s3/sdkconfig.old new file mode 100644 index 0000000..2667e7a --- /dev/null +++ b/firmware/esp32-s3/sdkconfig.old @@ -0,0 +1,2214 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) 5.3.2 Project Configuration +# +CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000 +CONFIG_SOC_MPU_REGIONS_MAX_NUM=8 +CONFIG_SOC_ADC_SUPPORTED=y +CONFIG_SOC_UART_SUPPORTED=y +CONFIG_SOC_PCNT_SUPPORTED=y +CONFIG_SOC_PHY_SUPPORTED=y +CONFIG_SOC_WIFI_SUPPORTED=y +CONFIG_SOC_TWAI_SUPPORTED=y +CONFIG_SOC_GDMA_SUPPORTED=y +CONFIG_SOC_AHB_GDMA_SUPPORTED=y +CONFIG_SOC_GPTIMER_SUPPORTED=y +CONFIG_SOC_LCDCAM_SUPPORTED=y +CONFIG_SOC_LCDCAM_I80_LCD_SUPPORTED=y +CONFIG_SOC_LCDCAM_RGB_LCD_SUPPORTED=y +CONFIG_SOC_MCPWM_SUPPORTED=y +CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y +CONFIG_SOC_CACHE_SUPPORT_WRAP=y +CONFIG_SOC_ULP_SUPPORTED=y +CONFIG_SOC_ULP_FSM_SUPPORTED=y +CONFIG_SOC_RISCV_COPROC_SUPPORTED=y +CONFIG_SOC_BT_SUPPORTED=y +CONFIG_SOC_USB_OTG_SUPPORTED=y +CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y +CONFIG_SOC_CCOMP_TIMER_SUPPORTED=y +CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y +CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y +CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y +CONFIG_SOC_EFUSE_SUPPORTED=y +CONFIG_SOC_SDMMC_HOST_SUPPORTED=y +CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y +CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED=y +CONFIG_SOC_RTC_MEM_SUPPORTED=y +CONFIG_SOC_PSRAM_DMA_CAPABLE=y +CONFIG_SOC_XT_WDT_SUPPORTED=y +CONFIG_SOC_I2S_SUPPORTED=y +CONFIG_SOC_RMT_SUPPORTED=y +CONFIG_SOC_SDM_SUPPORTED=y +CONFIG_SOC_GPSPI_SUPPORTED=y +CONFIG_SOC_LEDC_SUPPORTED=y +CONFIG_SOC_I2C_SUPPORTED=y +CONFIG_SOC_SYSTIMER_SUPPORTED=y +CONFIG_SOC_SUPPORT_COEXISTENCE=y +CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y +CONFIG_SOC_AES_SUPPORTED=y +CONFIG_SOC_MPI_SUPPORTED=y +CONFIG_SOC_SHA_SUPPORTED=y +CONFIG_SOC_HMAC_SUPPORTED=y +CONFIG_SOC_DIG_SIGN_SUPPORTED=y +CONFIG_SOC_FLASH_ENC_SUPPORTED=y +CONFIG_SOC_SECURE_BOOT_SUPPORTED=y +CONFIG_SOC_MEMPROT_SUPPORTED=y +CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y +CONFIG_SOC_BOD_SUPPORTED=y +CONFIG_SOC_CLK_TREE_SUPPORTED=y +CONFIG_SOC_MPU_SUPPORTED=y +CONFIG_SOC_WDT_SUPPORTED=y +CONFIG_SOC_SPI_FLASH_SUPPORTED=y +CONFIG_SOC_RNG_SUPPORTED=y +CONFIG_SOC_LIGHT_SLEEP_SUPPORTED=y +CONFIG_SOC_DEEP_SLEEP_SUPPORTED=y +CONFIG_SOC_LP_PERIPH_SHARE_INTERRUPT=y +CONFIG_SOC_PM_SUPPORTED=y +CONFIG_SOC_XTAL_SUPPORT_40M=y +CONFIG_SOC_APPCPU_HAS_CLOCK_GATING_BUG=y +CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_ARBITER_SUPPORTED=y +CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y +CONFIG_SOC_ADC_MONITOR_SUPPORTED=y +CONFIG_SOC_ADC_DMA_SUPPORTED=y +CONFIG_SOC_ADC_PERIPH_NUM=2 +CONFIG_SOC_ADC_MAX_CHANNEL_NUM=10 +CONFIG_SOC_ADC_ATTEN_NUM=4 +CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=2 +CONFIG_SOC_ADC_PATT_LEN_MAX=24 +CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4 +CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4 +CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2 +CONFIG_SOC_ADC_DIGI_MONITOR_NUM=2 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611 +CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y +CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y +CONFIG_SOC_ADC_SHARED_POWER=y +CONFIG_SOC_APB_BACKUP_DMA=y +CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y +CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED=y +CONFIG_SOC_CACHE_FREEZE_SUPPORTED=y +CONFIG_SOC_CPU_CORES_NUM=2 +CONFIG_SOC_CPU_INTR_NUM=32 +CONFIG_SOC_CPU_HAS_FPU=y +CONFIG_SOC_HP_CPU_HAS_MULTIPLE_CORES=y +CONFIG_SOC_CPU_BREAKPOINTS_NUM=2 +CONFIG_SOC_CPU_WATCHPOINTS_NUM=2 +CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE=64 +CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=4096 +CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16 +CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100 +CONFIG_SOC_AHB_GDMA_VERSION=1 +CONFIG_SOC_GDMA_NUM_GROUPS_MAX=1 +CONFIG_SOC_GDMA_PAIRS_PER_GROUP=5 +CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX=5 +CONFIG_SOC_AHB_GDMA_SUPPORT_PSRAM=y +CONFIG_SOC_GPIO_PORT=1 +CONFIG_SOC_GPIO_PIN_COUNT=49 +CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y +CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y +CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT=y +CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y +CONFIG_SOC_GPIO_VALID_GPIO_MASK=0x1FFFFFFFFFFFF +CONFIG_SOC_GPIO_IN_RANGE_MAX=48 +CONFIG_SOC_GPIO_OUT_RANGE_MAX=48 +CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x0001FFFFFC000000 +CONFIG_SOC_GPIO_CLOCKOUT_BY_IO_MUX=y +CONFIG_SOC_GPIO_CLOCKOUT_CHANNEL_NUM=3 +CONFIG_SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP=y +CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_GPIO_OUT_AUTO_ENABLE=y +CONFIG_SOC_I2C_NUM=2 +CONFIG_SOC_HP_I2C_NUM=2 +CONFIG_SOC_I2C_FIFO_LEN=32 +CONFIG_SOC_I2C_CMD_REG_NUM=8 +CONFIG_SOC_I2C_SUPPORT_SLAVE=y +CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y +CONFIG_SOC_I2C_SUPPORT_XTAL=y +CONFIG_SOC_I2C_SUPPORT_RTC=y +CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR=y +CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST=y +CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS=y +CONFIG_SOC_I2S_NUM=2 +CONFIG_SOC_I2S_HW_VERSION_2=y +CONFIG_SOC_I2S_SUPPORTS_XTAL=y +CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y +CONFIG_SOC_I2S_SUPPORTS_PCM=y +CONFIG_SOC_I2S_SUPPORTS_PDM=y +CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y +CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2 +CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y +CONFIG_SOC_I2S_PDM_MAX_RX_LINES=4 +CONFIG_SOC_I2S_SUPPORTS_TDM=y +CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y +CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y +CONFIG_SOC_LEDC_CHANNEL_NUM=8 +CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14 +CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y +CONFIG_SOC_MCPWM_GROUPS=2 +CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3 +CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3 +CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3 +CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y +CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3 +CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3 +CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE=y +CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1 +CONFIG_SOC_MMU_PERIPH_NUM=1 +CONFIG_SOC_PCNT_GROUPS=1 +CONFIG_SOC_PCNT_UNITS_PER_GROUP=4 +CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2 +CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2 +CONFIG_SOC_RMT_GROUPS=1 +CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=4 +CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=4 +CONFIG_SOC_RMT_CHANNELS_PER_GROUP=8 +CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48 +CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y +CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y +CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y +CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y +CONFIG_SOC_RMT_SUPPORT_XTAL=y +CONFIG_SOC_RMT_SUPPORT_RC_FAST=y +CONFIG_SOC_RMT_SUPPORT_APB=y +CONFIG_SOC_RMT_SUPPORT_DMA=y +CONFIG_SOC_LCD_I80_SUPPORTED=y +CONFIG_SOC_LCD_RGB_SUPPORTED=y +CONFIG_SOC_LCD_I80_BUSES=1 +CONFIG_SOC_LCD_RGB_PANELS=1 +CONFIG_SOC_LCD_I80_BUS_WIDTH=16 +CONFIG_SOC_LCD_RGB_DATA_WIDTH=16 +CONFIG_SOC_LCD_SUPPORT_RGB_YUV_CONV=y +CONFIG_SOC_LCDCAM_I80_NUM_BUSES=1 +CONFIG_SOC_LCDCAM_I80_BUS_WIDTH=16 +CONFIG_SOC_LCDCAM_RGB_NUM_PANELS=1 +CONFIG_SOC_LCDCAM_RGB_DATA_WIDTH=16 +CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128 +CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=549 +CONFIG_SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH=128 +CONFIG_SOC_RTCIO_PIN_COUNT=22 +CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y +CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y +CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y +CONFIG_SOC_SDM_GROUPS=y +CONFIG_SOC_SDM_CHANNELS_PER_GROUP=8 +CONFIG_SOC_SDM_CLK_SUPPORT_APB=y +CONFIG_SOC_SPI_PERIPH_NUM=3 +CONFIG_SOC_SPI_MAX_CS_NUM=6 +CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64 +CONFIG_SOC_SPI_SUPPORT_DDRCLK=y +CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y +CONFIG_SOC_SPI_SUPPORT_CD_SIG=y +CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y +CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y +CONFIG_SOC_SPI_SUPPORT_CLK_APB=y +CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y +CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y +CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y +CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16 +CONFIG_SOC_SPI_SUPPORT_OCT=y +CONFIG_SOC_SPI_SCT_SUPPORTED=y +CONFIG_SOC_SPI_SCT_REG_NUM=14 +CONFIG_SOC_SPI_SCT_BUFFER_NUM_MAX=y +CONFIG_SOC_SPI_SCT_CONF_BITLEN_MAX=0x3FFFA +CONFIG_SOC_MEMSPI_SRC_FREQ_120M=y +CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y +CONFIG_SOC_SPIRAM_SUPPORTED=y +CONFIG_SOC_SPIRAM_XIP_SUPPORTED=y +CONFIG_SOC_SYSTIMER_COUNTER_NUM=2 +CONFIG_SOC_SYSTIMER_ALARM_NUM=3 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20 +CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y +CONFIG_SOC_SYSTIMER_INT_LEVEL=y +CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y +CONFIG_SOC_TIMER_GROUPS=2 +CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=2 +CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54 +CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y +CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y +CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=4 +CONFIG_SOC_TOUCH_SENSOR_VERSION=2 +CONFIG_SOC_TOUCH_SENSOR_NUM=15 +CONFIG_SOC_TOUCH_SUPPORT_SLEEP_WAKEUP=y +CONFIG_SOC_TOUCH_SUPPORT_WATERPROOF=y +CONFIG_SOC_TOUCH_SUPPORT_PROX_SENSING=y +CONFIG_SOC_TOUCH_PROXIMITY_CHANNEL_NUM=3 +CONFIG_SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED=y +CONFIG_SOC_TOUCH_SAMPLE_CFG_NUM=1 +CONFIG_SOC_TWAI_CONTROLLER_NUM=1 +CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y +CONFIG_SOC_TWAI_BRP_MIN=2 +CONFIG_SOC_TWAI_BRP_MAX=16384 +CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y +CONFIG_SOC_UART_NUM=3 +CONFIG_SOC_UART_HP_NUM=3 +CONFIG_SOC_UART_FIFO_LEN=128 +CONFIG_SOC_UART_BITRATE_MAX=5000000 +CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y +CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y +CONFIG_SOC_UART_SUPPORT_APB_CLK=y +CONFIG_SOC_UART_SUPPORT_RTC_CLK=y +CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y +CONFIG_SOC_USB_OTG_PERIPH_NUM=1 +CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968 +CONFIG_SOC_SHA_SUPPORT_DMA=y +CONFIG_SOC_SHA_SUPPORT_RESUME=y +CONFIG_SOC_SHA_GDMA=y +CONFIG_SOC_SHA_SUPPORT_SHA1=y +CONFIG_SOC_SHA_SUPPORT_SHA224=y +CONFIG_SOC_SHA_SUPPORT_SHA256=y +CONFIG_SOC_SHA_SUPPORT_SHA384=y +CONFIG_SOC_SHA_SUPPORT_SHA512=y +CONFIG_SOC_SHA_SUPPORT_SHA512_224=y +CONFIG_SOC_SHA_SUPPORT_SHA512_256=y +CONFIG_SOC_SHA_SUPPORT_SHA512_T=y +CONFIG_SOC_MPI_MEM_BLOCKS_NUM=4 +CONFIG_SOC_MPI_OPERATIONS_NUM=3 +CONFIG_SOC_RSA_MAX_BIT_LEN=4096 +CONFIG_SOC_AES_SUPPORT_DMA=y +CONFIG_SOC_AES_GDMA=y +CONFIG_SOC_AES_SUPPORT_AES_128=y +CONFIG_SOC_AES_SUPPORT_AES_256=y +CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_CPU_PD=y +CONFIG_SOC_PM_SUPPORT_TAGMEM_PD=y +CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y +CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y +CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y +CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y +CONFIG_SOC_PM_SUPPORT_MODEM_PD=y +CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED=y +CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY=y +CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL=y +CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA=y +CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y +CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y +CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y +CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y +CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y +CONFIG_SOC_EFUSE_DIS_DOWNLOAD_DCACHE=y +CONFIG_SOC_EFUSE_HARD_DIS_JTAG=y +CONFIG_SOC_EFUSE_DIS_USB_JTAG=y +CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y +CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y +CONFIG_SOC_EFUSE_DIS_ICACHE=y +CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y +CONFIG_SOC_SECURE_BOOT_V2_RSA=y +CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3 +CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y +CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y +CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=64 +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_256=y +CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16 +CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=256 +CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21 +CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192 +CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12 +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y +CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_OPI_MODE=y +CONFIG_SOC_SPI_MEM_SUPPORT_TIMING_TUNING=y +CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y +CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y +CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY=y +CONFIG_SOC_MEMSPI_CORE_CLK_SHARED_WITH_PSRAM=y +CONFIG_SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP=y +CONFIG_SOC_COEX_HW_PTI=y +CONFIG_SOC_EXTERNAL_COEX_LEADER_TX_LINE=y +CONFIG_SOC_SDMMC_USE_GPIO_MATRIX=y +CONFIG_SOC_SDMMC_NUM_SLOTS=2 +CONFIG_SOC_SDMMC_SUPPORT_XTAL_CLOCK=y +CONFIG_SOC_SDMMC_DELAY_PHASE_NUM=4 +CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y +CONFIG_SOC_WIFI_HW_TSF=y +CONFIG_SOC_WIFI_FTM_SUPPORT=y +CONFIG_SOC_WIFI_GCMP_SUPPORT=y +CONFIG_SOC_WIFI_WAPI_SUPPORT=y +CONFIG_SOC_WIFI_CSI_SUPPORT=y +CONFIG_SOC_WIFI_MESH_SUPPORT=y +CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y +CONFIG_SOC_WIFI_PHY_NEEDS_USB_WORKAROUND=y +CONFIG_SOC_BLE_SUPPORTED=y +CONFIG_SOC_BLE_MESH_SUPPORTED=y +CONFIG_SOC_BLE_50_SUPPORTED=y +CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y +CONFIG_SOC_BLUFI_SUPPORTED=y +CONFIG_SOC_ULP_HAS_ADC=y +CONFIG_SOC_PHY_COMBO_MODULE=y +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TOOLCHAIN="gcc" +CONFIG_IDF_TARGET_ARCH_XTENSA=y +CONFIG_IDF_TARGET_ARCH="xtensa" +CONFIG_IDF_TARGET="esp32s3" +CONFIG_IDF_INIT_VERSION="5.3.2" +CONFIG_IDF_TARGET_ESP32S3=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0009 + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# CONFIG_APP_REPRODUCIBLE_BUILD is not set +# CONFIG_APP_NO_BLOBS is not set +# end of Build type + +# +# Bootloader config +# + +# +# Bootloader manager +# +CONFIG_BOOTLOADER_COMPILE_TIME_DATE=y +CONFIG_BOOTLOADER_PROJECT_VER=1 +# end of Bootloader manager + +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0 +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set +CONFIG_BOOTLOADER_LOG_LEVEL=3 + +# +# Serial Flash Configurations +# +# CONFIG_BOOTLOADER_FLASH_DC_AWARE is not set +CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y +# end of Serial Flash Configurations + +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +# end of Bootloader config + +# +# Security features +# +CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y +CONFIG_SECURE_BOOT_V2_PREFERRED=y +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT is not set +# CONFIG_SECURE_FLASH_ENC_ENABLED is not set +CONFIG_SECURE_ROM_DL_MODE_ENABLED=y +# end of Security features + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=9 +# end of Application manager + +CONFIG_ESP_ROM_HAS_CRC_LE=y +CONFIG_ESP_ROM_HAS_CRC_BE=y +CONFIG_ESP_ROM_HAS_MZ_CRC32=y +CONFIG_ESP_ROM_HAS_JPEG_DECODE=y +CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y +CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y +CONFIG_ESP_ROM_USB_OTG_NUM=3 +CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=4 +CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG=y +CONFIG_ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV=y +CONFIG_ESP_ROM_GET_CLK_FREQ=y +CONFIG_ESP_ROM_HAS_HAL_WDT=y +CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y +CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y +CONFIG_ESP_ROM_HAS_SPI_FLASH=y +CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y +CONFIG_ESP_ROM_HAS_NEWLIB=y +CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y +CONFIG_ESP_ROM_HAS_NEWLIB_32BIT_TIME=y +CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y +CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y +CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG=y +CONFIG_ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG=y +CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG=y +CONFIG_ESP_ROM_HAS_SW_FLOAT=y +CONFIG_ESP_ROM_HAS_VERSION=y +CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB=y + +# +# Boot ROM Behavior +# +CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y +# CONFIG_BOOT_ROM_LOG_ALWAYS_OFF is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW is not set +# end of Boot ROM Behavior + +# +# Serial flasher config +# +# CONFIG_ESPTOOLPY_NO_STUB is not set +# CONFIG_ESPTOOLPY_OCT_FLASH is not set +CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT=y +# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y +CONFIG_ESPTOOLPY_FLASHMODE="dio" +# CONFIG_ESPTOOLPY_FLASHFREQ_120M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_80M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y +CONFIG_ESPTOOLPY_FLASHFREQ="80m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_32MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="2MB" +# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 +# end of Serial flasher config + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP=y +# CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +# CONFIG_PARTITION_TABLE_CUSTOM is not set +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Compiler options +# +CONFIG_COMPILER_OPTIMIZATION_DEBUG=y +# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set +# CONFIG_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_COMPILER_OPTIMIZATION_NONE is not set +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set +CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set +CONFIG_COMPILER_HIDE_PATHS_MACROS=y +# CONFIG_COMPILER_CXX_EXCEPTIONS is not set +# CONFIG_COMPILER_CXX_RTTI is not set +CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set +# CONFIG_COMPILER_DISABLE_GCC13_WARNINGS is not set +# CONFIG_COMPILER_DUMP_RTL_FILES is not set +CONFIG_COMPILER_RT_LIB_GCCLIB=y +CONFIG_COMPILER_RT_LIB_NAME="gcc" +# CONFIG_COMPILER_ORPHAN_SECTIONS_WARNING is not set +CONFIG_COMPILER_ORPHAN_SECTIONS_PLACE=y +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_JTAG is not set +CONFIG_APPTRACE_DEST_NONE=y +# CONFIG_APPTRACE_DEST_UART1 is not set +# CONFIG_APPTRACE_DEST_UART2 is not set +# CONFIG_APPTRACE_DEST_USB_CDC is not set +CONFIG_APPTRACE_DEST_UART_NONE=y +CONFIG_APPTRACE_UART_TASK_PRIO=1 +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +# +# Bluetooth +# +# CONFIG_BT_ENABLED is not set +CONFIG_BT_ALARM_MAX_NUM=50 +# end of Bluetooth + +# +# Console Library +# +# CONFIG_CONSOLE_SORTED_HELP is not set +# end of Console Library + +# +# Driver Configurations +# + +# +# TWAI Configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y +# end of TWAI Configuration + +# +# Legacy ADC Driver Configuration +# +# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set + +# +# Legacy ADC Calibration Configuration +# +# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy ADC Calibration Configuration +# end of Legacy ADC Driver Configuration + +# +# Legacy MCPWM Driver Configurations +# +# CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy MCPWM Driver Configurations + +# +# Legacy Timer Group Driver Configurations +# +# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy Timer Group Driver Configurations + +# +# Legacy RMT Driver Configurations +# +# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy RMT Driver Configurations + +# +# Legacy I2S Driver Configurations +# +# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy I2S Driver Configurations + +# +# Legacy PCNT Driver Configurations +# +# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy PCNT Driver Configurations + +# +# Legacy SDM Driver Configurations +# +# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy SDM Driver Configurations + +# +# Legacy Temperature Sensor Driver Configurations +# +# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy Temperature Sensor Driver Configurations +# end of Driver Configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +CONFIG_EFUSE_MAX_BLK_LEN=256 +# end of eFuse Bit Manager + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y +# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set +# CONFIG_ESP_TLS_SERVER_SESSION_TICKETS is not set +# CONFIG_ESP_TLS_SERVER_CERT_SELECT_HOOK is not set +# CONFIG_ESP_TLS_SERVER_MIN_AUTH_MODE_OPTIONAL is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# CONFIG_ESP_TLS_INSECURE is not set +# end of ESP-TLS + +# +# ADC and ADC Calibration +# +# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set +# CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set +# CONFIG_ADC_ENABLE_DEBUG_LOG is not set +# end of ADC and ADC Calibration + +# +# Wireless Coexistence +# +CONFIG_ESP_COEX_ENABLED=y +# CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set +# CONFIG_ESP_COEX_GPIO_DEBUG is not set +# end of Wireless Coexistence + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +# end of Common ESP-related + +# +# ESP-Driver:GPIO Configurations +# +# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set +# end of ESP-Driver:GPIO Configurations + +# +# ESP-Driver:GPTimer Configurations +# +CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM=y +# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set +# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:GPTimer Configurations + +# +# ESP-Driver:I2C Configurations +# +# CONFIG_I2C_ISR_IRAM_SAFE is not set +# CONFIG_I2C_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:I2C Configurations + +# +# ESP-Driver:I2S Configurations +# +# CONFIG_I2S_ISR_IRAM_SAFE is not set +# CONFIG_I2S_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:I2S Configurations + +# +# ESP-Driver:LEDC Configurations +# +# CONFIG_LEDC_CTRL_FUNC_IN_IRAM is not set +# end of ESP-Driver:LEDC Configurations + +# +# ESP-Driver:MCPWM Configurations +# +# CONFIG_MCPWM_ISR_IRAM_SAFE is not set +# CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:MCPWM Configurations + +# +# ESP-Driver:PCNT Configurations +# +# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_PCNT_ISR_IRAM_SAFE is not set +# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:PCNT Configurations + +# +# ESP-Driver:RMT Configurations +# +# CONFIG_RMT_ISR_IRAM_SAFE is not set +# CONFIG_RMT_RECV_FUNC_IN_IRAM is not set +# CONFIG_RMT_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:RMT Configurations + +# +# ESP-Driver:Sigma Delta Modulator Configurations +# +# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_SDM_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:Sigma Delta Modulator Configurations + +# +# ESP-Driver:SPI Configurations +# +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# end of ESP-Driver:SPI Configurations + +# +# ESP-Driver:Touch Sensor Configurations +# +# CONFIG_TOUCH_CTRL_FUNC_IN_IRAM is not set +# CONFIG_TOUCH_ISR_IRAM_SAFE is not set +# CONFIG_TOUCH_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:Touch Sensor Configurations + +# +# ESP-Driver:Temperature Sensor Configurations +# +# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set +# end of ESP-Driver:Temperature Sensor Configurations + +# +# ESP-Driver:UART Configurations +# +# CONFIG_UART_ISR_IN_IRAM is not set +# end of ESP-Driver:UART Configurations + +# +# ESP-Driver:USB Serial/JTAG Configuration +# +CONFIG_USJ_ENABLE_USB_SERIAL_JTAG=y +# end of ESP-Driver:USB Serial/JTAG Configuration + +# +# Ethernet +# +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_SPI_ETHERNET=y +# CONFIG_ETH_SPI_ETHERNET_DM9051 is not set +# CONFIG_ETH_SPI_ETHERNET_W5500 is not set +# CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set +# CONFIG_ETH_USE_OPENETH is not set +# CONFIG_ETH_TRANSMIT_MUTEX is not set +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y +# end of Event Loop Library + +# +# GDB Stub +# +CONFIG_ESP_GDBSTUB_ENABLED=y +# CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set +CONFIG_ESP_GDBSTUB_SUPPORT_TASKS=y +CONFIG_ESP_GDBSTUB_MAX_TASKS=32 +# end of GDB Stub + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +# CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH is not set +# CONFIG_ESP_HTTP_CLIENT_ENABLE_CUSTOM_TRANSPORT is not set +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set +# CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set +# end of ESP HTTPS server + +# +# Hardware Settings +# + +# +# Chip revision +# +CONFIG_ESP32S3_REV_MIN_0=y +# CONFIG_ESP32S3_REV_MIN_1 is not set +# CONFIG_ESP32S3_REV_MIN_2 is not set +CONFIG_ESP32S3_REV_MIN_FULL=0 +CONFIG_ESP_REV_MIN_FULL=0 + +# +# Maximum Supported ESP32-S3 Revision (Rev v0.99) +# +CONFIG_ESP32S3_REV_MAX_FULL=99 +CONFIG_ESP_REV_MAX_FULL=99 +CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL=0 +CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL=199 + +# +# Maximum Supported ESP32-S3 eFuse Block Revision (eFuse Block Rev v1.99) +# +# end of Chip revision + +# +# MAC Config +# +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y +CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y +CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES=4 +# CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO is not set +CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR=y +CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES=4 +# CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC is not set +# end of MAC Config + +# +# Sleep Config +# +# CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set +CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y +CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU=y +CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y +CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=y +CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY=2000 +# CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION is not set +# CONFIG_ESP_SLEEP_DEBUG is not set +CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS=y +# end of Sleep Config + +# +# RTC Clock Config +# +CONFIG_RTC_CLK_SRC_INT_RC=y +# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_RTC_CLK_CAL_CYCLES=1024 +# end of RTC Clock Config + +# +# Peripheral Control +# +CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y +# end of Peripheral Control + +# +# GDMA Configurations +# +CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y +# CONFIG_GDMA_ISR_IRAM_SAFE is not set +# CONFIG_GDMA_ENABLE_DEBUG_LOG is not set +# end of GDMA Configurations + +# +# Main XTAL Config +# +CONFIG_XTAL_FREQ_40=y +CONFIG_XTAL_FREQ=40 +# end of Main XTAL Config + +CONFIG_ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM=y +# end of Hardware Settings + +# +# LCD and Touch Panel +# + +# +# LCD Touch Drivers are maintained in the IDF Component Registry +# + +# +# LCD Peripheral Configuration +# +# CONFIG_LCD_ENABLE_DEBUG_LOG is not set +# CONFIG_LCD_RGB_ISR_IRAM_SAFE is not set +# CONFIG_LCD_RGB_RESTART_IN_VSYNC is not set +# end of LCD Peripheral Configuration +# end of LCD and Touch Panel + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y +# CONFIG_ESP_NETIF_RECEIVE_REPORT_ERRORS is not set +# CONFIG_ESP_NETIF_L2_TAP is not set +# CONFIG_ESP_NETIF_BRIDGE_EN is not set +# CONFIG_ESP_NETIF_SET_DNS_PER_DEFAULT_NETIF is not set +# end of ESP NETIF Adapter + +# +# Partition API Configuration +# +# end of Partition API Configuration + +# +# PHY +# +CONFIG_ESP_PHY_ENABLED=y +CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP_PHY_MAX_TX_POWER=20 +# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set +CONFIG_ESP_PHY_ENABLE_USB=y +# CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set +CONFIG_ESP_PHY_RF_CAL_PARTIAL=y +# CONFIG_ESP_PHY_RF_CAL_NONE is not set +# CONFIG_ESP_PHY_RF_CAL_FULL is not set +CONFIG_ESP_PHY_CALIBRATION_MODE=0 +# CONFIG_ESP_PHY_PLL_TRACK_DEBUG is not set +# end of PHY + +# +# Power Management +# +# CONFIG_PM_ENABLE is not set +# CONFIG_PM_SLP_IRAM_OPT is not set +CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y +CONFIG_PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP=y +# end of Power Management + +# +# ESP PSRAM +# +# CONFIG_SPIRAM is not set +# end of ESP PSRAM + +# +# ESP Ringbuf +# +# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set +# end of ESP Ringbuf + +# +# ESP System Settings +# +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160 + +# +# Cache config +# +CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y +# CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE=0x4000 +# CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS=y +CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS=8 +# CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B=y +CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE=32 +# CONFIG_ESP32S3_DATA_CACHE_16KB is not set +CONFIG_ESP32S3_DATA_CACHE_32KB=y +# CONFIG_ESP32S3_DATA_CACHE_64KB is not set +CONFIG_ESP32S3_DATA_CACHE_SIZE=0x8000 +# CONFIG_ESP32S3_DATA_CACHE_4WAYS is not set +CONFIG_ESP32S3_DATA_CACHE_8WAYS=y +CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS=8 +# CONFIG_ESP32S3_DATA_CACHE_LINE_16B is not set +CONFIG_ESP32S3_DATA_CACHE_LINE_32B=y +# CONFIG_ESP32S3_DATA_CACHE_LINE_64B is not set +CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32 +# end of Cache config + +# +# Memory +# +# CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM is not set +# CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE is not set +# end of Memory + +# +# Trace memory +# +# CONFIG_ESP32S3_TRAX is not set +CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0 +# end of Trace memory + +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0 +CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y +CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y + +# +# Memory protection +# +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y +# end of Memory protection + +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y +# CONFIG_ESP_MAIN_TASK_AFFINITY_CPU1 is not set +# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_ESP_MAIN_TASK_AFFINITY=0x0 +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +CONFIG_ESP_CONSOLE_UART_DEFAULT=y +# CONFIG_ESP_CONSOLE_USB_CDC is not set +# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG is not set +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_NONE is not set +# CONFIG_ESP_CONSOLE_SECONDARY_NONE is not set +CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG=y +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED=y +CONFIG_ESP_CONSOLE_UART=y +CONFIG_ESP_CONSOLE_UART_NUM=0 +CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM=0 +CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ESP_INT_WDT=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 +CONFIG_ESP_INT_WDT_CHECK_CPU1=y +CONFIG_ESP_TASK_WDT_EN=y +CONFIG_ESP_TASK_WDT_INIT=y +# CONFIG_ESP_TASK_WDT_PANIC is not set +CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set +# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP_DEBUG_OCDAWARE=y +CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y + +# +# Brownout Detector +# +CONFIG_ESP_BROWNOUT_DET=y +CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_ESP_BROWNOUT_DET_LVL=7 +# end of Brownout Detector + +CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y +CONFIG_ESP_SYSTEM_BBPLL_RECALIB=y +# end of ESP System Settings + +# +# IPC (Inter-Processor Call) +# +CONFIG_ESP_IPC_TASK_STACK_SIZE=1280 +CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y +CONFIG_ESP_IPC_ISR_ENABLE=y +# end of IPC (Inter-Processor Call) + +# +# ESP Timer (High Resolution Timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y +CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y +CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1 +# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set +CONFIG_ESP_TIMER_TASK_AFFINITY=0x0 +CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y +CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y +# CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set +CONFIG_ESP_TIMER_IMPL_SYSTIMER=y +# end of ESP Timer (High Resolution Timer) + +# +# Wi-Fi +# +CONFIG_ESP_WIFI_ENABLED=y +CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP_WIFI_STATIC_TX_BUFFER is not set +CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER=y +CONFIG_ESP_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +CONFIG_ESP_WIFI_STATIC_RX_MGMT_BUFFER=y +# CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUFFER is not set +CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUF=0 +CONFIG_ESP_WIFI_RX_MGMT_BUF_NUM_DEF=5 +# CONFIG_ESP_WIFI_CSI_ENABLED is not set +CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP_WIFI_TX_BA_WIN=6 +CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP_WIFI_RX_BA_WIN=6 +CONFIG_ESP_WIFI_NVS_ENABLED=y +CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_0=y +# CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_1 is not set +CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP_WIFI_IRAM_OPT=y +# CONFIG_ESP_WIFI_EXTRA_IRAM_OPT is not set +CONFIG_ESP_WIFI_RX_IRAM_OPT=y +CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y +CONFIG_ESP_WIFI_ENABLE_SAE_PK=y +CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y +CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y +# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set +CONFIG_ESP_WIFI_SLP_DEFAULT_MIN_ACTIVE_TIME=50 +CONFIG_ESP_WIFI_SLP_DEFAULT_MAX_ACTIVE_TIME=10 +CONFIG_ESP_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME=15 +# CONFIG_ESP_WIFI_FTM_ENABLE is not set +CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE=y +# CONFIG_ESP_WIFI_GCMP_SUPPORT is not set +CONFIG_ESP_WIFI_GMAC_SUPPORT=y +CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y +# CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set +CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7 +CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y +CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y +# CONFIG_ESP_WIFI_WAPI_PSK is not set +# CONFIG_ESP_WIFI_SUITE_B_192 is not set +# CONFIG_ESP_WIFI_11KV_SUPPORT is not set +# CONFIG_ESP_WIFI_MBO_SUPPORT is not set +# CONFIG_ESP_WIFI_DPP_SUPPORT is not set +# CONFIG_ESP_WIFI_11R_SUPPORT is not set +# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set + +# +# WPS Configuration Options +# +# CONFIG_ESP_WIFI_WPS_STRICT is not set +# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set +# end of WPS Configuration Options + +# CONFIG_ESP_WIFI_DEBUG_PRINT is not set +# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set +CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT=y +# CONFIG_ESP_WIFI_ENT_FREE_DYNAMIC_BUFFER is not set +# end of Wi-Fi + +# +# Core dump +# +# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y +# end of Core dump + +# +# FAT Filesystem support +# +CONFIG_FATFS_VOLUME_COUNT=2 +CONFIG_FATFS_LFN_NONE=y +# CONFIG_FATFS_LFN_HEAP is not set +# CONFIG_FATFS_LFN_STACK is not set +# CONFIG_FATFS_SECTOR_512 is not set +CONFIG_FATFS_SECTOR_4096=y +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +# CONFIG_FATFS_USE_FASTSEEK is not set +CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0 +# CONFIG_FATFS_IMMEDIATE_FSYNC is not set +# CONFIG_FATFS_USE_LABEL is not set +CONFIG_FATFS_LINK_LOCK=y +# end of FAT Filesystem support + +# +# FreeRTOS +# + +# +# Kernel +# +# CONFIG_FREERTOS_SMP is not set +# CONFIG_FREERTOS_UNICORE is not set +CONFIG_FREERTOS_HZ=100 +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +# CONFIG_FREERTOS_USE_IDLE_HOOK is not set +# CONFIG_FREERTOS_USE_TICK_HOOK is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set +CONFIG_FREERTOS_TIMER_SERVICE_TASK_NAME="Tmr Svc" +# CONFIG_FREERTOS_TIMER_TASK_AFFINITY_CPU0 is not set +# CONFIG_FREERTOS_TIMER_TASK_AFFINITY_CPU1 is not set +CONFIG_FREERTOS_TIMER_TASK_NO_AFFINITY=y +CONFIG_FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1 +# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set +# CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +# CONFIG_FREERTOS_USE_APPLICATION_TASK_TAG is not set +# end of Kernel + +# +# Port +# +CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y +# CONFIG_FREERTOS_TASK_PRE_DELETION_HOOK is not set +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y +CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y +# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set +CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y +# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +# end of Port + +CONFIG_FREERTOS_PORT=y +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y +CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH=y +CONFIG_FREERTOS_NUMBER_OF_CORES=2 +# end of FreeRTOS + +# +# Hardware Abstraction Layer (HAL) and Low Level (LL) +# +CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y +# CONFIG_HAL_ASSERTION_DISABLE is not set +# CONFIG_HAL_ASSERTION_SILENT is not set +# CONFIG_HAL_ASSERTION_ENABLE is not set +CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2 +CONFIG_HAL_WDT_USE_ROM_IMPL=y +CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y +CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y +# CONFIG_HAL_ECDSA_GEN_SIG_CM is not set +# end of Hardware Abstraction Layer (HAL) and Low Level (LL) + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +# CONFIG_HEAP_POISONING_LIGHT is not set +# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set +CONFIG_HEAP_TRACING_OFF=y +# CONFIG_HEAP_TRACING_STANDALONE is not set +# CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_USE_HOOKS is not set +# CONFIG_HEAP_TASK_TRACKING is not set +# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set +# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set +# end of Heap memory debugging + +# +# Log output +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y +# CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set +# CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set +CONFIG_LOG_MAXIMUM_LEVEL=3 +# CONFIG_LOG_MASTER_LEVEL is not set +CONFIG_LOG_COLORS=y +CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set +# end of Log output + +# +# LWIP +# +CONFIG_LWIP_ENABLE=y +CONFIG_LWIP_LOCAL_HOSTNAME="espressif" +# CONFIG_LWIP_NETIF_API is not set +CONFIG_LWIP_TCPIP_TASK_PRIO=18 +# CONFIG_LWIP_TCPIP_CORE_LOCKING is not set +# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +# CONFIG_LWIP_EXTRA_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_ND6=y +# CONFIG_LWIP_FORCE_ROUTER_FORWARDING is not set +CONFIG_LWIP_MAX_SOCKETS=10 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +# CONFIG_LWIP_SO_LINGER is not set +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +# CONFIG_LWIP_SO_RCVBUF is not set +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP_DEFAULT_TTL=64 +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set +CONFIG_LWIP_IP_REASS_MAX_PBUFS=10 +# CONFIG_LWIP_IP_FORWARD is not set +# CONFIG_LWIP_STATS is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_ESP_MLDV6_REPORT=y +CONFIG_LWIP_MLDV6_TMR_INTERVAL=40 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set +CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCP_OPTIONS_LEN=68 +CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0 +CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1 + +# +# DHCP server +# +CONFIG_LWIP_DHCPS=y +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +CONFIG_LWIP_DHCPS_STATIC_ENTRIES=y +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_IPV4=y +CONFIG_LWIP_IPV6=y +# CONFIG_LWIP_IPV6_AUTOCONFIG is not set +CONFIG_LWIP_IPV6_NUM_ADDRESSES=3 +# CONFIG_LWIP_IPV6_FORWARD is not set +# CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=12 +CONFIG_LWIP_TCP_MSS=1440 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT=20000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5760 +CONFIG_LWIP_TCP_WND_DEFAULT=5760 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 +CONFIG_LWIP_TCP_ACCEPTMBOX_SIZE=6 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +CONFIG_LWIP_TCP_OOSEQ_TIMEOUT=6 +CONFIG_LWIP_TCP_OOSEQ_MAX_PBUFS=4 +# CONFIG_LWIP_TCP_SACK_OUT is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=1500 +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +# +# Checksums +# +# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set +# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set +CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y +# end of Checksums + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF +CONFIG_LWIP_IPV6_ND6_NUM_PREFIXES=5 +CONFIG_LWIP_IPV6_ND6_NUM_ROUTERS=3 +CONFIG_LWIP_IPV6_ND6_NUM_DESTINATIONS=10 +# CONFIG_LWIP_PPP_SUPPORT is not set +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 +# CONFIG_LWIP_SLIP_SUPPORT is not set + +# +# ICMP +# +CONFIG_LWIP_ICMP=y +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_SNTP_MAX_SERVERS=1 +# CONFIG_LWIP_DHCP_GET_NTP_SRV is not set +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +CONFIG_LWIP_SNTP_STARTUP_DELAY=y +CONFIG_LWIP_SNTP_MAXIMUM_STARTUP_DELAY=5000 +# end of SNTP + +# +# DNS +# +CONFIG_LWIP_DNS_MAX_HOST_IP=1 +CONFIG_LWIP_DNS_MAX_SERVERS=3 +# CONFIG_LWIP_FALLBACK_DNS_SERVER_SUPPORT is not set +# CONFIG_LWIP_DNS_SETSERVER_WITH_NETIF is not set +# end of DNS + +CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7 +CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Hooks +# +# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set +CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y +# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y +# CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set +# CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE=y +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM is not set +CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +CONFIG_LWIP_HOOK_DNS_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_DNS_EXT_RESOLVE_CUSTOM is not set +# CONFIG_LWIP_HOOK_IP6_INPUT_NONE is not set +CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT=y +# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set +# end of Hooks + +# CONFIG_LWIP_DEBUG is not set +# end of LWIP + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 +# CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set +# CONFIG_MBEDTLS_DEBUG is not set + +# +# mbedTLS v3.x related +# +# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set +# CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set +# CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set +# CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set +CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y +CONFIG_MBEDTLS_PKCS7_C=y +# end of mbedTLS v3.x related + +# +# Certificate Bundle +# +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set +# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEPRECATED_LIST is not set +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200 +# end of Certificate Bundle + +# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set +CONFIG_MBEDTLS_CMAC_C=y +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_AES_USE_INTERRUPT=y +CONFIG_MBEDTLS_AES_INTERRUPT_LEVEL=0 +CONFIG_MBEDTLS_GCM_SUPPORT_NON_AES_CIPHER=y +CONFIG_MBEDTLS_HARDWARE_MPI=y +# CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set +CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y +CONFIG_MBEDTLS_MPI_INTERRUPT_LEVEL=0 +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_ROM_MD5=y +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set +CONFIG_MBEDTLS_HAVE_TIME=y +# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set +# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set +CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y +CONFIG_MBEDTLS_SHA512_C=y +# CONFIG_MBEDTLS_SHA3_C is not set +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +# CONFIG_MBEDTLS_DES_C is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +# CONFIG_MBEDTLS_XTEA_C is not set +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_NIST_KW_C is not set +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C is not set + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +# CONFIG_MBEDTLS_DHM_C is not set +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +# CONFIG_MBEDTLS_ECJPAKE_C is not set +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +# CONFIG_MBEDTLS_ECP_FIXED_POINT_OPTIM is not set +# CONFIG_MBEDTLS_POLY1305_C is not set +# CONFIG_MBEDTLS_CHACHA20_C is not set +# CONFIG_MBEDTLS_HKDF_C is not set +# CONFIG_MBEDTLS_THREADING_C is not set +CONFIG_MBEDTLS_ERROR_STRINGS=y +CONFIG_MBEDTLS_FS_IO=y +# end of mbedTLS + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +# CONFIG_MQTT_PROTOCOL_5 is not set +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set +# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set +# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y +# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set +# end of Newlib + +# +# NVS +# +# CONFIG_NVS_ENCRYPTION is not set +# CONFIG_NVS_ASSERT_ERROR_CHECK is not set +# CONFIG_NVS_LEGACY_DUP_KEYS_COMPATIBILITY is not set +# end of NVS + +# +# OpenThread +# +# CONFIG_OPENTHREAD_ENABLED is not set + +# +# Thread Operational Dataset +# +CONFIG_OPENTHREAD_NETWORK_NAME="OpenThread-ESP" +CONFIG_OPENTHREAD_MESH_LOCAL_PREFIX="fd00:db8:a0:0::/64" +CONFIG_OPENTHREAD_NETWORK_CHANNEL=15 +CONFIG_OPENTHREAD_NETWORK_PANID=0x1234 +CONFIG_OPENTHREAD_NETWORK_EXTPANID="dead00beef00cafe" +CONFIG_OPENTHREAD_NETWORK_MASTERKEY="00112233445566778899aabbccddeeff" +CONFIG_OPENTHREAD_NETWORK_PSKC="104810e2315100afd6bc9215a6bfac53" +# end of Thread Operational Dataset + +CONFIG_OPENTHREAD_XTAL_ACCURACY=130 +# CONFIG_OPENTHREAD_SPINEL_ONLY is not set +CONFIG_OPENTHREAD_RX_ON_WHEN_IDLE=y + +# +# Thread Address Query Config +# +# end of Thread Address Query Config +# end of OpenThread + +# +# Protocomm +# +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y +# end of Protocomm + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY=y +# CONFIG_PTHREAD_DEFAULT_CORE_0 is not set +# CONFIG_PTHREAD_DEFAULT_CORE_1 is not set +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# MMU Config +# +CONFIG_MMU_PAGE_SIZE_64KB=y +CONFIG_MMU_PAGE_MODE="64KB" +CONFIG_MMU_PAGE_SIZE=0x10000 +# end of MMU Config + +# +# Main Flash configuration +# + +# +# SPI Flash behavior when brownout +# +CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y +CONFIG_SPI_FLASH_BROWNOUT_RESET=y +# end of SPI Flash behavior when brownout + +# +# Optional and Experimental Features (READ DOCS FIRST) +# + +# +# Features here require specific hardware (READ DOCS FIRST!) +# +# CONFIG_SPI_FLASH_HPM_ENA is not set +CONFIG_SPI_FLASH_HPM_AUTO=y +# CONFIG_SPI_FLASH_HPM_DIS is not set +CONFIG_SPI_FLASH_HPM_ON=y +CONFIG_SPI_FLASH_HPM_DC_AUTO=y +# CONFIG_SPI_FLASH_HPM_DC_DISABLE is not set +CONFIG_SPI_FLASH_SUSPEND_QVL_SUPPORTED=y +# CONFIG_SPI_FLASH_AUTO_SUSPEND is not set +CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US=50 +# CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND is not set +# end of Optional and Experimental Features (READ DOCS FIRST) +# end of Main Flash configuration + +# +# SPI Flash driver +# +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +# CONFIG_SPI_FLASH_ROM_IMPL is not set +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 +# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set +# CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED=y +CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_TH_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP=y +# end of Auto-detect flash chips + +CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TCP Transport +# + +# +# Websocket +# +CONFIG_WS_TRANSPORT=y +CONFIG_WS_BUFFER_SIZE=1024 +# CONFIG_WS_DYNAMIC_BUFFER is not set +# end of Websocket +# end of TCP Transport + +# +# Ultra Low Power (ULP) Co-processor +# +# CONFIG_ULP_COPROC_ENABLED is not set + +# +# ULP Debugging Options +# +# end of ULP Debugging Options +# end of Ultra Low Power (ULP) Co-processor + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_64BIT is not set +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# USB-OTG +# +CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=256 +CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED=y +# CONFIG_USB_HOST_HW_BUFFER_BIAS_IN is not set +# CONFIG_USB_HOST_HW_BUFFER_BIAS_PERIODIC_OUT is not set + +# +# Hub Driver Configuration +# + +# +# Root Port configuration +# +CONFIG_USB_HOST_DEBOUNCE_DELAY_MS=250 +CONFIG_USB_HOST_RESET_HOLD_MS=30 +CONFIG_USB_HOST_RESET_RECOVERY_MS=30 +CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS=10 +# end of Root Port configuration + +# CONFIG_USB_HOST_HUBS_SUPPORTED is not set +# end of Hub Driver Configuration + +# CONFIG_USB_HOST_ENABLE_ENUM_FILTER_CALLBACK is not set +CONFIG_USB_OTG_SUPPORTED=y +# end of USB-OTG + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +CONFIG_VFS_SUPPORT_SELECT=y +CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y +# CONFIG_VFS_SELECT_IN_RAM is not set +CONFIG_VFS_SUPPORT_TERMIOS=y +CONFIG_VFS_MAX_COUNT=8 + +# +# Host File System I/O (Semihosting) +# +CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# end of Host File System I/O (Semihosting) +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y +# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set +# end of Wi-Fi Provisioning Manager +# end of Component config + +# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set + +# Deprecated options for backward compatibility +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +# CONFIG_NO_BLOBS is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set +CONFIG_LOG_BOOTLOADER_LEVEL=3 +# CONFIG_APP_ROLLBACK_ENABLE is not set +# CONFIG_FLASH_ENCRYPTION_ENABLED is not set +# CONFIG_FLASHMODE_QIO is not set +# CONFIG_FLASHMODE_QOUT is not set +CONFIG_FLASHMODE_DIO=y +# CONFIG_FLASHMODE_DOUT is not set +CONFIG_MONITOR_BAUD=115200 +CONFIG_OPTIMIZATION_LEVEL_DEBUG=y +CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y +CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y +# CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set +# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set +CONFIG_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_CXX_EXCEPTIONS is not set +CONFIG_STACK_CHECK_NONE=y +# CONFIG_STACK_CHECK_NORM is not set +# CONFIG_STACK_CHECK_STRONG is not set +# CONFIG_STACK_CHECK_ALL is not set +# CONFIG_WARN_WRITE_STRINGS is not set +# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +# CONFIG_EXTERNAL_COEX_ENABLE is not set +# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set +# CONFIG_MCPWM_ISR_IN_IRAM is not set +# CONFIG_EVENT_LOOP_PROFILING is not set +CONFIG_POST_EVENTS_FROM_ISR=y +CONFIG_POST_EVENTS_FROM_IRAM_ISR=y +CONFIG_GDBSTUB_SUPPORT_TASKS=y +CONFIG_GDBSTUB_MAX_TASKS=32 +# CONFIG_OTA_ALLOW_HTTP is not set +# CONFIG_ESP_SYSTEM_PD_FLASH is not set +CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 +# CONFIG_REDUCE_PHY_TX_POWER is not set +# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set +CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y +CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP=y +# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set +# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_80 is not set +CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160=y +# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240 is not set +CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ=160 +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_CONSOLE_UART_DEFAULT=y +# CONFIG_CONSOLE_UART_CUSTOM is not set +# CONFIG_CONSOLE_UART_NONE is not set +# CONFIG_ESP_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART=y +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_INT_WDT_CHECK_CPU1=y +CONFIG_TASK_WDT=y +CONFIG_ESP_TASK_WDT=y +# CONFIG_TASK_WDT_PANIC is not set +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP32S3_DEBUG_OCDAWARE=y +CONFIG_BROWNOUT_DET=y +CONFIG_ESP32S3_BROWNOUT_DET=y +CONFIG_ESP32S3_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_7=y +CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_BROWNOUT_DET_LVL=7 +CONFIG_ESP32S3_BROWNOUT_DET_LVL=7 +CONFIG_IPC_TASK_STACK_SIZE=1280 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP32_WIFI_ENABLED=y +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_WIFI_RX_IRAM_OPT=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y +CONFIG_WPA_MBEDTLS_CRYPTO=y +CONFIG_WPA_MBEDTLS_TLS_CLIENT=y +# CONFIG_WPA_WAPI_PSK is not set +# CONFIG_WPA_SUITE_B_192 is not set +# CONFIG_WPA_11KV_SUPPORT is not set +# CONFIG_WPA_MBO_SUPPORT is not set +# CONFIG_WPA_DPP_SUPPORT is not set +# CONFIG_WPA_11R_SUPPORT is not set +# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set +# CONFIG_WPA_WPS_STRICT is not set +# CONFIG_WPA_DEBUG_PRINT is not set +# CONFIG_WPA_TESTING_OPTIONS is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set +# CONFIG_HAL_ASSERTION_SILIENT is not set +# CONFIG_L2_TO_L3_COPY is not set +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=12 +CONFIG_TCP_MSS=1440 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5760 +CONFIG_TCP_WND_DEFAULT=5760 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +CONFIG_TCP_OVERSIZE_MSS=y +# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_TCP_OVERSIZE_DISABLE is not set +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set +# CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_PPP_SUPPORT is not set +CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_SYSTIMER=y +CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1=y +# CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_SYSTIMER is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_FRC1 is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_ESP32_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0 is not set +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y +CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# End of deprecated options diff --git a/firmware/stm32f4xx/.clang-format b/firmware/stm32f4xx/.clang-format new file mode 100644 index 0000000..ecaef24 --- /dev/null +++ b/firmware/stm32f4xx/.clang-format @@ -0,0 +1 @@ +ColumnLimit: 0 \ No newline at end of file diff --git a/firmware/.cproject b/firmware/stm32f4xx/.cproject similarity index 100% rename from firmware/.cproject rename to firmware/stm32f4xx/.cproject diff --git a/firmware/.mxproject b/firmware/stm32f4xx/.mxproject similarity index 100% rename from firmware/.mxproject rename to firmware/stm32f4xx/.mxproject diff --git a/firmware/.project b/firmware/stm32f4xx/.project similarity index 100% rename from firmware/.project rename to firmware/stm32f4xx/.project diff --git a/firmware/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs b/firmware/stm32f4xx/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs similarity index 100% rename from firmware/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs rename to firmware/stm32f4xx/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs diff --git a/firmware/.settings/language.settings.xml b/firmware/stm32f4xx/.settings/language.settings.xml similarity index 100% rename from firmware/.settings/language.settings.xml rename to firmware/stm32f4xx/.settings/language.settings.xml diff --git a/firmware/.settings/stm32cubeide.project.prefs b/firmware/stm32f4xx/.settings/stm32cubeide.project.prefs similarity index 100% rename from firmware/.settings/stm32cubeide.project.prefs rename to firmware/stm32f4xx/.settings/stm32cubeide.project.prefs diff --git a/firmware/stm32f4xx/.vscode/c_cpp_properties.json b/firmware/stm32f4xx/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..d6bc528 --- /dev/null +++ b/firmware/stm32f4xx/.vscode/c_cpp_properties.json @@ -0,0 +1,18 @@ +{ + "configurations": [ + { + "name": "Firmware", + "includePath": [ + "${workspaceFolder}/Core/Inc", + + "${workspaceFolder}/Drivers/STM32F4xx_HAL_Driver/Inc/**", + "${workspaceFolder}/Drivers/CMSIS/Device/ST/STM32F4xx/Include", + "${workspaceFolder}/Drivers/CMSIS/Include", + + "${workspaceFolder}/tinyusb/src/**" + ], + "defines": ["USE_HAL_DRIVER", "STM32F411xE"] + } + ], + "version": 4 +} diff --git a/firmware/stm32f4xx/.vscode/extensions.json b/firmware/stm32f4xx/.vscode/extensions.json new file mode 100644 index 0000000..48a680b --- /dev/null +++ b/firmware/stm32f4xx/.vscode/extensions.json @@ -0,0 +1,3 @@ +{ + "recommendations": ["ms-vscode.cpptools", "xaver.clang-format"] +} diff --git a/firmware/stm32f4xx/.vscode/settings.json b/firmware/stm32f4xx/.vscode/settings.json new file mode 100644 index 0000000..ad92582 --- /dev/null +++ b/firmware/stm32f4xx/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "editor.formatOnSave": true +} diff --git a/firmware/stm32f4xx/Core/Inc/DRV2605L.h b/firmware/stm32f4xx/Core/Inc/DRV2605L.h new file mode 100644 index 0000000..1116e28 --- /dev/null +++ b/firmware/stm32f4xx/Core/Inc/DRV2605L.h @@ -0,0 +1,196 @@ +#ifndef _DRV2605_H +#define _DRV2605_H + +#include + +#define DRV2605_ADDR 0x5A ///< Device I2C address + +#define DRV2605_REG_STATUS 0x00 ///< Status register +#define DRV2605_REG_MODE 0x01 ///< Mode register +#define DRV2605_MODE_INTTRIG 0x00 ///< Internal trigger mode +#define DRV2605_MODE_EXTTRIGEDGE 0x01 ///< External edge trigger mode +#define DRV2605_MODE_EXTTRIGLVL 0x02 ///< External level trigger mode +#define DRV2605_MODE_PWMANALOG 0x03 ///< PWM/Analog input mode +#define DRV2605_MODE_AUDIOVIBE 0x04 ///< Audio-to-vibe mode +#define DRV2605_MODE_REALTIME 0x05 ///< Real-time playback (RTP) mode +#define DRV2605_MODE_DIAGNOS 0x06 ///< Diagnostics mode +#define DRV2605_MODE_AUTOCAL 0x07 ///< Auto calibration mode + +#define DRV2605_REG_RTPIN 0x02 ///< Real-time playback input register +#define DRV2605_REG_LIBRARY 0x03 ///< Waveform library selection register +#define DRV2605_REG_WAVESEQ1 0x04 ///< Waveform sequence register 1 +#define DRV2605_REG_WAVESEQ2 0x05 ///< Waveform sequence register 2 +#define DRV2605_REG_WAVESEQ3 0x06 ///< Waveform sequence register 3 +#define DRV2605_REG_WAVESEQ4 0x07 ///< Waveform sequence register 4 +#define DRV2605_REG_WAVESEQ5 0x08 ///< Waveform sequence register 5 +#define DRV2605_REG_WAVESEQ6 0x09 ///< Waveform sequence register 6 +#define DRV2605_REG_WAVESEQ7 0x0A ///< Waveform sequence register 7 +#define DRV2605_REG_WAVESEQ8 0x0B ///< Waveform sequence register 8 + +#define DRV2605_REG_GO 0x0C ///< Go register +#define DRV2605_REG_OVERDRIVE 0x0D ///< Overdrive time offset register +#define DRV2605_REG_SUSTAINPOS 0x0E ///< Sustain time offset, positive register +#define DRV2605_REG_SUSTAINNEG 0x0F ///< Sustain time offset, negative register +#define DRV2605_REG_BREAK 0x10 ///< Brake time offset register +#define DRV2605_REG_AUDIOCTRL 0x11 ///< Audio-to-vibe control register +#define DRV2605_REG_AUDIOLVL 0x12 ///< Audio-to-vibe minimum input level register +#define DRV2605_REG_AUDIOMAX 0x13 ///< Audio-to-vibe maximum input level register +#define DRV2605_REG_AUDIOOUTMIN 0x14 ///< Audio-to-vibe minimum output drive register +#define DRV2605_REG_AUDIOOUTMAX 0x15 ///< Audio-to-vibe maximum output drive register +#define DRV2605_REG_RATEDV 0x16 ///< Rated voltage register +#define DRV2605_REG_CLAMPV 0x17 ///< Overdrive clamp voltage register +#define DRV2605_REG_AUTOCALCOMP 0x18 ///< Auto-calibration compensation result register +#define DRV2605_REG_AUTOCALEMP 0x19 ///< Auto-calibration back-EMF result register +#define DRV2605_REG_FEEDBACK 0x1A ///< Feedback control register +#define DRV2605_REG_CONTROL1 0x1B ///< Control1 Register +#define DRV2605_REG_CONTROL2 0x1C ///< Control2 Register +#define DRV2605_REG_CONTROL3 0x1D ///< Control3 Register +#define DRV2605_REG_CONTROL4 0x1E ///< Control4 Register +#define DRV2605_REG_VBAT 0x21 ///< Vbat voltage-monitor register +#define DRV2605_REG_LRARESON 0x22 ///< LRA resonance-period register + +// Effects: +// 1 − Strong Click - 100% +// 2 − Strong Click - 60% +// 3 − Strong Click - 30% +// 4 − Sharp Click - 100% +// 5 − Sharp Click - 60% +// 6 − Sharp Click - 30% +// 7 − Soft Bump - 100% +// 8 − Soft Bump - 60% +// 9 − Soft Bump - 30% +// 10 − Double Click - 100% +// 11 − Double Click - 60% +// 12 − Triple Click - 100% +// 13 − Soft Fuzz - 60% +// 14 − Strong Buzz - 100% +// 15 − 750 ms Alert 100% +// 16 − 1000 ms Alert 100% +// 17 − Strong Click 1 - 100% +// 18 − Strong Click 2 - 80% +// 19 − Strong Click 3 - 60% +// 20 − Strong Click 4 - 30% +// 21 − Medium Click 1 - 100% +// 22 − Medium Click 2 - 80% +// 23 − Medium Click 3 - 60% +// 24 − Sharp Tick 1 - 100% +// 25 − Sharp Tick 2 - 80% +// 26 − Sharp Tick 3 – 60% +// 27 − Short Double Click Strong 1 – 100% +// 28 − Short Double Click Strong 2 – 80% +// 29 − Short Double Click Strong 3 – 60% +// 30 − Short Double Click Strong 4 – 30% +// 31 − Short Double Click Medium 1 – 100% +// 32 − Short Double Click Medium 2 – 80% +// 33 − Short Double Click Medium 3 – 60% +// 34 − Short Double Sharp Tick 1 – 100% +// 35 − Short Double Sharp Tick 2 – 80% +// 36 − Short Double Sharp Tick 3 – 60% +// 37 − Long Double Sharp Click Strong 1 – 100% +// 38 − Long Double Sharp Click Strong 2 – 80% +// 39 − Long Double Sharp Click Strong 3 – 60% +// 40 − Long Double Sharp Click Strong 4 – 30% +// 41 − Long Double Sharp Click Medium 1 – 100% +// 42 − Long Double Sharp Click Medium 2 – 80% +// 43 − Long Double Sharp Click Medium 3 – 60% +// 44 − Long Double Sharp Tick 1 – 100% +// 45 − Long Double Sharp Tick 2 – 80% +// 46 − Long Double Sharp Tick 3 – 60% +// 47 − Buzz 1 – 100% +// 48 − Buzz 2 – 80% +// 49 − Buzz 3 – 60% +// 50 − Buzz 4 – 40% +// 51 − Buzz 5 – 20% +// 52 − Pulsing Strong 1 – 100% +// 53 − Pulsing Strong 2 – 60% +// 54 − Pulsing Medium 1 – 100% +// 55 − Pulsing Medium 2 – 60% +// 56 − Pulsing Sharp 1 – 100% +// 57 − Pulsing Sharp 2 – 60% +// 58 − Transition Click 1 – 100% +// 59 − Transition Click 2 – 80% +// 60 − Transition Click 3 – 60% +// 61 − Transition Click 4 – 40% +// 62 − Transition Click 5 – 20% +// 63 − Transition Click 6 – 10% +// 64 − Transition Hum 1 – 100% +// 65 − Transition Hum 2 – 80% +// 66 − Transition Hum 3 – 60% +// 67 − Transition Hum 4 – 40% +// 68 − Transition Hum 5 – 20% +// 69 − Transition Hum 6 – 10% +// 70 − Transition Ramp Down Long Smooth 1 – 100 to 0% +// 71 − Transition Ramp Down Long Smooth 2 – 100 to 0% +// 72 − Transition Ramp Down Medium Smooth 1 – 100 to 0% +// 73 − Transition Ramp Down Medium Smooth 2 – 100 to 0% +// 74 − Transition Ramp Down Short Smooth 1 – 100 to 0% +// 75 − Transition Ramp Down Short Smooth 2 – 100 to 0% +// 76 − Transition Ramp Down Long Sharp 1 – 100 to 0% +// 77 − Transition Ramp Down Long Sharp 2 – 100 to 0% +// 78 − Transition Ramp Down Medium Sharp 1 – 100 to 0% +// 79 − Transition Ramp Down Medium Sharp 2 – 100 to 0% +// 80 − Transition Ramp Down Short Sharp 1 – 100 to 0% +// 81 − Transition Ramp Down Short Sharp 2 – 100 to 0% +// 82 − Transition Ramp Up Long Smooth 1 – 0 to 100% +// 83 − Transition Ramp Up Long Smooth 2 – 0 to 100% +// 84 − Transition Ramp Up Medium Smooth 1 – 0 to 100% +// 85 − Transition Ramp Up Medium Smooth 2 – 0 to 100% +// 86 − Transition Ramp Up Short Smooth 1 – 0 to 100% +// 87 − Transition Ramp Up Short Smooth 2 – 0 to 100% +// 88 − Transition Ramp Up Long Sharp 1 – 0 to 100% +// 89 − Transition Ramp Up Long Sharp 2 – 0 to 100% +// 90 − Transition Ramp Up Medium Sharp 1 – 0 to 100% +// 91 − Transition Ramp Up Medium Sharp 2 – 0 to 100% +// 92 − Transition Ramp Up Short Sharp 1 – 0 to 100% +// 93 − Transition Ramp Up Short Sharp 2 – 0 to 100% +// 94 − Transition Ramp Down Long Smooth 1 – 50 to 0% +// 95 − Transition Ramp Down Long Smooth 2 – 50 to 0% +// 96 − Transition Ramp Down Medium Smooth 1 – 50 to 0% +// 97 − Transition Ramp Down Medium Smooth 2 – 50 to 0% +// 98 − Transition Ramp Down Short Smooth 1 – 50 to 0% +// 99 − Transition Ramp Down Short Smooth 2 – 50 to 0% +// 100 − Transition Ramp Down Long Sharp 1 – 50 to 0% +// 101 − Transition Ramp Down Long Sharp 2 – 50 to 0% +// 102 − Transition Ramp Down Medium Sharp 1 – 50 to 0% +// 103 − Transition Ramp Down Medium Sharp 2 – 50 to 0% +// 104 − Transition Ramp Down Short Sharp 1 – 50 to 0% +// 105 − Transition Ramp Down Short Sharp 2 – 50 to 0% +// 106 − Transition Ramp Up Long Smooth 1 – 0 to 50% +// 107 − Transition Ramp Up Long Smooth 2 – 0 to 50% +// 108 − Transition Ramp Up Medium Smooth 1 – 0 to 50% +// 109 − Transition Ramp Up Medium Smooth 2 – 0 to 50% +// 110 − Transition Ramp Up Short Smooth 1 – 0 to 50% +// 111 − Transition Ramp Up Short Smooth 2 – 0 to 50% +// 112 − Transition Ramp Up Long Sharp 1 – 0 to 50% +// 113 − Transition Ramp Up Long Sharp 2 – 0 to 50% +// 114 − Transition Ramp Up Medium Sharp 1 – 0 to 50% +// 115 − Transition Ramp Up Medium Sharp 2 – 0 to 50% +// 116 − Transition Ramp Up Short Sharp 1 – 0 to 50% +// 117 − Transition Ramp Up Short Sharp 2 – 0 to 50% +// 118 − Long buzz for programmatic stopping – 100% +// 119 − Smooth Hum 1 (No kick or brake pulse) – 50% +// 120 − Smooth Hum 2 (No kick or brake pulse) – 40% +// 121 − Smooth Hum 3 (No kick or brake pulse) – 30% +// 122 − Smooth Hum 4 (No kick or brake pulse) – 20% +// 123 − Smooth Hum 5 (No kick or brake pulse) – 10% + +/**************************************************************************/ +/*! + @brief The DRV2605 driver class. +*/ +/**************************************************************************/ +void drv2605l_init(); +void writeRegister8(uint8_t reg, uint8_t val); +uint8_t readRegister8(uint8_t reg); +void drv2605l_setWaveform(uint8_t slot, uint8_t w); +void drv2605l_selectLibrary(uint8_t lib); +void drv2605l_go(void); +void drv2605l_stop(void); +void drv2605l_setMode(uint8_t mode); +void drv2605l_setRealtimeValue(uint8_t rtp); +// Select ERM (Eccentric Rotating Mass) or LRA (Linear Resonant Actuator) +// vibration motor The default is ERM, which is more common +void drv2605l_useERM(); +void drv2605l_useLRA(); + +#endif diff --git a/firmware/stm32f4xx/Core/Inc/config.h b/firmware/stm32f4xx/Core/Inc/config.h new file mode 100644 index 0000000..55950ef --- /dev/null +++ b/firmware/stm32f4xx/Core/Inc/config.h @@ -0,0 +1,22 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define DEFAULT_TRIGGER_OFFSET 64 +#define DEFAULT_RESET_THRESHOLD 3 +#define DEFAULT_RAPID_TRIGGER_OFFSET 40 +#define DEFAULT_SCREAMING_VELOCITY_TRIGGER 45 +#define DEFAULT_TAP_TIMEOUT 200 + +#define ADC_CHANNEL_COUNT 5 +#define AMUX_SELECT_PINS_COUNT 4 +#define AMUX_CHANNEL_COUNT 16 + +#define MATRIX_ROWS 5 +#define MATRIX_COLS 15 + +extern const struct user_config keyboard_default_user_config; +extern const uint8_t channels_by_row_col[MATRIX_ROWS][MATRIX_COLS][2]; + +#endif /* __CONFIG_H */ diff --git a/firmware/stm32f4xx/Core/Inc/hid.h b/firmware/stm32f4xx/Core/Inc/hid.h new file mode 100644 index 0000000..201dae5 --- /dev/null +++ b/firmware/stm32f4xx/Core/Inc/hid.h @@ -0,0 +1,22 @@ +#ifndef __HID_H +#define __HID_H + +#include "keyboard.h" +#include + +#define VENDOR_REQUEST_KEYS 0xfe +#define VENDOR_REQUEST_CONFIG 0xff +#define VENDOR_REQUEST_RESET_CONFIG 0xfd +#define VENDOR_REQUEST_DFU_MODE 0xfc +#define VENDOR_REQUEST_CYCLE_DURATION 0xfb + +#define VENDOR_VALUE_GET_LENGTH 0x00 +#define VENDOR_VALUE_GET 0x01 +#define VENDOR_VALUE_SET 0x02 + +void hid_init(); +void hid_task(); +void hid_press_key(struct key *key, uint8_t layer); +void hid_release_key(struct key *key, uint8_t layer); + +#endif /* __HID_H */ diff --git a/firmware/stm32f4xx/Core/Inc/keyboard.h b/firmware/stm32f4xx/Core/Inc/keyboard.h new file mode 100644 index 0000000..3bfd07d --- /dev/null +++ b/firmware/stm32f4xx/Core/Inc/keyboard.h @@ -0,0 +1,109 @@ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __KEYBOARD_H +#define __KEYBOARD_H + +#include "config.h" +#include + +#define CALIBRATION_CYCLES 20 + +#define IDLE_VALUE_APPROX 1800 +#define MAX_DISTANCE_APPROX 500 +#define IDLE_VALUE_OFFSET 10 +#define MAX_DISTANCE_OFFSET 60 +#define IDLE_CYCLES_UNTIL_SLEEP 15 + +#define XXXX 0xff +#define ____ 0x00 + +#define SPECIAL(X) (0b1000000000000000 | X) + +struct __attribute__((__packed__)) calibration { + uint16_t cycles_count; + uint16_t idle_value; + uint16_t max_distance; +}; + +enum direction { + GOING_UP, + GOING_DOWN, +}; + +struct __attribute__((__packed__)) state { + uint16_t value; + uint16_t distance; + uint8_t distance_8bits; + float filtered_distance; + int8_t velocity; + uint8_t filtered_distance_8bits; +}; + +enum actuation_status { + STATUS_MIGHT_BE_TAP, + STATUS_TAP, + STATUS_TRIGGERED, + STATUS_RESET, + STATUS_RAPID_TRIGGER_RESET +}; + +struct __attribute__((__packed__)) actuation { + enum direction direction; + uint8_t direction_changed_point; + enum actuation_status status; + uint8_t reset_offset; + uint8_t trigger_offset; + uint8_t rapid_trigger_offset; + uint8_t is_continuous_rapid_trigger_enabled; + uint32_t triggered_at; +}; + +enum key_type { + KEY_TYPE_EMPTY, + KEY_TYPE_NORMAL, + KEY_TYPE_MODIFIER, + KEY_TYPE_CONSUMER_CONTROL, +}; + +struct __attribute__((__packed__)) layer { + enum key_type type; + uint16_t value; +}; + +enum { + _BASE_LAYER, + _TAP_LAYER, + LAYERS_COUNT +}; + +struct __attribute__((__packed__)) key { + uint8_t is_enabled; + uint8_t row; + uint8_t column; + uint8_t idle_counter; + uint8_t is_idle; + struct layer layers[LAYERS_COUNT]; + struct calibration calibration; + struct state state; + struct actuation actuation; +}; + +struct user_config { + uint8_t trigger_offset; + uint8_t reset_threshold; + uint8_t rapid_trigger_offset; + uint8_t screaming_velocity_trigger; + uint16_t tap_timeout; + uint16_t keymaps[LAYERS_COUNT][MATRIX_ROWS][MATRIX_COLS]; +}; + +void keyboard_task(); +void keyboard_init_keys(); +extern void keyboard_read_config(); +extern uint8_t keyboard_write_config(uint8_t *buffer, uint16_t offset, uint16_t size); +extern void keyboard_select_amux(uint8_t amux_channel); +extern void keyboard_select_adc(uint8_t adc_channel); +extern uint16_t keyboard_read_adc(); +extern void keyboard_close_adc(); +extern uint32_t keyboard_get_time(); + +#endif /* __KEYBOARD_H */ diff --git a/firmware/Core/Inc/main.h b/firmware/stm32f4xx/Core/Inc/main.h similarity index 100% rename from firmware/Core/Inc/main.h rename to firmware/stm32f4xx/Core/Inc/main.h diff --git a/firmware/Core/Inc/stm32f4xx_hal_conf.h b/firmware/stm32f4xx/Core/Inc/stm32f4xx_hal_conf.h similarity index 100% rename from firmware/Core/Inc/stm32f4xx_hal_conf.h rename to firmware/stm32f4xx/Core/Inc/stm32f4xx_hal_conf.h diff --git a/firmware/Core/Inc/stm32f4xx_it.h b/firmware/stm32f4xx/Core/Inc/stm32f4xx_it.h similarity index 100% rename from firmware/Core/Inc/stm32f4xx_it.h rename to firmware/stm32f4xx/Core/Inc/stm32f4xx_it.h diff --git a/firmware/stm32f4xx/Core/Inc/tusb_config.h b/firmware/stm32f4xx/Core/Inc/tusb_config.h new file mode 100644 index 0000000..3e450af --- /dev/null +++ b/firmware/stm32f4xx/Core/Inc/tusb_config.h @@ -0,0 +1,109 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef _TUSB_CONFIG_H_ +#define _TUSB_CONFIG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------+ +// Board Specific Configuration +//--------------------------------------------------------------------+ + +// RHPort number used for device can be defined by board.mk, default to port 0 +#ifndef BOARD_TUD_RHPORT +#define BOARD_TUD_RHPORT 0 +#endif + +// RHPort max operational speed can defined by board.mk +#ifndef BOARD_TUD_MAX_SPEED +#define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED +#endif + +//-------------------------------------------------------------------- +// COMMON CONFIGURATION +//-------------------------------------------------------------------- + +#define CFG_TUSB_MCU OPT_MCU_STM32F4 + +#ifndef CFG_TUSB_OS +#define CFG_TUSB_OS OPT_OS_NONE +#endif + +#ifndef CFG_TUSB_DEBUG +#define CFG_TUSB_DEBUG 0 +#endif + +// Enable Device stack +#define CFG_TUD_ENABLED 1 + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED + +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUSB_MEM_SECTION +#define CFG_TUSB_MEM_SECTION +#endif + +#ifndef CFG_TUSB_MEM_ALIGN +#define CFG_TUSB_MEM_ALIGN __attribute__((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// DEVICE CONFIGURATION +//-------------------------------------------------------------------- + +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 +#endif + +//------------- CLASS -------------// +#define CFG_TUD_HID 1 +#define CFG_TUD_CDC 0 +#define CFG_TUD_MSC 0 +#define CFG_TUD_MIDI 0 +#define CFG_TUD_VENDOR 1 + +// HID buffer size Should be sufficient to hold ID (if any) + Data +#define CFG_TUD_HID_EP_BUFSIZE 16 + +// Vendor FIFO size of TX and RX +// If not configured vendor endpoints will not be buffered +#define CFG_TUD_VENDOR_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_VENDOR_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) + +#ifdef __cplusplus +} +#endif + +#endif /* _TUSB_CONFIG_H_ */ diff --git a/firmware/stm32f4xx/Core/Inc/usb_descriptors.h b/firmware/stm32f4xx/Core/Inc/usb_descriptors.h new file mode 100644 index 0000000..bd4536f --- /dev/null +++ b/firmware/stm32f4xx/Core/Inc/usb_descriptors.h @@ -0,0 +1,44 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef USB_DESCRIPTORS_H_ +#define USB_DESCRIPTORS_H_ + +enum { + REPORT_ID_KEYBOARD = 1, + REPORT_ID_CONSUMER_CONTROL, +}; + +enum { + VENDOR_REQUEST_WEBUSB = 1, + VENDOR_REQUEST_MICROSOFT = 2 +}; + +enum { + ITF_NUM_KEYBOARD = 0, + ITF_NUM_VENDOR, + ITF_NUM_TOTAL +}; + +#endif /* USB_DESCRIPTORS_H_ */ diff --git a/firmware/stm32f4xx/Core/Src/config.c b/firmware/stm32f4xx/Core/Src/config.c new file mode 100644 index 0000000..2b99db6 --- /dev/null +++ b/firmware/stm32f4xx/Core/Src/config.c @@ -0,0 +1,39 @@ +#include "config.h" +#include "DRV2605L.h" +#include "keyboard.h" +#include "stdlib.h" +#include + +const struct user_config keyboard_default_user_config = { + .trigger_offset = DEFAULT_TRIGGER_OFFSET, + .reset_threshold = DEFAULT_RESET_THRESHOLD, + .rapid_trigger_offset = DEFAULT_RAPID_TRIGGER_OFFSET, + .screaming_velocity_trigger = DEFAULT_SCREAMING_VELOCITY_TRIGGER, + .tap_timeout = DEFAULT_TAP_TIMEOUT, + .keymaps = { + // clang-format off + [_BASE_LAYER] = { + {HID_KEY_ESCAPE, HID_KEY_GRAVE, HID_KEY_1, HID_KEY_2, HID_KEY_3, HID_KEY_4, HID_KEY_5, HID_KEY_6, HID_KEY_7, HID_KEY_8, HID_KEY_9, HID_KEY_0, HID_KEY_MINUS, HID_KEY_EQUAL, HID_KEY_BACKSPACE}, + {SPECIAL(HID_USAGE_CONSUMER_VOLUME_INCREMENT), HID_KEY_TAB, HID_KEY_Q, HID_KEY_W, HID_KEY_E, HID_KEY_R, HID_KEY_T, HID_KEY_Y, HID_KEY_U, HID_KEY_I, HID_KEY_O, HID_KEY_P, HID_KEY_BRACKET_LEFT, HID_KEY_BRACKET_RIGHT, HID_KEY_ENTER}, + {SPECIAL(HID_USAGE_CONSUMER_VOLUME_DECREMENT), HID_KEY_CAPS_LOCK, HID_KEY_A, HID_KEY_S, HID_KEY_D, HID_KEY_F, HID_KEY_G, HID_KEY_H, HID_KEY_J, HID_KEY_K, HID_KEY_L, HID_KEY_SEMICOLON, HID_KEY_APOSTROPHE, HID_KEY_EUROPE_1, XXXX}, + {XXXX, HID_KEY_SHIFT_LEFT, HID_KEY_EUROPE_2, HID_KEY_Z, HID_KEY_X, HID_KEY_C, HID_KEY_V, HID_KEY_B, HID_KEY_N, HID_KEY_M, HID_KEY_COMMA, HID_KEY_PERIOD, HID_KEY_SLASH, HID_KEY_SHIFT_RIGHT, XXXX}, + {XXXX, HID_KEY_CONTROL_LEFT, HID_KEY_ALT_LEFT, HID_KEY_GUI_LEFT, XXXX, HID_KEY_SPACE, XXXX, HID_KEY_SPACE, XXXX, HID_KEY_GUI_RIGHT, HID_KEY_ALT_RIGHT, XXXX, HID_KEY_ARROW_LEFT, SPECIAL(HID_USAGE_CONSUMER_PLAY_PAUSE), HID_KEY_ARROW_RIGHT}, + }, + [_TAP_LAYER] = { + {____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____}, + {____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____}, + {____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, XXXX}, + {XXXX, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, HID_KEY_ARROW_UP, XXXX}, + {XXXX, ____, ____, ____, XXXX, ____, XXXX, ____, XXXX, ____, ____, XXXX, ____, HID_KEY_ARROW_DOWN, ____}, + }, + // clang-format on + }}; + +// {adc_channel, amux_channel} +const uint8_t channels_by_row_col[MATRIX_ROWS][MATRIX_COLS][2] = { + {{0, 10}, {0, 8}, {0, 7}, {0, 5}, {1, 9}, {1, 8}, {1, 6}, {2, 10}, {2, 9}, {2, 7}, {2, 6}, {3, 9}, {3, 8}, {3, 6}, {4, 2}}, + {{0, 11}, {0, 9}, {0, 6}, {0, 4}, {1, 10}, {1, 7}, {1, 5}, {2, 11}, {2, 8}, {2, 5}, {2, 4}, {3, 10}, {3, 7}, {3, 5}, {4, 1}}, + {{0, 12}, {0, 14}, {0, 2}, {1, 11}, {1, 14}, {1, 1}, {1, 4}, {2, 12}, {2, 15}, {2, 3}, {3, 11}, {3, 14}, {3, 1}, {3, 4}, {XXXX, XXXX}}, + {{XXXX, XXXX}, {0, 13}, {0, 0}, {0, 3}, {1, 13}, {1, 15}, {1, 2}, {1, 3}, {2, 14}, {2, 0}, {2, 2}, {3, 12}, {3, 15}, {3, 3}, {XXXX, XXXX}}, + {{XXXX, XXXX}, {0, 15}, {0, 1}, {1, 12}, {XXXX, XXXX}, {1, 0}, {XXXX, XXXX}, {2, 13}, {XXXX, XXXX}, {2, 1}, {3, 13}, {XXXX, XXXX}, {3, 0}, {3, 2}, {4, 0}}, +}; \ No newline at end of file diff --git a/firmware/stm32f4xx/Core/Src/hid.c b/firmware/stm32f4xx/Core/Src/hid.c new file mode 100644 index 0000000..fc01828 --- /dev/null +++ b/firmware/stm32f4xx/Core/Src/hid.c @@ -0,0 +1,341 @@ +#include "tusb.h" +#include "usb_descriptors.h" +#include +#include +#include + +extern uint8_t const desc_ms_os_20[]; +extern struct key keyboard_keys[ADC_CHANNEL_COUNT][AMUX_CHANNEL_COUNT]; +extern struct user_config keyboard_user_config; +extern uint32_t keyboard_last_cycle_duration; + +static uint8_t should_send_consumer_report = 0; +static uint8_t should_send_keyboard_report = 0; + +static uint8_t modifiers = 0; +static uint8_t keycodes[6] = {0}; +// static uint8_t is_screaming = 0; +static uint8_t consumer_report = 0; + +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t usb_vendor_control_buffer[400]; + +void hid_init() { + tud_init(BOARD_TUD_RHPORT); +} + +void hid_task() { + tud_task(); + + if ((should_send_consumer_report || should_send_keyboard_report) && tud_hid_ready()) { + if (tud_suspended()) { + tud_remote_wakeup(); + } else { + if (should_send_consumer_report) { + should_send_consumer_report = 0; + tud_hid_report(REPORT_ID_CONSUMER_CONTROL, &consumer_report, 2); + } else if (should_send_keyboard_report) { + should_send_keyboard_report = 0; + tud_hid_keyboard_report(REPORT_ID_KEYBOARD, modifiers, keycodes); + } + } + } +} + +void hid_press_key(struct key *key, uint8_t layer) { + switch (key->layers[layer].type) { + case KEY_TYPE_MODIFIER: + modifiers |= key->layers[layer].value; + should_send_keyboard_report = 1; + break; + + case KEY_TYPE_NORMAL: + for (uint8_t i = 0; i < 6; i++) { + if (keycodes[i] == 0) { + keycodes[i] = key->layers[layer].value; + // if the key is violently pressed, automatically add the MAJ modifier :) + // if (is_screaming) { + // is_screaming = 0; + // modifiers &= ~get_bitmask_for_modifier(HID_KEY_SHIFT_LEFT); + // } else if (i == 0 && key->state.velocity > keyboard_user_config.screaming_velocity_trigger) { + // is_screaming = 1; + // modifiers |= get_bitmask_for_modifier(HID_KEY_SHIFT_LEFT); + // } + should_send_keyboard_report = 1; + break; + } + } + break; + + case KEY_TYPE_CONSUMER_CONTROL: + consumer_report = key->layers[layer].value; + should_send_consumer_report = 1; + break; + + default: + break; + } +} + +void hid_release_key(struct key *key, uint8_t layer) { + switch (key->layers[layer].type) { + case KEY_TYPE_MODIFIER: + modifiers &= ~key->layers[layer].value; + should_send_keyboard_report = 1; + break; + + case KEY_TYPE_NORMAL: + for (uint8_t i = 0; i < 6; i++) { + if (keycodes[i] == key->layers[layer].value) { + keycodes[i] = 0; + // if (is_screaming) { + // is_screaming = 0; + // modifiers &= ~get_bitmask_for_modifier(HID_KEY_SHIFT_LEFT); + // } + should_send_keyboard_report = 1; + break; + } + } + break; + + case KEY_TYPE_CONSUMER_CONTROL: + consumer_report = 0; + should_send_consumer_report = 1; + break; + + default: + break; + } +} + +// Invoked when received SET_PROTOCOL request +// protocol is either HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1) +void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol) { + (void)instance; + (void)protocol; + + // nothing to do since we use the same compatible boot report for both Boot and Report mode. + // TODO set a indicator for user +} + +// Invoked when sent REPORT successfully to host +// Application can use this to send the next report +// Note: For composite reports, report[0] is report ID +void tud_hid_report_complete_cb(uint8_t instance, uint8_t const *report, uint16_t len) { + (void)instance; + (void)report; + (void)len; +} + +// Invoked when received GET_REPORT control request +// Application must fill buffer report's content and return its length. +// Return zero will cause the stack to STALL request +uint16_t tud_hid_get_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t *buffer, uint16_t reqlen) { + // TODO not Implemented + (void)instance; + (void)report_id; + (void)report_type; + (void)buffer; + (void)reqlen; + + return 0; +} + +// Invoked when received SET_REPORT control request or +// received data on OUT endpoint ( Report ID = 0, Type = 0 ) +void tud_hid_set_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t const *buffer, uint16_t bufsize) { + (void)report_id; + // if (instance == 1 && report_id == 0) { + // keyboard_write_config(buffer, bufsize); + + // keyboard_init_keys(); + // } +} + +// // Invoked when cdc when line state changed e.g connected/disconnected +// void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) { +// (void)itf; + +// // connected +// if (dtr && rts) { +// // print initial message when connected +// tud_cdc_write(&keyboard_user_config, 3); +// tud_cdc_write_str('\r\n'); +// tud_cdc_write_flush(); +// } +// } + +// // Invoked when CDC interface received data from host +// void tud_cdc_rx_cb(uint8_t itf) { +// (void)itf; +// } + +// Invoked when a control transfer occurred on an interface of this class +// Driver response accordingly to the request and the transfer stage (setup/data/ack) +// return false to stall control endpoint (e.g unsupported request) +bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) { + switch (request->bmRequestType_bit.type) { + case TUSB_REQ_TYPE_VENDOR: { + switch (request->bRequest) { + + case VENDOR_REQUEST_CONFIG: { + switch (request->wValue) { + case VENDOR_VALUE_GET_LENGTH: { + if (stage == CONTROL_STAGE_SETUP) { + uint16_t size = sizeof(keyboard_user_config); + return tud_control_xfer(rhport, request, &size, request->wLength); + } + + break; + } + + case VENDOR_VALUE_GET: { + if (stage == CONTROL_STAGE_SETUP) { + return tud_control_xfer(rhport, request, &keyboard_user_config, request->wLength); + } + + break; + } + + case VENDOR_VALUE_SET: { + if (stage == CONTROL_STAGE_SETUP) { + return tud_control_xfer(rhport, request, usb_vendor_control_buffer, request->wLength); + } else if (stage == CONTROL_STAGE_DATA) { + if (!keyboard_write_config(&usb_vendor_control_buffer, 0, request->wLength)) { + return false; + } + keyboard_read_config(); + keyboard_init_keys(); + } + + break; + } + + default: + break; + } + } + + case VENDOR_REQUEST_RESET_CONFIG: { + if (request->wValue == VENDOR_VALUE_SET) { + if (stage == CONTROL_STAGE_SETUP) { + if (!keyboard_write_config(&keyboard_default_user_config, 0, sizeof keyboard_default_user_config)) { + return false; + } + keyboard_read_config(); + keyboard_init_keys(); + return tud_control_status(rhport, request); + } + + break; + } + } + + case VENDOR_REQUEST_DFU_MODE: { + if (request->wValue == VENDOR_VALUE_SET) { + if (stage == CONTROL_STAGE_SETUP) { + return tud_control_status(rhport, request); + } + + break; + } + } + + case VENDOR_REQUEST_KEYS: { + switch (request->wValue) { + case VENDOR_VALUE_GET_LENGTH: { + if (stage == CONTROL_STAGE_SETUP) { + uint16_t size = sizeof(keyboard_keys); + return tud_control_xfer(rhport, request, &size, request->wLength); + } + + break; + } + + case VENDOR_VALUE_GET: { + if (stage == CONTROL_STAGE_SETUP) { + return tud_control_xfer(rhport, request, &keyboard_keys, request->wLength); + } + + break; + } + + default: + break; + } + } + + case VENDOR_REQUEST_CYCLE_DURATION: { + switch (request->wValue) { + case VENDOR_VALUE_GET_LENGTH: { + if (stage == CONTROL_STAGE_SETUP) { + uint16_t size = sizeof(keyboard_last_cycle_duration); + return tud_control_xfer(rhport, request, &size, request->wLength); + } + + break; + } + + case VENDOR_VALUE_GET: { + if (stage == CONTROL_STAGE_SETUP) { + return tud_control_xfer(rhport, request, &keyboard_last_cycle_duration, request->wLength); + } + + break; + } + + default: + break; + } + } + + case VENDOR_REQUEST_WEBUSB: { + if (stage == CONTROL_STAGE_SETUP) { + return tud_control_status(rhport, request); + } + + break; + } + + case VENDOR_REQUEST_MICROSOFT: { + if (stage == CONTROL_STAGE_SETUP) { + if (request->wIndex == 7) { + // Get Microsoft OS 2.0 compatible descriptor + uint16_t total_len; + memcpy(&total_len, desc_ms_os_20 + 8, 2); + + return tud_control_xfer(rhport, request, (void *)(uintptr_t)desc_ms_os_20, total_len); + } + + return false; + } + + break; + } + + default: + break; + } + } + + case TUSB_REQ_TYPE_CLASS: { + if (stage == CONTROL_STAGE_SETUP) { + if (request->bRequest == 0x22) { + // response with status OK + return tud_control_status(rhport, request); + } + + return false; + } + + break; + } + + default: + break; + } + + if (stage != CONTROL_STAGE_SETUP) { + return true; + } + return false; +} \ No newline at end of file diff --git a/firmware/stm32f4xx/Core/Src/keyboard.c b/firmware/stm32f4xx/Core/Src/keyboard.c new file mode 100644 index 0000000..e798ad5 --- /dev/null +++ b/firmware/stm32f4xx/Core/Src/keyboard.c @@ -0,0 +1,313 @@ +#include "keyboard.h" +#include "DRV2605L.h" +#include "hid.h" +#include +#include + +struct key keyboard_keys[ADC_CHANNEL_COUNT][AMUX_CHANNEL_COUNT] = {0}; +struct user_config keyboard_user_config = {0}; + +uint32_t keyboard_last_cycle_duration = 0; + +static uint8_t key_triggered = 0; + +uint8_t get_bitmask_for_modifier(uint8_t keycode) { + switch (keycode) { + case HID_KEY_CONTROL_LEFT: + return 0b00000001; + case HID_KEY_SHIFT_LEFT: + return 0b00000010; + case HID_KEY_ALT_LEFT: + return 0b00000100; + case HID_KEY_GUI_LEFT: + return 0b00001000; + case HID_KEY_CONTROL_RIGHT: + return 0b00010000; + case HID_KEY_SHIFT_RIGHT: + return 0b00100000; + case HID_KEY_ALT_RIGHT: + return 0b01000000; + case HID_KEY_GUI_RIGHT: + return 0b10000000; + default: + return 0b00000000; + } +} + +uint16_t get_usage_consumer_control(uint16_t value) { + if (value > 0xFF) { + return value & 0b0111111111111111; + } else { + return 0; + } +} + +void init_key(uint8_t adc_channel, uint8_t amux_channel, uint8_t row, uint8_t column) { + struct key *key = &keyboard_keys[adc_channel][amux_channel]; + + key->is_enabled = 1; + key->is_idle = 0; + key->row = row; + key->column = column; + + key->calibration.cycles_count = 0; + key->calibration.idle_value = IDLE_VALUE_APPROX; + key->calibration.max_distance = MAX_DISTANCE_APPROX; + + key->actuation.status = STATUS_RESET; + key->actuation.trigger_offset = keyboard_user_config.trigger_offset; + key->actuation.reset_offset = keyboard_user_config.trigger_offset - keyboard_user_config.reset_threshold; + key->actuation.rapid_trigger_offset = keyboard_user_config.rapid_trigger_offset; + key->actuation.is_continuous_rapid_trigger_enabled = 0; + + for (uint8_t i = 0; i < LAYERS_COUNT; i++) { + if (keyboard_user_config.keymaps[i][row][column] != ____) { + uint16_t usage_consumer_control = get_usage_consumer_control(keyboard_user_config.keymaps[i][row][column]); + if (usage_consumer_control) { + key->layers[i].type = KEY_TYPE_CONSUMER_CONTROL; + key->layers[i].value = usage_consumer_control; + } else { + uint8_t bitmask = get_bitmask_for_modifier(keyboard_user_config.keymaps[i][row][column]); + if (bitmask) { + key->layers[i].type = KEY_TYPE_MODIFIER; + key->layers[i].value = bitmask; + } else { + key->layers[i].type = KEY_TYPE_NORMAL; + key->layers[i].value = keyboard_user_config.keymaps[i][row][column]; + } + } + } + } +} + +uint8_t update_key_state(struct key *key) { + struct state state; + + // Get a reading + state.value = keyboard_read_adc(); + + if (key->calibration.cycles_count < CALIBRATION_CYCLES) { + // Calibrate idle value + float delta = 0.6; + key->calibration.idle_value = (1 - delta) * state.value + delta * key->calibration.idle_value; + key->calibration.cycles_count++; + + return 0; + } + + // Calibrate idle value + if (state.value > key->calibration.idle_value) { + // opti possible sur float + float delta = 0.8; + key->calibration.idle_value = (1 - delta) * state.value + delta * key->calibration.idle_value; + state.value = key->calibration.idle_value; + } + + // Do nothing if key is idle + if (key->state.distance == 0 && state.value >= key->calibration.idle_value - IDLE_VALUE_OFFSET) { + if (key->idle_counter >= IDLE_CYCLES_UNTIL_SLEEP) { + key->is_idle = 1; + return 0; + } + key->idle_counter++; + } + + // Get distance from top + if (state.value >= key->calibration.idle_value - IDLE_VALUE_OFFSET) { + state.distance = 0; + key->actuation.direction_changed_point = 0; + } else { + state.distance = key->calibration.idle_value - IDLE_VALUE_OFFSET - state.value; + key->is_idle = 0; + key->idle_counter = 0; + } + + // Calibrate max distance value + if (state.distance > key->calibration.max_distance) { + key->calibration.max_distance = state.distance; + } + + // Limit max distance + if (state.distance >= key->calibration.max_distance - MAX_DISTANCE_OFFSET) { + state.distance = key->calibration.max_distance; + } + + // Map distance in percentages + state.distance_8bits = (state.distance * 0xff) / key->calibration.max_distance; + + float delta = 0.8; + state.filtered_distance = (1 - delta) * state.distance_8bits + delta * key->state.filtered_distance; + state.filtered_distance_8bits = state.filtered_distance; + + // Update velocity + state.velocity = state.filtered_distance_8bits - key->state.filtered_distance_8bits; + + // Update direction + if (key->state.velocity > 0 && state.velocity > 0 && key->actuation.direction != GOING_DOWN) { + key->actuation.direction = GOING_DOWN; + if (key->actuation.direction_changed_point != 0) { + key->actuation.direction_changed_point = key->state.filtered_distance_8bits; + } + } else if (key->state.velocity < 0 && state.velocity < 0 && key->actuation.direction != GOING_UP) { + key->actuation.direction = GOING_UP; + if (key->actuation.direction_changed_point != 255) { + key->actuation.direction_changed_point = key->state.filtered_distance_8bits; + } + } + + key->state = state; + return 1; +} + +void update_key_actuation(struct key *key) { + /** + * https://www.youtube.com/watch?v=_Sl-T6iQr8U&t + * + * ----- |--------| - + * | | | | + * is_before_reset_offset | | | | + * | | | | Continuous rapid trigger domain (deactivated when full_reset) + * ----- | ------ | <- reset_offset | + * | | | | + * ----- | ------ | <- trigger_offset - + * | | | | + * | | | | + * is_after_trigger_offset | | | | Rapid trigger domain + * | | | | + * | | | | + * ----- |--------| - + * + */ + + // if rapid trigger enable, move trigger and reset offsets according to the distance taht began the trigger + + uint32_t now = keyboard_get_time(); + uint8_t is_after_trigger_offset = key->state.distance_8bits > key->actuation.trigger_offset; + uint8_t is_before_reset_offset = key->state.distance_8bits < key->actuation.reset_offset; + uint8_t has_rapid_trigger = key->actuation.rapid_trigger_offset != 0; + uint8_t is_after_rapid_trigger_offset = key->state.distance_8bits > key->actuation.direction_changed_point - key->actuation.rapid_trigger_offset + keyboard_user_config.reset_threshold; + uint8_t is_before_rapid_reset_offset = key->state.distance_8bits < key->actuation.direction_changed_point - key->actuation.rapid_trigger_offset; + + switch (key->actuation.status) { + + case STATUS_RESET: + // if reset, can be triggered or tap + if (is_after_trigger_offset) { + if (key->layers[_TAP_LAYER].value) { + key->actuation.status = STATUS_MIGHT_BE_TAP; + // key_triggered = 1; + } else { + key->actuation.status = STATUS_TRIGGERED; + key_triggered = 1; + hid_press_key(key, _BASE_LAYER); + } + key->actuation.triggered_at = now; + } + break; + + case STATUS_RAPID_TRIGGER_RESET: + if (!has_rapid_trigger) { + key->actuation.status = STATUS_RESET; + break; + } + // if reset, can be triggered or tap + if (is_after_trigger_offset && key->actuation.direction == GOING_DOWN && is_after_rapid_trigger_offset) { + if (key->layers[_TAP_LAYER].value) { + key->actuation.status = STATUS_MIGHT_BE_TAP; + key_triggered = 1; + } else { + key->actuation.status = STATUS_TRIGGERED; + key_triggered = 1; + hid_press_key(key, _BASE_LAYER); + } + key->actuation.triggered_at = now; + } else if (is_before_reset_offset) { + key->actuation.status = STATUS_RESET; + } + break; + + case STATUS_TAP: + // if tap, can be reset + key->actuation.status = STATUS_RESET; + hid_release_key(key, _TAP_LAYER); + break; + + case STATUS_TRIGGERED: + // if triggered, can be reset + if (is_before_reset_offset) { + key->actuation.status = STATUS_RESET; + hid_release_key(key, _BASE_LAYER); + } else if (has_rapid_trigger && key->actuation.direction == GOING_UP && is_before_rapid_reset_offset) { + key->actuation.status = STATUS_RAPID_TRIGGER_RESET; + hid_release_key(key, _BASE_LAYER); + } + break; + + default: + break; + } +} + +void update_key(struct key *key) { + if (!update_key_state(key)) { + return; + } + + update_key_actuation(key); +} + +void keyboard_init_keys() { + keyboard_read_config(); + + for (uint8_t row = 0; row < MATRIX_ROWS; row++) { + for (uint8_t col = 0; col < MATRIX_COLS; col++) { + if (channels_by_row_col[row][col][0] != XXXX) { + init_key(channels_by_row_col[row][col][0], channels_by_row_col[row][col][1], row, col); + } + } + } +} + +void keyboard_task() { + uint32_t started_at = keyboard_get_time(); + key_triggered = 0; + + for (uint8_t amux_channel = 0; amux_channel < AMUX_CHANNEL_COUNT; amux_channel++) { + keyboard_select_amux(amux_channel); + + for (uint8_t adc_channel = 0; adc_channel < ADC_CHANNEL_COUNT; adc_channel++) { + if (keyboard_keys[adc_channel][amux_channel].is_enabled == 0) { + continue; + } + keyboard_select_adc(adc_channel); + + update_key(&keyboard_keys[adc_channel][amux_channel]); + + keyboard_close_adc(); + } + } + + // If a key might be tap and a non tap key has been triggered, then the might be tap key is a normal trigger + for (uint8_t amux_channel = 0; amux_channel < AMUX_CHANNEL_COUNT; amux_channel++) { + for (uint8_t adc_channel = 0; adc_channel < ADC_CHANNEL_COUNT; adc_channel++) { + if (keyboard_keys[adc_channel][amux_channel].is_enabled == 0 || keyboard_keys[adc_channel][amux_channel].actuation.status != STATUS_MIGHT_BE_TAP) { + continue; + } + + struct key *key = &keyboard_keys[adc_channel][amux_channel]; + uint8_t is_before_reset_offset = key->state.distance_8bits < key->actuation.reset_offset; + uint8_t is_before_timeout = keyboard_get_time() - key->actuation.triggered_at <= keyboard_user_config.tap_timeout; + + // if might be tap, can be tap or triggered + if (is_before_reset_offset && is_before_timeout) { + key->actuation.status = STATUS_TAP; + hid_press_key(key, _TAP_LAYER); + } else if (!is_before_timeout || key_triggered) { + key->actuation.status = STATUS_TRIGGERED; + hid_press_key(key, _BASE_LAYER); + } + } + } + + keyboard_last_cycle_duration = keyboard_get_time() - started_at; +} diff --git a/firmware/Core/Src/main.c b/firmware/stm32f4xx/Core/Src/main.c similarity index 100% rename from firmware/Core/Src/main.c rename to firmware/stm32f4xx/Core/Src/main.c diff --git a/firmware/Core/Src/stm32f4xx_hal_msp.c b/firmware/stm32f4xx/Core/Src/stm32f4xx_hal_msp.c similarity index 100% rename from firmware/Core/Src/stm32f4xx_hal_msp.c rename to firmware/stm32f4xx/Core/Src/stm32f4xx_hal_msp.c diff --git a/firmware/Core/Src/stm32f4xx_it.c b/firmware/stm32f4xx/Core/Src/stm32f4xx_it.c similarity index 100% rename from firmware/Core/Src/stm32f4xx_it.c rename to firmware/stm32f4xx/Core/Src/stm32f4xx_it.c diff --git a/firmware/Core/Src/syscalls.c b/firmware/stm32f4xx/Core/Src/syscalls.c similarity index 100% rename from firmware/Core/Src/syscalls.c rename to firmware/stm32f4xx/Core/Src/syscalls.c diff --git a/firmware/Core/Src/sysmem.c b/firmware/stm32f4xx/Core/Src/sysmem.c similarity index 100% rename from firmware/Core/Src/sysmem.c rename to firmware/stm32f4xx/Core/Src/sysmem.c diff --git a/firmware/Core/Src/system_stm32f4xx.c b/firmware/stm32f4xx/Core/Src/system_stm32f4xx.c similarity index 100% rename from firmware/Core/Src/system_stm32f4xx.c rename to firmware/stm32f4xx/Core/Src/system_stm32f4xx.c diff --git a/firmware/stm32f4xx/Core/Src/usb_descriptors.c b/firmware/stm32f4xx/Core/Src/usb_descriptors.c new file mode 100644 index 0000000..0ab79f9 --- /dev/null +++ b/firmware/stm32f4xx/Core/Src/usb_descriptors.c @@ -0,0 +1,280 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "usb_descriptors.h" +#include "tusb.h" + +/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug. + * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC. + * + * Auto ProductID layout's Bitmap: + * [MSB] HID | MSC | CDC [LSB] + */ +#define _PID_MAP(itf, n) ((CFG_TUD_##itf) << (n)) +#define USB_PID (0x5000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ + _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4)) + +//--------------------------------------------------------------------+ +// Device Descriptors +//--------------------------------------------------------------------+ +tusb_desc_device_t const desc_device = + { + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = 0x0210, // at least 2.1 or 3.x for BOS & webUSB + + // Use Interface Association Descriptor (IAD) for CDC + // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + + .idVendor = 0xCafe, + .idProduct = USB_PID + 11, + .bcdDevice = 0x0100, + + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, + + .bNumConfigurations = 0x01, +}; + +// Invoked when received GET DEVICE DESCRIPTOR +// Application return pointer to descriptor +uint8_t const *tud_descriptor_device_cb(void) { + return (uint8_t const *)&desc_device; +} + +//--------------------------------------------------------------------+ +// HID Report Descriptor +//--------------------------------------------------------------------+ + +uint8_t const desc_hid_keyboard_report[] = + { + TUD_HID_REPORT_DESC_KEYBOARD(HID_REPORT_ID(REPORT_ID_KEYBOARD)), + TUD_HID_REPORT_DESC_CONSUMER(HID_REPORT_ID(REPORT_ID_CONSUMER_CONTROL)), +}; + +// Invoked when received GET HID REPORT DESCRIPTOR +// Application return pointer to descriptor +// Descriptor contents must exist long enough for transfer to complete +uint8_t const *tud_hid_descriptor_report_cb(uint8_t instance) { + if (instance == ITF_NUM_KEYBOARD) { + return desc_hid_keyboard_report; + } + + return NULL; +} + +//--------------------------------------------------------------------+ +// Configuration Descriptor +//--------------------------------------------------------------------+ + +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_HID_DESC_LEN + TUD_VENDOR_DESC_LEN) + +#define EPNUM_KEYBOARD 1 +#define EPNUM_VENDOR_IN 2 +#define EPNUM_VENDOR_OUT 2 + +uint8_t const desc_configuration[] = + { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + + // Interface number, string index, protocol, report descriptor len, EP In address, size & polling interval + TUD_HID_DESCRIPTOR(ITF_NUM_KEYBOARD, 6, HID_ITF_PROTOCOL_KEYBOARD, sizeof(desc_hid_keyboard_report), 0x80 | EPNUM_KEYBOARD, CFG_TUD_HID_EP_BUFSIZE, 10), + + // Interface number, string index, EP Out & IN address, EP size + TUD_VENDOR_DESCRIPTOR(ITF_NUM_VENDOR, 5, EPNUM_VENDOR_OUT, 0x80 | EPNUM_VENDOR_IN, TUD_OPT_HIGH_SPEED ? 512 : 64), +}; + +// Invoked when received GET CONFIGURATION DESCRIPTOR +// Application return pointer to descriptor +// Descriptor contents must exist long enough for transfer to complete +uint8_t const *tud_descriptor_configuration_cb(uint8_t index) { + (void)index; // for multiple configurations + return desc_configuration; +} + +//--------------------------------------------------------------------+ +// BOS Descriptor +//--------------------------------------------------------------------+ + +/* Microsoft OS 2.0 registry property descriptor +Per MS requirements https://msdn.microsoft.com/en-us/library/windows/hardware/hh450799(v=vs.85).aspx +device should create DeviceInterfaceGUIDs. It can be done by driver and +in case of real PnP solution device should expose MS "Microsoft OS 2.0 +registry property descriptor". Such descriptor can insert any record +into Windows registry per device/configuration/interface. In our case it +will insert "DeviceInterfaceGUIDs" multistring property. + +GUID is freshly generated and should be OK to use. + +https://developers.google.com/web/fundamentals/native-hardware/build-for-webusb/ +(Section Microsoft OS compatibility descriptors) +*/ + +#define BOS_TOTAL_LEN (TUD_BOS_DESC_LEN + TUD_BOS_WEBUSB_DESC_LEN + TUD_BOS_MICROSOFT_OS_DESC_LEN) + +#define MS_OS_20_DESC_LEN 0xB2 + +// BOS Descriptor is required for webUSB +uint8_t const desc_bos[] = + { + // total length, number of device caps + TUD_BOS_DESCRIPTOR(BOS_TOTAL_LEN, 2), + + // Vendor Code, iLandingPage + TUD_BOS_WEBUSB_DESCRIPTOR(VENDOR_REQUEST_WEBUSB, 1), + + // Microsoft OS 2.0 descriptor + TUD_BOS_MS_OS_20_DESCRIPTOR(MS_OS_20_DESC_LEN, VENDOR_REQUEST_MICROSOFT)}; + +uint8_t const *tud_descriptor_bos_cb(void) { + return desc_bos; +} + +uint8_t const desc_ms_os_20[] = + { + // Set header: length, type, windows version, total length + U16_TO_U8S_LE(0x000A), U16_TO_U8S_LE(MS_OS_20_SET_HEADER_DESCRIPTOR), U32_TO_U8S_LE(0x06030000), U16_TO_U8S_LE(MS_OS_20_DESC_LEN), + + // Configuration subset header: length, type, configuration index, reserved, configuration total length + U16_TO_U8S_LE(0x0008), U16_TO_U8S_LE(MS_OS_20_SUBSET_HEADER_CONFIGURATION), 0, 0, U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A), + + // Function Subset header: length, type, first interface, reserved, subset length + U16_TO_U8S_LE(0x0008), U16_TO_U8S_LE(MS_OS_20_SUBSET_HEADER_FUNCTION), ITF_NUM_VENDOR, 0, U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A - 0x08), + + // MS OS 2.0 Compatible ID descriptor: length, type, compatible ID, sub compatible ID + U16_TO_U8S_LE(0x0014), U16_TO_U8S_LE(MS_OS_20_FEATURE_COMPATBLE_ID), 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // sub-compatible + + // MS OS 2.0 Registry property descriptor: length, type + U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A - 0x08 - 0x08 - 0x14), U16_TO_U8S_LE(MS_OS_20_FEATURE_REG_PROPERTY), + U16_TO_U8S_LE(0x0007), U16_TO_U8S_LE(0x002A), // wPropertyDataType, wPropertyNameLength and PropertyName "DeviceInterfaceGUIDs\0" in UTF-16 + 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, + 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, 'U', 0x00, 'I', 0x00, 'D', 0x00, 's', 0x00, 0x00, 0x00, + U16_TO_U8S_LE(0x0050), // wPropertyDataLength + // bPropertyData: “{975F44D9-0D08-43FD-8B3E-127CA8AFFF9D}”. + '{', 0x00, '9', 0x00, '7', 0x00, '5', 0x00, 'F', 0x00, '4', 0x00, '4', 0x00, 'D', 0x00, '9', 0x00, '-', 0x00, + '0', 0x00, 'D', 0x00, '0', 0x00, '8', 0x00, '-', 0x00, '4', 0x00, '3', 0x00, 'F', 0x00, 'D', 0x00, '-', 0x00, + '8', 0x00, 'B', 0x00, '3', 0x00, 'E', 0x00, '-', 0x00, '1', 0x00, '2', 0x00, '7', 0x00, 'C', 0x00, 'A', 0x00, + '8', 0x00, 'A', 0x00, 'F', 0x00, 'F', 0x00, 'F', 0x00, '9', 0x00, 'D', 0x00, '}', 0x00, 0x00, 0x00, 0x00, 0x00}; + +TU_VERIFY_STATIC(sizeof(desc_ms_os_20) == MS_OS_20_DESC_LEN, "Incorrect size"); + +//--------------------------------------------------------------------+ +// String Descriptors +//--------------------------------------------------------------------+ + +// String Descriptor Index +enum { + STRID_LANGID = 0, + STRID_MANUFACTURER, + STRID_PRODUCT, + STRID_SERIAL, +}; + +// array of pointer to string descriptors +char const *string_desc_arr[] = + { + (const char[]){0x09, 0x04}, // 0: is supported language is English (0x0409) + "Heiso", // 1: Manufacturer + "Macrolev", // 2: Product + "345678", // 3: Serials will use unique ID if possible + "WebUSB Interface", // 5: Interface 2 String + "Keyboard Interface", // 6: Interface 3 String +}; + +static uint16_t _desc_str[32 + 1]; + +// Invoked when received GET STRING DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { + (void)langid; + size_t chr_count; + + if (index == 0) { + memcpy(&_desc_str[1], string_desc_arr[0], 2); + chr_count = 1; + } else { + // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. + // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors + + if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) + return NULL; + + const char *str = string_desc_arr[index]; + + // Cap at max char + chr_count = strlen(str); + if (chr_count > 31) + chr_count = 31; + + // Convert ASCII string into UTF-16 + for (uint8_t i = 0; i < chr_count; i++) { + _desc_str[1 + i] = str[i]; + } + } + + switch (index) { + case STRID_LANGID: + memcpy(&_desc_str[1], string_desc_arr[0], 2); + chr_count = 1; + break; + + case STRID_SERIAL: + chr_count = 10; + break; + + default: + // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. + // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors + + if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) + return NULL; + + const char *str = string_desc_arr[index]; + + // Cap at max char + chr_count = strlen(str); + size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type + if (chr_count > max_count) + chr_count = max_count; + + // Convert ASCII string into UTF-16 + for (size_t i = 0; i < chr_count; i++) { + _desc_str[1 + i] = str[i]; + } + break; + } + + // first byte is length (including header), second byte is string type + _desc_str[0] = (uint16_t)((TUSB_DESC_STRING << 8) | (2 * chr_count + 2)); + + return _desc_str; +} diff --git a/firmware/Core/Startup/startup_stm32f411ceux.s b/firmware/stm32f4xx/Core/Startup/startup_stm32f411ceux.s similarity index 100% rename from firmware/Core/Startup/startup_stm32f411ceux.s rename to firmware/stm32f4xx/Core/Startup/startup_stm32f411ceux.s diff --git a/firmware/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h b/firmware/stm32f4xx/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h similarity index 100% rename from firmware/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h rename to firmware/stm32f4xx/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h diff --git a/firmware/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h b/firmware/stm32f4xx/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h similarity index 100% rename from firmware/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h rename to firmware/stm32f4xx/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h diff --git a/firmware/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h b/firmware/stm32f4xx/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h similarity index 100% rename from firmware/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h rename to firmware/stm32f4xx/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h diff --git a/firmware/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt b/firmware/stm32f4xx/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt similarity index 100% rename from firmware/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt rename to firmware/stm32f4xx/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt diff --git a/firmware/Drivers/CMSIS/Include/cachel1_armv7.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/cachel1_armv7.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/cachel1_armv7.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/cachel1_armv7.h diff --git a/firmware/Drivers/CMSIS/Include/cmsis_armcc.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_armcc.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/cmsis_armcc.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_armcc.h diff --git a/firmware/Drivers/CMSIS/Include/cmsis_armclang.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_armclang.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/cmsis_armclang.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_armclang.h diff --git a/firmware/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_armclang_ltm.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/cmsis_armclang_ltm.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_armclang_ltm.h diff --git a/firmware/Drivers/CMSIS/Include/cmsis_compiler.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_compiler.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/cmsis_compiler.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_compiler.h diff --git a/firmware/Drivers/CMSIS/Include/cmsis_gcc.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_gcc.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/cmsis_gcc.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_gcc.h diff --git a/firmware/Drivers/CMSIS/Include/cmsis_iccarm.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_iccarm.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/cmsis_iccarm.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_iccarm.h diff --git a/firmware/Drivers/CMSIS/Include/cmsis_version.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_version.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/cmsis_version.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/cmsis_version.h diff --git a/firmware/Drivers/CMSIS/Include/core_armv81mml.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_armv81mml.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_armv81mml.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_armv81mml.h diff --git a/firmware/Drivers/CMSIS/Include/core_armv8mbl.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_armv8mbl.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_armv8mbl.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_armv8mbl.h diff --git a/firmware/Drivers/CMSIS/Include/core_armv8mml.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_armv8mml.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_armv8mml.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_armv8mml.h diff --git a/firmware/Drivers/CMSIS/Include/core_cm0.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm0.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_cm0.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm0.h diff --git a/firmware/Drivers/CMSIS/Include/core_cm0plus.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm0plus.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_cm0plus.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm0plus.h diff --git a/firmware/Drivers/CMSIS/Include/core_cm1.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm1.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_cm1.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm1.h diff --git a/firmware/Drivers/CMSIS/Include/core_cm23.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm23.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_cm23.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm23.h diff --git a/firmware/Drivers/CMSIS/Include/core_cm3.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm3.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_cm3.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm3.h diff --git a/firmware/Drivers/CMSIS/Include/core_cm33.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm33.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_cm33.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm33.h diff --git a/firmware/Drivers/CMSIS/Include/core_cm35p.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm35p.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_cm35p.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm35p.h diff --git a/firmware/Drivers/CMSIS/Include/core_cm4.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm4.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_cm4.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm4.h diff --git a/firmware/Drivers/CMSIS/Include/core_cm55.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm55.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_cm55.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm55.h diff --git a/firmware/Drivers/CMSIS/Include/core_cm7.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm7.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_cm7.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm7.h diff --git a/firmware/Drivers/CMSIS/Include/core_cm85.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm85.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_cm85.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_cm85.h diff --git a/firmware/Drivers/CMSIS/Include/core_sc000.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_sc000.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_sc000.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_sc000.h diff --git a/firmware/Drivers/CMSIS/Include/core_sc300.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_sc300.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_sc300.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_sc300.h diff --git a/firmware/Drivers/CMSIS/Include/core_starmc1.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/core_starmc1.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/core_starmc1.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/core_starmc1.h diff --git a/firmware/Drivers/CMSIS/Include/mpu_armv7.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/mpu_armv7.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/mpu_armv7.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/mpu_armv7.h diff --git a/firmware/Drivers/CMSIS/Include/mpu_armv8.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/mpu_armv8.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/mpu_armv8.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/mpu_armv8.h diff --git a/firmware/Drivers/CMSIS/Include/pac_armv81.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/pac_armv81.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/pac_armv81.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/pac_armv81.h diff --git a/firmware/Drivers/CMSIS/Include/pmu_armv8.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/pmu_armv8.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/pmu_armv8.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/pmu_armv8.h diff --git a/firmware/Drivers/CMSIS/Include/tz_context.h b/firmware/stm32f4xx/Drivers/CMSIS/Include/tz_context.h similarity index 100% rename from firmware/Drivers/CMSIS/Include/tz_context.h rename to firmware/stm32f4xx/Drivers/CMSIS/Include/tz_context.h diff --git a/firmware/Drivers/CMSIS/LICENSE.txt b/firmware/stm32f4xx/Drivers/CMSIS/LICENSE.txt similarity index 100% rename from firmware/Drivers/CMSIS/LICENSE.txt rename to firmware/stm32f4xx/Drivers/CMSIS/LICENSE.txt diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c diff --git a/firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c b/firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c similarity index 100% rename from firmware/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c rename to firmware/stm32f4xx/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c diff --git a/firmware/STM32F411CEUX_FLASH.ld b/firmware/stm32f4xx/STM32F411CEUX_FLASH.ld similarity index 100% rename from firmware/STM32F411CEUX_FLASH.ld rename to firmware/stm32f4xx/STM32F411CEUX_FLASH.ld diff --git a/firmware/STM32F411CEUX_RAM.ld b/firmware/stm32f4xx/STM32F411CEUX_RAM.ld similarity index 100% rename from firmware/STM32F411CEUX_RAM.ld rename to firmware/stm32f4xx/STM32F411CEUX_RAM.ld diff --git a/firmware/macrolev Debug.launch b/firmware/stm32f4xx/macrolev Debug.launch similarity index 100% rename from firmware/macrolev Debug.launch rename to firmware/stm32f4xx/macrolev Debug.launch diff --git a/firmware/macrolev Release.launch b/firmware/stm32f4xx/macrolev Release.launch similarity index 100% rename from firmware/macrolev Release.launch rename to firmware/stm32f4xx/macrolev Release.launch diff --git a/firmware/macrolev.ioc b/firmware/stm32f4xx/macrolev.ioc similarity index 100% rename from firmware/macrolev.ioc rename to firmware/stm32f4xx/macrolev.ioc diff --git a/firmware/stm32f4xx/tinyusb b/firmware/stm32f4xx/tinyusb new file mode 160000 index 0000000..7c7b30f --- /dev/null +++ b/firmware/stm32f4xx/tinyusb @@ -0,0 +1 @@ +Subproject commit 7c7b30f0ae66a856ada3526cb947bd3a255567f8 diff --git a/firmware/tinyusb b/firmware/tinyusb deleted file mode 160000 index d816a9b..0000000 --- a/firmware/tinyusb +++ /dev/null @@ -1 +0,0 @@ -Subproject commit d816a9bdf892daeb35b88b9a469599fcda432c55