diff --git a/benches/logicvector.rs b/benches/logicvector.rs
index f4d697c..818330f 100644
--- a/benches/logicvector.rs
+++ b/benches/logicvector.rs
@@ -12,7 +12,7 @@ const NITER: u128 = 10_000;
 fn create_from_int(b: &mut Bencher) {
     b.iter(|| {
         for i in 0..NITER {
-            bb(LogicVector::from_int_value(i, 128));
+            bb(LogicVector::from_int(i, 128));
         }
     });
 }
@@ -48,7 +48,7 @@ fn create_width(b: &mut Bencher) {
 fn to_u128(b: &mut Bencher) {
     b.iter(|| {
         for i in 0..NITER {
-            assert_eq!(Some(i), bb(LogicVector::from_int_value(i, 128)).unwrap().as_u128());
+            assert_eq!(Some(i), bb(LogicVector::from_int(i, 128)).unwrap().as_u128());
         }
     })
 }
diff --git a/examples/fulladder.rs b/examples/fulladder.rs
index 4bc5dab..9e4ac66 100644
--- a/examples/fulladder.rs
+++ b/examples/fulladder.rs
@@ -106,9 +106,9 @@ fn main() {
     ];
 
     for triple in VALUES.iter() {
-        x.set_value(triple[0]);
-        y.set_value(triple[1]);
-        c.set_value(triple[2]);
+        x.replace(triple[0]);
+        y.replace(triple[1]);
+        c.replace(triple[2]);
 
         for _ in 0..3 {
             circuit.tick();
diff --git a/examples/vcd_reg_dump.rs b/examples/vcd_reg_dump.rs
index bd7f66e..fa5113b 100644
--- a/examples/vcd_reg_dump.rs
+++ b/examples/vcd_reg_dump.rs
@@ -29,7 +29,7 @@ fn main() {
     dumper.serialize_logivector("foo", &foo);
     dumper.tick();
 
-    let one = LogicVector::from_int_value(1, 16).unwrap();
+    let one = LogicVector::from_int(1, 16).unwrap();
     for _ in 0..90 {
         foo = foo + &one;
         dumper.serialize_logivector("foo", &foo);
diff --git a/examples/vcd_wire_dump.rs b/examples/vcd_wire_dump.rs
index 16f7900..de9777a 100644
--- a/examples/vcd_wire_dump.rs
+++ b/examples/vcd_wire_dump.rs
@@ -49,7 +49,7 @@ fn main() {
     circuit.tick();
     circuit.tick();
     circuit.tick();
-    mux_switch.set_value(Ieee1164::_1);
+    mux_switch.replace(Ieee1164::_1);
     circuit.tick();
 
     let mut dumper = Vcd::new("VCD Example");
@@ -62,7 +62,7 @@ fn main() {
         dumper.tick();
         if i % 20 == 0 {
             val = !val;
-            input1.set_value(val);
+            input1.replace(val);
         }
     }
 
diff --git a/src/logicbit/ieee1164.rs b/src/logicbit/ieee1164.rs
index 964f272..e4e1e32 100644
--- a/src/logicbit/ieee1164.rs
+++ b/src/logicbit/ieee1164.rs
@@ -353,4 +353,19 @@ mod tests {
         assert!(Ieee1164::_D.is_UXZ());
         assert!(Ieee1164::_X.is_UXZ());
     }
+
+    #[test]
+    fn check_associated_consts() {
+        // this testcase seems useless, but I want to make sure, that the associated consts do match
+        // the proposed values!
+        assert_eq!(Ieee1164::_U, Ieee1164::Uninitialized);
+        assert_eq!(Ieee1164::_X, Ieee1164::Strong(Ieee1164Value::Unknown));
+        assert_eq!(Ieee1164::_1, Ieee1164::Strong(Ieee1164Value::One));
+        assert_eq!(Ieee1164::_0, Ieee1164::Strong(Ieee1164Value::Zero));
+        assert_eq!(Ieee1164::_W, Ieee1164::Weak(Ieee1164Value::Unknown));
+        assert_eq!(Ieee1164::_H, Ieee1164::Weak(Ieee1164Value::One));
+        assert_eq!(Ieee1164::_L, Ieee1164::Weak(Ieee1164Value::Zero));
+        assert_eq!(Ieee1164::_Z, Ieee1164::HighImpedance);
+        assert_eq!(Ieee1164::_D, Ieee1164::DontCare);
+    }
 }
diff --git a/src/logicbit/logicvector/mod.rs b/src/logicbit/logicvector/mod.rs
index b2bf441..04bb11c 100644
--- a/src/logicbit/logicvector/mod.rs
+++ b/src/logicbit/logicvector/mod.rs
@@ -69,17 +69,17 @@ pub struct LogicVector {
 }
 
 impl LogicVector {
-    /// Accepts a [`Ieee1164`] and set that value to the whole range of `width`.
+    /// Accepts a [`Ieee1164`] and sets that `value` to the whole range of `width`.
     ///
     /// # Example
     ///
     /// ```rust
     /// use logical::{Ieee1164, LogicVector};
-    /// let lv = LogicVector::from_ieee_value(Ieee1164::_0, 8);
+    /// let lv = LogicVector::from_ieee(Ieee1164::_0, 8);
     /// assert_eq!(8, lv.width());
     /// assert!(lv.is_000());
     /// ```
-    pub fn from_ieee_value(value: Ieee1164, width: u8) -> Self {
+    pub fn from_ieee(value: Ieee1164, width: u8) -> Self {
         assert!(assert_width(width));
         let mut s = Self {
             masks: Masks::default(),
@@ -102,7 +102,7 @@ impl LogicVector {
     ///
     /// ```rust
     /// use logical::LogicVector;
-    /// let lv = LogicVector::from_int_value(42, 8).unwrap();
+    /// let lv = LogicVector::from_int(42, 8).unwrap();
     /// assert_eq!(lv.as_u128(), Some(42));
     /// ```
     ///
@@ -111,10 +111,10 @@ impl LogicVector {
     ///
     /// ```rust
     /// use logical::LogicVector;
-    /// let lv = LogicVector::from_int_value(42, 5);
+    /// let lv = LogicVector::from_int(42, 5);
     /// assert!(lv.is_none());
     /// ```
-    pub fn from_int_value(value: u128, width: u8) -> Option<Self> {
+    pub fn from_int(value: u128, width: u8) -> Option<Self> {
         let zeros = value.leading_zeros() as u8;
         if assert_width(width) && width >= (128 - zeros) {
             let mut masks = Masks::default();
@@ -132,11 +132,11 @@ impl LogicVector {
     /// (undefined). It is a shortcut for
     ///
     /// ```text
-    /// LogicVector::from_ieee_value(Ieee1164::_U, width);
+    /// LogicVector::from_ieee(Ieee1164::_U, width);
     /// ```
     pub fn with_width(width: u8) -> Self {
         assert!(assert_width(width));
-        Self::from_ieee_value(Ieee1164::default(), width)
+        Self::from_ieee(Ieee1164::default(), width)
     }
 }
 
@@ -178,7 +178,7 @@ impl LogicVector {
     ///
     /// ```rust
     /// # use logical::{Ieee1164, LogicVector};
-    /// let mut lv1 = LogicVector::from_int_value(42, 8).unwrap();
+    /// let mut lv1 = LogicVector::from_int(42, 8).unwrap();
     /// let lv2 = lv1.clone();
     /// let cropped = lv1.resize(8, Ieee1164::_U);
     ///
@@ -190,7 +190,7 @@ impl LogicVector {
     ///
     /// ```rust
     /// # use logical::{Ieee1164, LogicVector};
-    /// let mut lv = LogicVector::from_int_value(58, 7).unwrap();
+    /// let mut lv = LogicVector::from_int(58, 7).unwrap();
     /// let cropped = lv.resize(4, Ieee1164::_U).unwrap();
     ///
     /// assert_eq!(4, lv.width());
@@ -203,7 +203,7 @@ impl LogicVector {
     ///
     /// ```rust
     /// # use logical::{Ieee1164, LogicVector};
-    /// let mut lv = LogicVector::from_int_value(42, 6).unwrap();
+    /// let mut lv = LogicVector::from_int(42, 6).unwrap();
     /// lv.resize(8, Ieee1164::_1);
     ///
     /// assert_eq!(Some(0b11101010), lv.as_u128());
@@ -211,7 +211,7 @@ impl LogicVector {
     ///
     /// ```rust
     /// # use logical::{Ieee1164, LogicVector};
-    /// let mut lv = LogicVector::from_int_value(42, 8).unwrap();
+    /// let mut lv = LogicVector::from_int(42, 8).unwrap();
     /// lv.resize(10, Ieee1164::_1);
     ///
     /// assert_eq!(Some(0b1100101010), lv.as_u128());
@@ -222,7 +222,7 @@ impl LogicVector {
                 (a, b) if a >= b => unreachable!("`old` cannot be greater/equal than `new`!"),
                 (128, 128) => std::u128::MAX,
                 (a, 128) => std::u128::MAX & !((1 << a) - 1),
-                (a, b) => ((1 << b) - 1) & !((1 << a) - 1),
+                (a, b) => ((1u128 << b) - 1) & !((1 << a) - 1),
             }
         }
 
@@ -303,13 +303,13 @@ impl LogicVector {
     ///
     /// ```rust
     /// # use logical::LogicVector;
-    /// let lv = LogicVector::from_int_value(55, 8).unwrap();
+    /// let lv = LogicVector::from_int(55, 8).unwrap();
     /// assert_eq!(Some(55), lv.as_u128());
     /// ```
     ///
     /// ```rust
     /// # use logical::{Ieee1164, LogicVector};
-    /// let mut lv = LogicVector::from_int_value(55, 8).unwrap();
+    /// let mut lv = LogicVector::from_int(55, 8).unwrap();
     /// assert_eq!(Some(55), lv.as_u128());
     /// lv.set(7, Ieee1164::_X);
     /// assert_eq!(None, lv.as_u128());
@@ -432,7 +432,7 @@ impl LogicVector {
         }
         let width = self.width();
         if let (Some(a), Some(b)) = (self.as_u128(), rhs.as_u128()) {
-            LogicVector::from_int_value((a + b) & mask_from_width(width), width)
+            LogicVector::from_int((a + b) & mask_from_width(width), width)
         } else {
             Some(LogicVector::with_width(width))
         }
@@ -448,7 +448,7 @@ fn add(lhs: &LogicVector, rhs: &LogicVector) -> LogicVector {
     let width = lhs.width();
     assert_eq!(width, rhs.width());
 
-    LogicVector::from_int_value(
+    LogicVector::from_int(
         (lhs.as_u128().unwrap() + rhs.as_u128().unwrap()) & mask_from_width(width),
         width,
     )
@@ -636,7 +636,7 @@ mod tests {
     proptest! {
         #[test]
         fn atm_ctor_value(value in 1u64..) {
-            let v = LogicVector::from_int_value(value as u128, 128);
+            let v = LogicVector::from_int(value as u128, 128);
             prop_assert!(v.is_some());
             let v = v.unwrap();
             prop_assert_eq!(v, value as u128);
@@ -644,7 +644,7 @@ mod tests {
 
         #[test]
         fn atm_as_u128(val in 0u64..) {
-            let v = LogicVector::from_int_value(val as u128, 64);
+            let v = LogicVector::from_int(val as u128, 64);
             prop_assert!(v.is_some());
             let mut v = v.unwrap();
             prop_assert_eq!(Ok(()), v.sanity_check());
@@ -664,8 +664,8 @@ mod tests {
             prop_assume!(c.is_some());
             let c = c.unwrap();
 
-            let ia = LogicVector::from_int_value(a, 128);
-            let ib = LogicVector::from_int_value(b, 128);
+            let ia = LogicVector::from_int(a, 128);
+            let ib = LogicVector::from_int(b, 128);
 
             prop_assert!(ia.is_some());
             prop_assert!(ib.is_some());
@@ -706,17 +706,17 @@ mod tests {
 
     #[test]
     fn ctor_value() {
-        let v = LogicVector::from_int_value(5, 3);
+        let v = LogicVector::from_int(5, 3);
         assert!(v.is_some());
         let v = v.unwrap();
         assert_eq!(v.width(), 3);
         assert_eq!(v, 5);
-        let v = LogicVector::from_int_value(0, 128);
+        let v = LogicVector::from_int(0, 128);
         assert!(v.is_some());
         let v = v.unwrap();
         assert_eq!(v.width(), 128);
         assert_eq!(v, 0);
-        let v = LogicVector::from_int_value(5, 8);
+        let v = LogicVector::from_int(5, 8);
         assert!(v.is_some());
         let v = v.unwrap();
         assert_eq!(v.width(), 8);
@@ -736,7 +736,7 @@ mod tests {
         v.set_width(1);
         assert_eq!(v.width(), 1);
 
-        let mut v = LogicVector::from_int_value(31, 5).unwrap();
+        let mut v = LogicVector::from_int(31, 5).unwrap();
         assert_eq!(v.width(), 5);
         assert_eq!(v.as_u128(), Some(0b11111));
         v.set_width(4);
@@ -766,7 +766,7 @@ mod tests {
         v.set_width(5);
         assert_eq!(v.width(), 5);
 
-        let mut v = LogicVector::from_int_value(0, 1).unwrap();
+        let mut v = LogicVector::from_int(0, 1).unwrap();
         assert_eq!(v.width(), 1);
         assert_eq!(v, 0);
         v.resize(2, Ieee1164::_1);
diff --git a/src/models/rtlib/inputs/ivector.rs b/src/models/rtlib/inputs/ivector.rs
index c2bf354..3caa47e 100644
--- a/src/models/rtlib/inputs/ivector.rs
+++ b/src/models/rtlib/inputs/ivector.rs
@@ -14,4 +14,12 @@ impl VectorInput {
             _private: (),
         }
     }
+
+    /// Creates this input with the given [`LogicVector`] as inner value.
+    pub fn with_logicvector(lv: LogicVector) -> Self {
+        Self {
+            port: Port::new(lv),
+            _private: (),
+        }
+    }
 }
diff --git a/src/models/rtlib/memory/rom.rs b/src/models/rtlib/memory/rom.rs
index a40b7fb..381eb56 100644
--- a/src/models/rtlib/memory/rom.rs
+++ b/src/models/rtlib/memory/rom.rs
@@ -28,12 +28,12 @@ pub struct Rom1kx8 {
 impl FromIterator<u8> for Rom1kx8 {
     fn from_iter<I: IntoIterator<Item = u8>>(iter: I) -> Self {
         let mut mem = [0; 1024];
-        let mut idx = 0;
+        let mut bytes_read = 0;
         for (m, v) in mem.iter_mut().zip(iter.into_iter()).take(1024) {
-            idx += 1;
+            bytes_read += 1;
             *m = v;
         }
-        assert!(idx >= 1023);
+        assert_eq!(1024, bytes_read);
 
         Self {
             memory: mem,
@@ -88,7 +88,7 @@ impl Updateable for Rom1kx8 {
             } else if ncs.is_1H() || noe.is_1H() {
                 f.set_all_to(Ieee1164::_Z);
             } else if let Some(data) = data {
-                f.set_int_value(data).unwrap();
+                f.replace_with_int(data).unwrap();
             } else {
                 f.set_all_to(Ieee1164::_X);
             }
@@ -112,7 +112,7 @@ mod tests {
     #[test]
     fn read_out_all_data() {
         let mut rom: Rom1kx8 = (0..=255).cycle().collect();
-        let mut addr = Port::<LogicVector, Output>::new(LogicVector::from_ieee_value(Ieee1164::_0, 10));
+        let mut addr = Port::<LogicVector, Output>::new(LogicVector::from_ieee(Ieee1164::_0, 10));
         let data = Port::<LogicVector, Input>::new(LogicVector::with_width(8));
         let noe = Port::<Ieee1164, Output>::new(Ieee1164::_0);
 
@@ -132,7 +132,7 @@ mod tests {
         sig_data.connect(&data).unwrap();
 
         for i in 0..1024 {
-            addr.with_value_mut(|f| f.set_int_value(i).unwrap());
+            addr.with_value_mut(|f| f.replace_with_int(i).unwrap());
             sig_addr.update();
             rom.update();
             sig_data.update();
@@ -147,7 +147,7 @@ mod tests {
         for (i, m) in rom.memory.iter_mut().enumerate() {
             *m = i as u8;
         }
-        let mut addr = Port::<LogicVector, Output>::new(LogicVector::from_ieee_value(Ieee1164::_0, 10));
+        let mut addr = Port::<LogicVector, Output>::new(LogicVector::from_ieee(Ieee1164::_0, 10));
         let data = Port::<LogicVector, Input>::new(LogicVector::with_width(8));
         let noe = Port::<Ieee1164, Output>::new(Ieee1164::_0);
 
@@ -167,7 +167,7 @@ mod tests {
         sig_data.connect(&data).unwrap();
 
         for i in 0..1024 {
-            addr.with_value_mut(|f| f.set_int_value(i).unwrap());
+            addr.with_value_mut(|f| f.replace_with_int(i).unwrap());
             sig_addr.update();
             rom.update();
             sig_data.update();
diff --git a/src/port/pport.rs b/src/port/pport.rs
index ac8306a..0837631 100644
--- a/src/port/pport.rs
+++ b/src/port/pport.rs
@@ -316,24 +316,24 @@ mod tests {
     #[test]
     fn set() {
         let mut s = Port::<_, Output>::default();
-        s.replace(LogicVector::from_int_value(3, 8));
+        s.replace(LogicVector::from_int(3, 8));
         //assert_eq!(*s.inner.value.read().unwrap(), 3);
     }
 
     #[test]
     fn reset() {
         let mut s = Port::<_, InOut>::default();
-        s.replace(LogicVector::from_int_value(5, 8));
+        s.replace(LogicVector::from_int(5, 8));
         //assert_eq!(s.value(), 5);
-        s.replace(LogicVector::from_int_value(6, 8));
+        s.replace(LogicVector::from_int(6, 8));
         //assert_eq!(s.value(), 6);
     }
 
     #[test]
     fn reset_before_reading() {
         let mut s = Port::<_, InOut>::default();
-        s.replace(LogicVector::from_int_value(4, 8));
-        s.replace(LogicVector::from_int_value(8, 8));
+        s.replace(LogicVector::from_int(4, 8));
+        s.replace(LogicVector::from_int(8, 8));
         //assert_eq!(s.value(), 8);
     }
 
diff --git a/src/signal.rs b/src/signal.rs
index d7319cf..e498710 100644
--- a/src/signal.rs
+++ b/src/signal.rs
@@ -138,7 +138,6 @@ where
         self.remove_expired_portconnector();
 
         let in_guard = self.inner.input_ports.write().unwrap();
-
         let mut iter = in_guard.iter();
 
         let first_port = loop {