From b818e15bff24c6b4a5c771695efd4c4b4d0d1223 Mon Sep 17 00:00:00 2001 From: Simon Doppler Date: Mon, 19 Aug 2019 13:05:47 +0200 Subject: [PATCH] fix documentation links --- src/models/gates/mod.rs | 5 +++-- src/models/gates/tri.rs | 2 +- src/models/mod.rs | 4 +++- src/models/rtlib/memory/rom.rs | 3 ++- src/port/portdirection.rs | 2 +- 5 files changed, 10 insertions(+), 6 deletions(-) diff --git a/src/models/gates/mod.rs b/src/models/gates/mod.rs index f81f9b1..6688623 100644 --- a/src/models/gates/mod.rs +++ b/src/models/gates/mod.rs @@ -1,5 +1,6 @@ -//! This module provides logic gates that work with [`Ieee1164`], e.g. [`AndGate`], [`OrGate`], -//! [`Buffer`], [`Mux`], etc. +//! This module provides logic gates that work with [`Ieee1164`](crate::Ieee1164), e.g. +//! [`AndGate`](crate::models::gates::AndGate), [`OrGate`](crate::models::gates::OrGate), +//! [`Buffer`](crate::models::gates::Buffer), [`Mux`](crate::models::gates::Mux), etc. mod mux; mod tri; diff --git a/src/models/gates/tri.rs b/src/models/gates/tri.rs index db5e084..b6b5dbb 100644 --- a/src/models/gates/tri.rs +++ b/src/models/gates/tri.rs @@ -2,7 +2,7 @@ use crate::direction::{Input, Output}; use crate::dump::IterPorts; use crate::{Ieee1164, Port, Updateable}; -/// A `Tristate-buffer` can be used if you need multiple signals to drive a single [`Signal`]. +/// A `Tristate-buffer` can be used if you need multiple signals to drive a single [`Signal`](crate::Signal). /// /// This is often used if multiple signals must drive a single one, e.g. a s.c. bus. If [`TriBuffer::s`] is /// driven high, [`TriBuffer::z`] will be the value of [`TriBuffer::a`]. If it's driven low, it will diff --git a/src/models/mod.rs b/src/models/mod.rs index 7db8d93..9867a7f 100644 --- a/src/models/mod.rs +++ b/src/models/mod.rs @@ -1,5 +1,7 @@ //! This module will contain different models that can be used to perform certain calculations. E.g. -//! Gates, like [`AndGate`], [`Mux`], [`Switch`], but also complex gates, like ['Alu`] or [`Rom1kx8`]. +//! Gates, like [`AndGate`](crate::models::gates::AndGate), [`Mux`](crate::models::gates::Mux), +//! [`Switch`](crate::models::inputs::Switch), but also complex gates, like +//! [`Rom1kx8`](crate::models::rtlib::memory::rom::Rom1kx8). pub mod gates; pub mod inputs; diff --git a/src/models/rtlib/memory/rom.rs b/src/models/rtlib/memory/rom.rs index 385ffd9..44cd81b 100644 --- a/src/models/rtlib/memory/rom.rs +++ b/src/models/rtlib/memory/rom.rs @@ -10,7 +10,8 @@ use crate::{Ieee1164, LogicVector, Port, Updateable}; /// output-enable line which can be used to control the data output to be [`Ieee1164::_Z`] /// (high-impedance) instead of outputting a value. /// -/// Althought it's a `Rom`, you can modify the values inside programmatically, but not with `Signals`. +/// Althought it's a `Rom`, you can modify the values inside programmatically, but not with +/// [`Signals`](crate::Signal). /// /// # Examples /// diff --git a/src/port/portdirection.rs b/src/port/portdirection.rs index 51b6b77..1e0bb5e 100644 --- a/src/port/portdirection.rs +++ b/src/port/portdirection.rs @@ -31,7 +31,7 @@ impl MaybeWrite for Off {} /// Trait for describing a `PortDirection`. /// -/// This is used for the [`Port`] struct so it can offer or +/// This is used for the [`Port`](crate::port::Port) struct so it can offer or /// decline certain functions at compile time, e.g. reading an `Output` `Port` should not be /// possible, but only writing to it. ///