diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..22676ce --- /dev/null +++ b/.gitignore @@ -0,0 +1,4 @@ +/target +**/*.rs.bk +Cargo.lock +.idea/ diff --git a/Cargo.toml b/Cargo.toml new file mode 100644 index 0000000..67ba67f --- /dev/null +++ b/Cargo.toml @@ -0,0 +1,8 @@ +[package] +name = "logical" +version = "0.1.0" +authors = ["Marcel Hellwig "] +edition = "2018" + +[dependencies] +anymap = "*" diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..f288702 --- /dev/null +++ b/LICENSE @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..2468caf --- /dev/null +++ b/Makefile @@ -0,0 +1,20 @@ + +all: clippy test + +format: + @cargo fmt + +clippy: + @cargo clippy + +test: + @cargo test + +build: + @cargo build + +run: + @cargo run + +doc: + @cargo doc --open diff --git a/examples/fulladder.rs b/examples/fulladder.rs new file mode 100644 index 0000000..693ab69 --- /dev/null +++ b/examples/fulladder.rs @@ -0,0 +1,131 @@ +//! Lets try to build a full adder! + +use std::error::Error; +use std::thread::sleep; +use std::time::Duration; + +use logical::gates::{AndGate, OrGate, XorGate}; +use logical::models::inputs::Switch; +use logical::models::outputs::Led; +use logical::{Ieee1164, Ieee1164Value, Reactor, Signal}; + +fn main() -> Result<(), Box> { + //first halfadder + let and1 = AndGate::default(); + let xor1 = XorGate::default(); + + //second halfadder + let and2 = AndGate::default(); + let xor2 = XorGate::default(); + + //cout or + let or = OrGate::default(); + + //inputs + let mut x = Switch::default(); + let mut y = Switch::default(); + let mut c = Switch::default(); + + //outputs + let cout = Led::default(); + let s = Led::default(); + + //connections + //from x to and and xor of ha1 + let mut s_x = Signal::::new(); + s_x.connect_as_input(&x.output); + s_x.connect_as_output(&and1.a); + s_x.connect_as_output(&xor1.a); + + //from y to and and xor of ha1 + let mut s_y = Signal::new(); + s_y.connect_as_input(&y.output); + s_y.connect_as_output(&and1.b); + s_y.connect_as_output(&xor1.b); + + //from and of ha1 to or + let mut s_ha1_o = Signal::new(); + s_ha1_o.connect_as_input(&and1.z); + s_ha1_o.connect_as_output(&or.a); + + //from from xor of ha1 to ha2 + let mut s_ha1_ha2 = Signal::new(); + s_ha1_ha2.connect_as_input(&xor1.z); + s_ha1_ha2.connect_as_output(&and2.a); + s_ha1_ha2.connect_as_output(&xor2.a); + + //from cin to and2 and xor2 + let mut s_cin_ha2 = Signal::new(); + s_cin_ha2.connect_as_input(&c.output); + s_cin_ha2.connect_as_output(&and2.b); + s_cin_ha2.connect_as_output(&xor2.b); + + //from and2 to xor + let mut s_ha2_o = Signal::new(); + s_ha2_o.connect_as_input(&and2.z); + s_ha2_o.connect_as_output(&or.b); + + //from or to cout + let mut s_or_cout = Signal::new(); + s_or_cout.connect_as_input(&or.z); + s_or_cout.connect_as_output(&cout.input); + + //from xor2 to s + let mut s_ha_s = Signal::new(); + s_ha_s.connect_as_input(&xor2.z); + s_ha_s.connect_as_output(&s.input); + + let mut r = Reactor::new(); + + r.add_updater(&s_x); + r.add_updater(&s_y); + r.add_updater(&s_ha1_o); + r.add_updater(&s_ha1_ha2); + r.add_updater(&s_cin_ha2); + r.add_updater(&s_ha2_o); + r.add_updater(&s_or_cout); + r.add_updater(&s_ha_s); + r.add_updater(&and1); + r.add_updater(&and2); + r.add_updater(&xor1); + r.add_updater(&xor2); + r.add_updater(&or); + + const _0: Ieee1164 = Ieee1164::Strong(Ieee1164Value::Zero); + const _1: Ieee1164 = Ieee1164::Strong(Ieee1164Value::One); + + const VALUES: [[Ieee1164; 5]; 8] = [ + [_0, _0, _0, _0, _0], + [_0, _0, _1, _1, _0], + [_0, _1, _0, _1, _0], + [_0, _1, _1, _0, _1], + [_1, _0, _0, _1, _0], + [_1, _0, _1, _0, _1], + [_1, _1, _0, _0, _1], + [_1, _1, _1, _1, _1], + ]; + + for triple in VALUES.iter() { + x.set_value(triple[0]); + y.set_value(triple[1]); + c.set_value(triple[2]); + + for _ in 0..3 { + r.tick(); + } + + println!( + "{} + {} + {} = {}{}", + triple[0], + triple[1], + triple[2], + cout.value(), + s.value() + ); + assert_eq!(triple[3], s.value()); + assert_eq!(triple[4], cout.value()); + sleep(Duration::from_secs(1)); + } + + Ok(()) +} diff --git a/src/dump/mod.rs b/src/dump/mod.rs new file mode 100644 index 0000000..46330df --- /dev/null +++ b/src/dump/mod.rs @@ -0,0 +1 @@ +//! TODO diff --git a/src/gates/and.rs b/src/gates/and.rs new file mode 100644 index 0000000..0a4bd42 --- /dev/null +++ b/src/gates/and.rs @@ -0,0 +1,35 @@ +use crate::logicbit::Ieee1164; +use crate::port::Port; +use crate::port::{Input, Output}; +use crate::Updateable; + +#[derive(Debug, Clone)] +pub struct AndGate { + pub a: Port, + pub b: Port, + pub z: Port, + _private: (), +} + +impl Updateable for AndGate { + fn update(&mut self) { + self.z.set_value(self.a.value() & self.b.value()); + } +} + +impl Default for AndGate { + fn default() -> Self { + Self::new() + } +} + +impl AndGate { + pub fn new() -> Self { + Self { + a: Port::default(), + b: Port::default(), + z: Port::default(), + _private: (), + } + } +} diff --git a/src/gates/mod.rs b/src/gates/mod.rs new file mode 100644 index 0000000..4d32a90 --- /dev/null +++ b/src/gates/mod.rs @@ -0,0 +1,7 @@ +mod and; +mod or; +mod xor; + +pub use self::and::AndGate; +pub use self::or::OrGate; +pub use self::xor::XorGate; diff --git a/src/gates/or.rs b/src/gates/or.rs new file mode 100644 index 0000000..5863820 --- /dev/null +++ b/src/gates/or.rs @@ -0,0 +1,42 @@ +use crate::logicbit::Ieee1164; +use crate::port::Port; +use crate::port::{Input, Output}; +use crate::Updateable; +use std::fmt; + +#[derive(Clone)] +pub struct OrGate { + pub a: Port, + pub b: Port, + pub z: Port, + _private: (), +} + +impl fmt::Debug for OrGate { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "OrGate {{ a: {:?}, b: {:?}, z: {:?} }}", self.a, self.b, self.z) + } +} + +impl Updateable for OrGate { + fn update(&mut self) { + self.z.set_value(self.a.value() | self.b.value()); + } +} + +impl Default for OrGate { + fn default() -> Self { + Self::new() + } +} + +impl OrGate { + pub fn new() -> Self { + Self { + a: Port::default(), + b: Port::default(), + z: Port::default(), + _private: (), + } + } +} diff --git a/src/gates/xor.rs b/src/gates/xor.rs new file mode 100644 index 0000000..9ccb0f1 --- /dev/null +++ b/src/gates/xor.rs @@ -0,0 +1,35 @@ +use crate::logicbit::Ieee1164; +use crate::port::Port; +use crate::port::{Input, Output}; +use crate::Updateable; + +#[derive(Debug, Clone)] +pub struct XorGate { + pub a: Port, + pub b: Port, + pub z: Port, + _private: (), +} + +impl Updateable for XorGate { + fn update(&mut self) { + self.z.set_value(self.a.value() ^ self.b.value()); + } +} + +impl Default for XorGate { + fn default() -> Self { + Self::new() + } +} + +impl XorGate { + pub fn new() -> Self { + Self { + a: Port::default(), + b: Port::default(), + z: Port::default(), + _private: (), + } + } +} diff --git a/src/integer.rs b/src/integer.rs new file mode 100644 index 0000000..187acef --- /dev/null +++ b/src/integer.rs @@ -0,0 +1,68 @@ +use crate::Resolve; + +#[derive(Debug, Default, Clone, Copy)] +pub struct Integer { + value: u128, + width: u8, +} + +impl<'a, 'b> Resolve<&'b Integer> for &'a Integer { + type Output = Integer; + fn resolve(self, other: &'b Integer) -> Self::Output { + if self.width != other.width { + panic!("Width mismatch!") //TODO: do not panic + } + Integer { + value: self.value | other.value, + width: self.width, + } + } + fn initial_value(&self) -> Integer { + Integer::new_with_value(0u8, self.width()) + } +} + +impl PartialEq for Integer { + fn eq(&self, other: &Integer) -> bool { + self.value == other.value + } +} + +impl + Copy> PartialEq for Integer { + fn eq(&self, other: &T) -> bool { + self.value == (*other).into() + } +} + +impl Eq for Integer {} + +impl Integer { + pub fn new() -> Self { + Self { value: 0, width: 128 } + } + + pub fn new_with_value(value: impl Into, width: impl Into>) -> Self { + Self { + value: value.into(), + width: width.into().unwrap_or(128), + } + } + + pub fn new_with_width(width: u8) -> Option { + if width != 0 && width <= 128 { + Some(Self { value: 0, width }) + } else { + None + } + } + + pub fn width(&self) -> u8 { + self.width + } + + pub fn set_width(&mut self, width: u8) { + if width != 0 && width <= 128 { + self.value &= (1 << width) - 1 + } + } +} diff --git a/src/lib.rs b/src/lib.rs new file mode 100644 index 0000000..a498bf7 --- /dev/null +++ b/src/lib.rs @@ -0,0 +1,74 @@ +#![feature(nll, try_from, vec_remove_item)] + +//! Logical is a digital network simulator. It is named after the german word "Logical" which +//! describes a puzzle that follows the rules of logic. +//! +//! You can build arbitrary complex networks, which then can be simulated. It supports Ieee1164 +//! conform values, like strong and weak drives, uninitialized, high impedance and don't care logic. +//! For more information about these take a look at [`Ieee1164`] Type +//! +//! It is also possible to generate tracefiles in various formats, see the the [`dump`] module. +//! +//! # Usage +//! +//! This crate will be on [crates.io](https://crates.io/crates/logical) and can be used by adding +//! `logical` to your dependencies in your projects `Cargo.toml`. +//! +//! ```toml +//! [dependencies] +//! logical = "0.1" +//! ``` +//! +//! Afterwards you can use it in your 2018-rust-project +//! +//! ```rust,ignore +//! use logical +//! ``` +//! +//! # Example: connect one port to an other +//! +//! ```rust +//! use logical::{Ieee1164, Port, Signal, Updateable}; +//! use logical::direction::{Input, Output}; +//! +//! let from = Port::<_, Output>::new(Ieee1164::from('1')); +//! let to = Port::<_, Input>::default(); +//! let mut signal = Signal::new(); +//! +//! signal.connect_as_input(&from); +//! signal.connect_as_output(&to); +//! +//! signal.update(); +//! +//! assert_eq!(Ieee1164::from('1'), to.value()); +//! ``` +//! + +#[macro_use] +mod mac; +pub mod dump; +mod integer; +mod logicbit; +pub(self) mod port; +mod reactor; +mod signal; + +pub mod gates; +pub mod models; + +pub use self::integer::Integer; +pub use self::logicbit::{Ieee1164, Ieee1164Value, Resolve}; +pub use self::port::Port; +pub use self::reactor::Reactor; +pub use self::signal::Signal; + +pub trait Updateable { + fn update(&mut self); +} + +pub mod direction { + pub use super::port::{Dir, InOut, Input, MaybeRead, MaybeWrite, Off, Output, PortDirection, Read, Write}; +} + +pub type IeeeSignal = Signal; +pub type IntegerSignal = Signal; diff --git a/src/logicbit/ieee1164.rs b/src/logicbit/ieee1164.rs new file mode 100644 index 0000000..d299f75 --- /dev/null +++ b/src/logicbit/ieee1164.rs @@ -0,0 +1,298 @@ +#![allow(clippy::just_underscores_and_digits)] + +use super::{Ieee1164Value, Resolve}; +use std::fmt; +use std::ops::{BitAnd, BitOr, BitXor, Not}; + +macro_rules! expand_op_ieee1164 { + ($func_name:ident, $trait_name:ident, $fn_name:ident) => { + expand_op!($func_name, $trait_name, $fn_name, Ieee1164, Ieee1164, Ieee1164); + }; +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum Ieee1164 { + Uninitialized, + Strong(Ieee1164Value), + Weak(Ieee1164Value), + HighImpedance, + DontCare, +} + +impl Default for Ieee1164 { + fn default() -> Self { + Ieee1164::Uninitialized + } +} + +impl From for Ieee1164 { + fn from(c: char) -> Self { + match c.to_ascii_lowercase() { + 'u' => Ieee1164::Uninitialized, + '0' => Ieee1164::Strong(Ieee1164Value::Zero), + '1' => Ieee1164::Strong(Ieee1164Value::One), + 'z' => Ieee1164::HighImpedance, + 'w' => Ieee1164::Weak(Ieee1164Value::Unknown), + 'l' => Ieee1164::Weak(Ieee1164Value::Zero), + 'h' => Ieee1164::Weak(Ieee1164Value::One), + '*' | '-' => Ieee1164::DontCare, + 'x' | _ => Ieee1164::Strong(Ieee1164Value::Unknown), + } + } +} + +impl<'a> From<&'a Ieee1164> for char { + fn from(i: &Ieee1164) -> Self { + match *i { + Ieee1164::Uninitialized => 'U', + Ieee1164::Strong(Ieee1164Value::Unknown) => 'X', + Ieee1164::Strong(Ieee1164Value::Zero) => '0', + Ieee1164::Strong(Ieee1164Value::One) => '1', + Ieee1164::HighImpedance => 'Z', + Ieee1164::Weak(Ieee1164Value::Unknown) => 'W', + Ieee1164::Weak(Ieee1164Value::Zero) => 'L', + Ieee1164::Weak(Ieee1164Value::One) => 'H', + Ieee1164::DontCare => '-', + } + } +} + +const _U: Ieee1164 = Ieee1164::Uninitialized; +const _X: Ieee1164 = Ieee1164::Strong(Ieee1164Value::Unknown); +const _0: Ieee1164 = Ieee1164::Strong(Ieee1164Value::Zero); +const _1: Ieee1164 = Ieee1164::Strong(Ieee1164Value::One); +const _Z: Ieee1164 = Ieee1164::HighImpedance; +const _W: Ieee1164 = Ieee1164::Weak(Ieee1164Value::Unknown); +const _L: Ieee1164 = Ieee1164::Weak(Ieee1164Value::Zero); +const _H: Ieee1164 = Ieee1164::Weak(Ieee1164Value::One); +const _D: Ieee1164 = Ieee1164::DontCare; + +fn and(a: Ieee1164, b: Ieee1164) -> Ieee1164 { + const TTABLE: [[Ieee1164; 9]; 9] = [ + // U X 0 1 Z W L H - + [_U, _U, _0, _U, _U, _U, _0, _U, _U], // U + [_U, _X, _0, _X, _X, _X, _0, _X, _X], // X + [_0, _0, _0, _0, _0, _0, _0, _0, _0], // 0 + [_U, _X, _0, _1, _X, _X, _0, _1, _X], // 1 + [_U, _X, _0, _X, _X, _X, _0, _X, _X], // Z + [_U, _X, _0, _X, _X, _X, _0, _X, _X], // W + [_0, _0, _0, _0, _0, _0, _0, _0, _0], // L + [_U, _X, _0, _1, _X, _X, _0, _1, _X], // H + [_U, _X, _0, _X, _X, _X, _0, _X, _X], // - + ]; + + TTABLE[a.to_index()][b.to_index()] +} +expand_op_ieee1164!(and, BitAnd, bitand); + +fn or(a: Ieee1164, b: Ieee1164) -> Ieee1164 { + const TTABLE: [[Ieee1164; 9]; 9] = [ + // U X 0 1 Z W L H - + [_U, _U, _U, _1, _U, _U, _U, _1, _U], // U + [_U, _X, _X, _1, _X, _X, _X, _1, _X], // X + [_U, _X, _0, _1, _X, _X, _0, _1, _X], // 0 + [_1, _1, _1, _1, _1, _1, _1, _1, _1], // 1 + [_U, _X, _X, _1, _X, _X, _X, _1, _X], // Z + [_U, _X, _X, _1, _X, _X, _X, _1, _X], // W + [_U, _X, _0, _1, _X, _X, _0, _1, _X], // L + [_1, _1, _1, _1, _1, _1, _1, _1, _1], // H + [_U, _X, _X, _1, _X, _X, _X, _1, _X], // - + ]; + + TTABLE[a.to_index()][b.to_index()] +} +expand_op_ieee1164!(or, BitOr, bitor); + +fn xor(a: Ieee1164, b: Ieee1164) -> Ieee1164 { + const TTABLE: [[Ieee1164; 9]; 9] = [ + // U X 0 1 Z W L H - + [_U, _U, _U, _U, _U, _U, _U, _U, _U], // U + [_U, _X, _X, _X, _X, _X, _X, _X, _X], // X + [_U, _X, _0, _1, _X, _X, _0, _1, _X], // 0 + [_U, _X, _1, _0, _X, _X, _1, _0, _X], // 1 + [_U, _X, _X, _X, _X, _X, _X, _X, _X], // Z + [_U, _X, _X, _X, _X, _X, _X, _X, _X], // W + [_U, _X, _0, _1, _X, _X, _0, _1, _X], // L + [_U, _X, _1, _0, _X, _X, _1, _0, _X], // H + [_U, _X, _X, _X, _X, _X, _X, _X, _X], // - + ]; + + TTABLE[a.to_index()][b.to_index()] +} +expand_op_ieee1164!(xor, BitXor, bitxor); + +fn not(i: Ieee1164) -> Ieee1164 { + match i { + Ieee1164::Uninitialized => Ieee1164::Uninitialized, + Ieee1164::Weak(Ieee1164Value::Zero) | Ieee1164::Strong(Ieee1164Value::Zero) => { + Ieee1164::Strong(Ieee1164Value::One) + } + Ieee1164::Weak(Ieee1164Value::One) | Ieee1164::Strong(Ieee1164Value::One) => { + Ieee1164::Strong(Ieee1164Value::Zero) + } + Ieee1164::Strong(Ieee1164Value::Unknown) + | Ieee1164::HighImpedance + | Ieee1164::Weak(Ieee1164Value::Unknown) + | Ieee1164::DontCare => Ieee1164::Strong(Ieee1164Value::Unknown), + } +} +impl Not for Ieee1164 { + type Output = Self; + fn not(self) -> Self::Output { + not(self) + } +} +impl<'a> Not for &'a Ieee1164 { + type Output = Ieee1164; + fn not(self) -> Self::Output { + not(*self) + } +} + +fn resolve(a: Ieee1164, b: Ieee1164) -> Ieee1164 { + const TTABLE: [[Ieee1164; 9]; 9] = [ + // U X 0 1 Z W L H - + [_U, _U, _U, _U, _U, _U, _U, _U, _U], // U + [_U, _X, _X, _X, _X, _X, _X, _X, _X], // X + [_U, _X, _0, _X, _0, _0, _0, _0, _X], // 0 + [_U, _X, _X, _1, _1, _1, _1, _1, _X], // 1 + [_U, _X, _0, _1, _Z, _W, _L, _H, _X], // Z + [_U, _X, _0, _1, _W, _W, _W, _W, _X], // W + [_U, _X, _0, _1, _L, _W, _L, _W, _X], // L + [_U, _X, _0, _1, _H, _W, _W, _H, _X], // H + [_U, _X, _X, _X, _X, _X, _X, _X, _X], // - + ]; + TTABLE[a.to_index()][b.to_index()] +} +expand_resolve_op!(resolve, Ieee1164, Ieee1164, Ieee1164, _Z); + +impl fmt::Display for Ieee1164 { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "<{}>", char::from(self)) + } +} + +impl Ieee1164 { + fn to_index(self) -> usize { + match self { + Ieee1164::Uninitialized => 0, + Ieee1164::Strong(Ieee1164Value::Unknown) => 1, + Ieee1164::Strong(Ieee1164Value::Zero) => 2, + Ieee1164::Strong(Ieee1164Value::One) => 3, + Ieee1164::HighImpedance => 4, + Ieee1164::Weak(Ieee1164Value::Unknown) => 5, + Ieee1164::Weak(Ieee1164Value::Zero) => 6, + Ieee1164::Weak(Ieee1164Value::One) => 7, + Ieee1164::DontCare => 8, + } + } +} + +#[allow(non_snake_case)] +impl Ieee1164 { + pub fn is_UXZ(self) -> bool { + !(self.is_1H() || self.is_0L()) + } + + pub fn is_01(self) -> bool { + self.is_0() || self.is_1() + } + + pub fn is_1H(self) -> bool { + self.is_1() || self.is_H() + } + + pub fn is_0L(self) -> bool { + self.is_0() || self.is_L() + } + + pub fn is_U(self) -> bool { + self == _U + } + + pub fn is_X(self) -> bool { + self == _X + } + + pub fn is_0(self) -> bool { + self == _0 + } + + pub fn is_1(self) -> bool { + self == _1 + } + + pub fn is_Z(self) -> bool { + self == _Z + } + + pub fn is_W(self) -> bool { + self == _W + } + + pub fn is_L(self) -> bool { + self == _L + } + + pub fn is_H(self) -> bool { + self == _H + } + + pub fn is_D(self) -> bool { + self == _D + } +} + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + fn add() { + assert_eq!(Ieee1164::from('0'), Ieee1164::from('x') & Ieee1164::from('0')); + } + + #[test] + fn or() { + assert_eq!(Ieee1164::from('1'), Ieee1164::from('L') | Ieee1164::from('H')) + } + + #[test] + fn xor() { + let a = Ieee1164::from('1'); + let b = Ieee1164::from('1'); + assert_eq!(Ieee1164::from('0'), a ^ b); + //TODO + } + + #[test] + fn not() { + //TODO + } + + #[test] + fn is_01() { + assert!(!Ieee1164::from('u').is_01()); + assert!(Ieee1164::from('0').is_01()); + assert!(Ieee1164::from('1').is_01()); + assert!(!Ieee1164::from('z').is_01()); + assert!(!Ieee1164::from('w').is_01()); + assert!(!Ieee1164::from('l').is_01()); + assert!(!Ieee1164::from('h').is_01()); + assert!(!Ieee1164::from('-').is_01()); + assert!(!Ieee1164::from('x').is_01()); + } + + #[test] + fn is_uxz() { + assert!(Ieee1164::from('u').is_UXZ()); + assert!(!Ieee1164::from('0').is_UXZ()); + assert!(!Ieee1164::from('1').is_UXZ()); + assert!(Ieee1164::from('z').is_UXZ()); + assert!(Ieee1164::from('w').is_UXZ()); + assert!(!Ieee1164::from('l').is_UXZ()); + assert!(!Ieee1164::from('h').is_UXZ()); + assert!(Ieee1164::from('-').is_UXZ()); + assert!(Ieee1164::from('x').is_UXZ()); + } +} diff --git a/src/logicbit/mac.rs b/src/logicbit/mac.rs new file mode 100644 index 0000000..1c11382 --- /dev/null +++ b/src/logicbit/mac.rs @@ -0,0 +1,40 @@ +macro_rules! expand_resolve_op { + ($func_name:ident, $for_type:ty, $output_type:ty, $rhs:ty, $initial:ident) => { + impl Resolve<$rhs> for $for_type { + type Output = $output_type; + fn resolve(self, rhs: $rhs) -> Self::Output { + $func_name(self, rhs) + } + fn initial_value(&self) -> Self::Output { + $initial + } + } + impl<'a> Resolve<$rhs> for &'a $for_type { + type Output = $output_type; + fn resolve(self, rhs: $rhs) -> Self::Output { + $func_name(*self, rhs) + } + fn initial_value(&self) -> Self::Output { + $initial + } + } + impl<'b> Resolve<&'b $rhs> for $for_type { + type Output = $output_type; + fn resolve(self, rhs: &'b $rhs) -> Self::Output { + $func_name(self, *rhs) + } + fn initial_value(&self) -> Self::Output { + $initial + } + } + impl<'a, 'b> Resolve<&'b $rhs> for &'a $for_type { + type Output = $output_type; + fn resolve(self, rhs: &'b $rhs) -> Self::Output { + $func_name(*self, *rhs) + } + fn initial_value(&self) -> Self::Output { + $initial + } + } + }; +} diff --git a/src/logicbit/mod.rs b/src/logicbit/mod.rs new file mode 100644 index 0000000..4f6f360 --- /dev/null +++ b/src/logicbit/mod.rs @@ -0,0 +1,17 @@ +#[macro_use] +mod mac; +mod ieee1164; +mod tvlogic; + +pub use self::ieee1164::Ieee1164; +pub use self::tvlogic::Ieee1164Value; + +/// This trait is similar to `Add`, `Sub`, `Mul`, ... and is used to describe how values on the +/// same line should be resolved to one `T`. +/// +/// It is required to be commutative! (e.g. `A.resolve(B) == B.resolve(A)`) +pub trait Resolve { + type Output: ?Sized; + fn resolve(self, rhs: RHS) -> Self::Output; + fn initial_value(&self) -> Self::Output; +} diff --git a/src/logicbit/tvlogic.rs b/src/logicbit/tvlogic.rs new file mode 100644 index 0000000..3186dc1 --- /dev/null +++ b/src/logicbit/tvlogic.rs @@ -0,0 +1,161 @@ +#![allow(clippy::just_underscores_and_digits)] + +use std::fmt; +use std::ops::{BitAnd, BitOr, BitXor, Not}; + +macro_rules! expand_op_ieee1164value { + ($func_name:ident, $trait_name:ident, $fn_name:ident) => { + expand_op!( + $func_name, + $trait_name, + $fn_name, + Ieee1164Value, + Ieee1164Value, + Ieee1164Value + ); + }; +} + +/// An Ieee1164Value is either `Zero`, `One` or `Unknown`, also known as Three-valued logic. +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +pub enum Ieee1164Value { + Zero, + One, + Unknown, +} + +use self::Ieee1164Value as Ie; + +const _0: Ieee1164Value = Ieee1164Value::Zero; +const _1: Ieee1164Value = Ieee1164Value::One; +const _U: Ieee1164Value = Ieee1164Value::Unknown; + +impl Default for Ie { + fn default() -> Self { + Ie::Unknown + } +} + +impl fmt::Display for Ieee1164Value { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!( + f, + "{}", + match *self { + Ie::Zero => '0', + Ie::One => '1', + Ie::Unknown => 'U', + } + ) + } +} + +fn and(a: Ie, b: Ie) -> Ie { + match (a, b) { + (_0, _) | (_, _0) => _0, + (_1, _1) => _1, + _ => _U, + } +} +expand_op_ieee1164value!(and, BitAnd, bitand); + +fn or(a: Ie, b: Ie) -> Ie { + match (a, b) { + (_1, _) | (_, _1) => _1, + (_0, _0) => _0, + _ => _U, + } +} +expand_op_ieee1164value!(or, BitOr, bitor); + +fn not(a: Ie) -> Ie { + match a { + _0 => _1, + _U => _U, + _1 => _0, + } +} +impl Not for Ieee1164Value { + type Output = Self; + fn not(self) -> Self::Output { + not(self) + } +} +impl<'a> Not for &'a Ieee1164Value { + type Output = Ieee1164Value; + fn not(self) -> Self::Output { + not(*self) + } +} + +fn xor(a: Ie, b: Ie) -> Ie { + match (a, b) { + (_U, _) | (_, _U) => _U, + (a, b) if a == b => _0, + _ => _1, + } +} +expand_op_ieee1164value!(xor, BitXor, bitxor); + +//TODO: aehm, how to resolve without inital value?! +#[allow(unused)] +fn resolve(a: Ie, b: Ie) -> Ie { + match (a, b) { + (a, b) if a == b => a, + _ => _U, + } +} + +#[cfg(test)] +mod tests { + use super::*; + + const BIN_VAL: [[Ie; 2]; 9] = [ + [_0, _0], + [_0, _1], + [_0, _U], + [_1, _0], + [_1, _1], + [_1, _U], + [_U, _0], + [_U, _1], + [_U, _U], + ]; + + fn test(test_vector: &[Ie; 9], operator: &str, func: fn(Ie, Ie) -> Ie) { + for ([a, b], e) in BIN_VAL.iter().zip(test_vector) { + assert_eq!(func(*a, *b), *e, "{} {} {} ≠ {}", a, operator, b, e); + } + } + + #[test] + fn t_and() { + const EXPECTED: [Ie; 9] = [_0, _0, _0, _0, _1, _U, _0, _U, _U]; + test(&EXPECTED, "&", and); + } + + #[test] + fn t_or() { + const EXPECTED: [Ie; 9] = [_0, _1, _U, _1, _1, _1, _U, _1, _U]; + test(&EXPECTED, "|", or); + } + + #[test] + fn t_xor() { + const EXPECTED: [Ie; 9] = [_0, _1, _U, _1, _0, _U, _U, _U, _U]; + test(&EXPECTED, "⊻", xor); + } + + #[test] + fn t_not() { + assert_eq!(_1, not(_0)); + assert_eq!(_0, not(_1)); + assert_eq!(_U, not(_U)); + } + + #[test] + fn t_resolve() { + const EXPECTED: [Ie; 9] = [_0, _U, _U, _U, _1, _U, _U, _U, _U]; + test(&EXPECTED, "resolves", resolve); + } +} diff --git a/src/mac.rs b/src/mac.rs new file mode 100644 index 0000000..962f689 --- /dev/null +++ b/src/mac.rs @@ -0,0 +1,116 @@ +macro_rules! expand_op { + ($func_name:ident, $trait_name:ident, $fn_name:ident, $for_type:ty, $output_type:ty, $rhs:ty) => { + impl $trait_name<$rhs> for $for_type { + type Output = $output_type; + fn $fn_name(self, rhs: $rhs) -> Self::Output { + $func_name(self, rhs) + } + } + impl<'a> $trait_name<$rhs> for &'a $for_type { + type Output = $output_type; + fn $fn_name(self, rhs: $rhs) -> Self::Output { + $func_name(*self, rhs) + } + } + impl<'b> $trait_name<&'b $rhs> for $for_type { + type Output = $output_type; + fn $fn_name(self, rhs: &'b $rhs) -> Self::Output { + $func_name(self, *rhs) + } + } + impl<'a, 'b> $trait_name<&'b $rhs> for &'a $for_type { + type Output = $output_type; + fn $fn_name(self, rhs: &'b $rhs) -> Self::Output { + $func_name(*self, *rhs) + } + } + }; +} + +#[allow(unused_macros)] +macro_rules! from_prim { + ($t:expr, $u:ident, $s:ident) => { + impl From<$u> for LogicVector { + fn from(v: $u) -> LogicVector { + LogicVector::new_from_value($t, u64::from(v)) + } + } + impl From<$s> for LogicVector { + fn from(v: $s) -> LogicVector { + LogicVector::new_from_value($t, v as u64) + } + } + }; +} + +#[allow(unused_macros)] +macro_rules! into_prim { + ($t:expr, $u:ident, $s:ident) => { + impl TryFrom for $u { + type Error = VectorError; + fn try_from(lv: LogicVector) -> Result { + //TODO maybe without string, could be improved here + if lv.bit_width() > $t { + return Err(VectorError::Overflow); + } + let mut str = String::from_iter(lv.data.iter().take($t).map(char::from)); + if !lv.is_01() { + return Err(VectorError::HasUXZ); + } + match $u::from_str_radix(str.deref_mut(), 2) { + Ok(e) => Ok(e), + _ => Err(VectorError::Other), + } //TODO hae?! + } + } + impl<'a> TryFrom<&'a LogicVector> for $u { + type Error = VectorError; + fn try_from(lv: &'a LogicVector) -> Result { + if lv.bit_width() > $t { + return Err(VectorError::Overflow); + } + let mut str = String::from_iter(lv.data.iter().take($t).map(char::from)); + if !lv.is_01() { + return Err(VectorError::HasUXZ); + } + match $u::from_str_radix(str.deref_mut(), 2) { + Ok(e) => Ok(e), + _ => Err(VectorError::Other), + } //TODO hae?! + } + } + impl TryFrom for $s { + type Error = VectorError; + fn try_from(lv: LogicVector) -> Result { + if lv.bit_width() > $t { + return Err(VectorError::Overflow); + } + let mut str = String::from_iter(lv.data.iter().take($t).map(char::from)); + if !lv.is_01() { + return Err(VectorError::HasUXZ); + } + match $u::from_str_radix(str.deref_mut(), 2) { + Ok(e) => Ok(e as $s), + _ => Err(VectorError::Other), + } //TODO hae?! + } + } + + impl<'a> TryFrom<&'a LogicVector> for $s { + type Error = VectorError; + fn try_from(lv: &'a LogicVector) -> Result { + if lv.bit_width() > $t { + return Err(VectorError::Overflow); + } + let mut str = String::from_iter(lv.data.iter().take($t).map(char::from)); + if !lv.is_01() { + return Err(VectorError::HasUXZ); + } + match $u::from_str_radix(str.deref_mut(), 2) { + Ok(e) => Ok(e as $s), + _ => Err(VectorError::Other), + } //TODO hae?! + } + } + }; +} diff --git a/src/models/inputs/mod.rs b/src/models/inputs/mod.rs new file mode 100644 index 0000000..f72944d --- /dev/null +++ b/src/models/inputs/mod.rs @@ -0,0 +1,3 @@ +mod switch; + +pub use self::switch::Switch; diff --git a/src/models/inputs/switch.rs b/src/models/inputs/switch.rs new file mode 100644 index 0000000..7118269 --- /dev/null +++ b/src/models/inputs/switch.rs @@ -0,0 +1,14 @@ +use crate::port::Output; +use crate::Port; + +#[derive(Debug, Default)] +pub struct Switch { + pub output: Port, + _private: (), +} + +impl Switch { + pub fn set_value(&mut self, value: T) { + self.output.set_value(value); + } +} diff --git a/src/models/mod.rs b/src/models/mod.rs new file mode 100644 index 0000000..20e155b --- /dev/null +++ b/src/models/mod.rs @@ -0,0 +1,2 @@ +pub mod inputs; +pub mod outputs; diff --git a/src/models/outputs/led.rs b/src/models/outputs/led.rs new file mode 100644 index 0000000..b002f88 --- /dev/null +++ b/src/models/outputs/led.rs @@ -0,0 +1,14 @@ +use crate::port::Input; +use crate::Port; + +#[derive(Debug, Default)] +pub struct Led { + pub input: Port, + _private: (), +} + +impl Led { + pub fn value(&self) -> T { + self.input.value() + } +} diff --git a/src/models/outputs/mod.rs b/src/models/outputs/mod.rs new file mode 100644 index 0000000..173d5e3 --- /dev/null +++ b/src/models/outputs/mod.rs @@ -0,0 +1,3 @@ +mod led; + +pub use self::led::Led; diff --git a/src/port/mod.rs b/src/port/mod.rs new file mode 100644 index 0000000..374f8b0 --- /dev/null +++ b/src/port/mod.rs @@ -0,0 +1,15 @@ +use std::sync::RwLock; + +mod portconnector; +mod portdirection; +mod pport; + +pub(crate) use self::portconnector::PortConnector; + +pub use self::portdirection::{Dir, InOut, Input, MaybeRead, MaybeWrite, Off, Output, PortDirection, Read, Write}; +pub use self::pport::Port; + +#[derive(Debug)] +pub(self) struct InnerPort { + value: RwLock, +} diff --git a/src/port/portconnector.rs b/src/port/portconnector.rs new file mode 100644 index 0000000..aa13158 --- /dev/null +++ b/src/port/portconnector.rs @@ -0,0 +1,70 @@ +use std::fmt; +use std::marker::PhantomData; +use std::sync::Weak; + +use super::portdirection::{Dir, MaybeRead, MaybeWrite, Read, Write}; +use super::{portdirection::PortDirection, InnerPort, Port}; + +#[derive(Clone)] +pub(crate) struct PortConnector { + inner: Weak>, + _marker: PhantomData, +} + +impl fmt::Debug for PortConnector { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "PortConnector {{ value: {:?} }} ", self.to_port(),) + } +} + +impl PartialEq for PortConnector { + fn eq(&self, other: &PortConnector) -> bool { + match (self.to_port(), other.to_port()) { + (Some(ref a), Some(ref b)) => a.eq(b), + // even when both ports are not upgradeable does not mean, that they are equal! + _ => false, + } + } +} + +impl PortConnector { + pub(super) fn new_with_weak(weak: Weak>) -> Self { + PortConnector { + inner: weak, + _marker: PhantomData, + } + } +} + +impl PortConnector { + fn to_port(&self) -> Option> { + self.inner.upgrade().map(Port::new_with_arc) + } + + pub fn is_valid(&self) -> bool { + self.inner.upgrade().is_some() + } +} + +impl PortConnector> +where + T: Clone, + W: MaybeWrite, + Dir: PortDirection, +{ + pub fn value(&self) -> Option { + self.inner.upgrade().map(|i| i.value.read().unwrap().clone()) + } +} + +impl PortConnector> +where + R: MaybeRead, + Dir: PortDirection, +{ + pub fn set_value(&mut self, value: T) { + if let Some(port) = self.to_port() { + *port.inner.value.write().unwrap() = value; + } + } +} diff --git a/src/port/portdirection.rs b/src/port/portdirection.rs new file mode 100644 index 0000000..71bd886 --- /dev/null +++ b/src/port/portdirection.rs @@ -0,0 +1,53 @@ +use std::fmt::Debug; +use std::hash::Hash; +use std::marker::PhantomData; + +mod private { + pub trait Sealed {} +} + +use self::private::Sealed; + +#[derive(Default, Debug, Clone, Copy, Eq, PartialEq, Hash)] +pub struct Read; +#[derive(Default, Debug, Clone, Copy, Eq, PartialEq, Hash)] +pub struct Write; +#[derive(Default, Debug, Clone, Copy, Eq, PartialEq, Hash)] +pub struct Off; + +pub trait MaybeRead {} +pub trait MaybeWrite {} + +impl MaybeRead for Read {} +impl MaybeWrite for Write {} +impl MaybeRead for Off {} +impl MaybeWrite for Off {} + +pub trait PortDirection: Default + Debug + PartialEq + Eq + Hash + Clone + Copy + Sealed { + type Opposite: PortDirection; + const IS_INPUT: bool = false; + const IS_OUTPUT: bool = false; + const IS_INOUT: bool = false; +} + +#[derive(Default, Debug, Clone, Copy, Eq, PartialEq, Hash)] +pub struct Dir(PhantomData<(R, W)>); + +impl Sealed for Dir {} + +impl PortDirection for Dir { + type Opposite = Self; + const IS_INOUT: bool = true; +} +impl PortDirection for Dir { + type Opposite = Dir; + const IS_INPUT: bool = true; +} +impl PortDirection for Dir { + type Opposite = Dir; + const IS_OUTPUT: bool = true; +} + +pub type Input = Dir; +pub type Output = Dir; +pub type InOut = Dir; diff --git a/src/port/pport.rs b/src/port/pport.rs new file mode 100644 index 0000000..0198347 --- /dev/null +++ b/src/port/pport.rs @@ -0,0 +1,196 @@ +use std::convert::TryInto; +use std::marker::PhantomData; +use std::sync::{Arc, RwLock}; + +use super::InnerPort; + +use crate::direction::{Dir, InOut, Input, MaybeRead, MaybeWrite, Output, PortDirection, Read, Write}; +use crate::port::portconnector::PortConnector; + +#[derive(Debug, Clone)] +pub struct Port { + pub(super) inner: Arc>, + _marker: PhantomData, +} + +impl PartialEq for Port { + fn eq(&self, other: &Port) -> bool { + Arc::ptr_eq(&self.inner, &other.inner) + } +} + +impl Eq for Port {} + +impl Default for Port { + fn default() -> Self { + Port::new(T::default()) + } +} + +impl Port { + pub fn new(value: T) -> Self { + Port { + inner: Arc::new(InnerPort { + value: RwLock::new(value), + }), + _marker: PhantomData, + } + } +} + +impl Port { + pub(super) fn new_with_arc(arc: Arc>) -> Self { + Port { + inner: arc, + _marker: PhantomData, + } + } +} + +impl Port> +where + T: Clone, + W: MaybeWrite, + Dir: PortDirection, +{ + pub fn value(&self) -> T { + self.inner.value.read().unwrap().clone() + } +} + +impl Port> +where + R: MaybeRead, + Dir: PortDirection, +{ + pub fn set_value(&mut self, value: T) { + *self.inner.value.write().unwrap() = value; + } +} + +impl Into> for Port { + fn into(self) -> PortConnector::Opposite> { + PortConnector::new_with_weak(Arc::downgrade(&self.inner)) + } +} + +impl Into> for Port { + fn into(self) -> PortConnector { + PortConnector::new_with_weak(Arc::downgrade(&self.inner)) + } +} + +impl Into> for Port { + fn into(self) -> PortConnector { + PortConnector::new_with_weak(Arc::downgrade(&self.inner)) + } +} + +impl TryInto> for Port +where + D: PortDirection, +{ + type Error = (); + + fn try_into(self) -> Result, >>::Error> { + if D::IS_OUTPUT || D::IS_INOUT { + Ok(PortConnector::new_with_weak(Arc::downgrade(&self.inner))) + } else { + Err(()) + } + } +} + +impl TryInto> for Port +where + D: PortDirection, +{ + type Error = (); + + fn try_into(self) -> Result, >>::Error> { + if D::IS_INPUT || D::IS_INOUT { + Ok(PortConnector::new_with_weak(Arc::downgrade(&self.inner))) + } else { + Err(()) + } + } +} + +impl TryInto> for &Port +where + D: PortDirection, +{ + type Error = (); + + fn try_into(self) -> Result, >>::Error> { + if D::IS_OUTPUT || D::IS_INOUT { + Ok(PortConnector::new_with_weak(Arc::downgrade(&self.inner))) + } else { + Err(()) + } + } +} + +impl TryInto> for &Port +where + D: PortDirection, +{ + type Error = (); + + fn try_into(self) -> Result, >>::Error> { + if D::IS_INPUT || D::IS_INOUT { + Ok(PortConnector::new_with_weak(Arc::downgrade(&self.inner))) + } else { + Err(()) + } + } +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::port::portdirection::InOut; + use crate::port::Input; + use crate::port::Output; + use crate::Integer; + + #[test] + fn reading() { + let s = Port::<_, Input>::new(3); + assert_eq!(s.value(), 3); + } + + #[test] + fn set() { + let mut s = Port::<_, Output>::default(); + s.set_value(Integer::new_with_value(3u8, 8)); + assert_eq!(*s.inner.value.read().unwrap(), 3u8); + } + + #[test] + fn reset() { + let mut s = Port::<_, InOut>::default(); + s.set_value(Integer::new_with_value(5u8, 8)); + assert_eq!(s.value(), 5u8); + s.set_value(Integer::new_with_value(6u8, 8)); + assert_eq!(s.value(), 6u8); + } + + #[test] + fn reset_before_reading() { + let mut s = Port::<_, InOut>::default(); + s.set_value(Integer::new_with_value(4u8, 8)); + s.set_value(Integer::new_with_value(8u8, 8)); + assert_eq!(s.value(), 8u8); + } + + fn write_on_input_should_not_compile() { + // ```compile_fail + // use logical::{Port, Integer, port::Output}; + // let mut s = Port::::new(); + // s.set_value(Integer::new_with_value(4u8, 8)); + // assert_eq!(Integer::default(), s.value()) + // ``` + let _ = 3; + } +} diff --git a/src/reactor.rs b/src/reactor.rs new file mode 100644 index 0000000..2232842 --- /dev/null +++ b/src/reactor.rs @@ -0,0 +1,22 @@ +use crate::Updateable; + +#[derive(Default)] +pub struct Reactor { + updater: Vec>, +} + +impl Reactor { + pub fn new() -> Self { + Reactor { updater: vec![] } + } + + pub fn tick(&mut self) { + for u in &mut self.updater { + u.update(); + } + } + + pub fn add_updater(&mut self, updater: &T) { + self.updater.push(Box::new(updater.clone())) + } +} diff --git a/src/signal.rs b/src/signal.rs new file mode 100644 index 0000000..339d65c --- /dev/null +++ b/src/signal.rs @@ -0,0 +1,251 @@ +use std::sync::{Arc, RwLock}; + +use crate::logicbit::Resolve; + +use crate::direction::{Dir, Input, MaybeRead, MaybeWrite, Output, Read, Write}; + +use crate::port::PortConnector; +use crate::port::PortDirection; +use crate::{Port, Updateable}; +use std::convert::TryInto; + +#[derive(Debug, Clone)] +pub struct Signal { + inner: Arc>, +} + +#[derive(Debug)] +struct InnerSignal { + input_ports: RwLock>>, + output_ports: RwLock>>, +} + +impl Default for Signal { + fn default() -> Self { + Signal::new() + } +} + +impl Signal { + pub fn new() -> Self { + Signal { + inner: Arc::new(InnerSignal { + input_ports: RwLock::new(vec![]), + output_ports: RwLock::new(vec![]), + }), + } + } + + pub fn connect_as_input(&mut self, port: &Port>) + where + R: MaybeRead, + Dir: PortDirection, + { + let connector = port.try_into().unwrap(); //TODO: how can get rid of `try_into` and use `into` because we know, that this is safe! + let mut guard = self.inner.input_ports.write().unwrap(); + if !guard.contains(&connector) { + guard.push(connector); + } + } + + pub fn connect_as_output(&mut self, port: &Port>) + where + W: MaybeWrite, + Dir: PortDirection, + { + let connector = port.try_into().unwrap(); + let mut guard = self.inner.output_ports.write().unwrap(); + if !guard.contains(&connector) { + guard.push(connector); + } + } + + pub fn disconnect_input(&mut self, port: &Port>) + where + R: MaybeRead, + Dir: PortDirection, + { + let connector = port.try_into().unwrap(); + self.inner.input_ports.write().unwrap().remove_item(&connector); + } + + pub fn disconnect_output(&mut self, port: &Port>) + where + W: MaybeWrite, + Dir: PortDirection, + { + let connector = port.try_into().unwrap(); + self.inner.output_ports.write().unwrap().remove_item(&connector); + } + + fn remove_expired_portconnector(&mut self) { + macro_rules! filter { + ($vec:expr) => { + let mut guard = $vec.write().unwrap(); + let v = std::mem::replace(&mut *guard, vec![]); + *guard = v.into_iter().filter(PortConnector::is_valid).collect() + }; + }; + + filter!(self.inner.input_ports); + filter!(self.inner.output_ports); + } +} + +impl Updateable for Signal +where + for<'a> &'a T: Resolve<&'a T, Output = T>, + T: Clone + std::fmt::Debug, +{ + fn update(&mut self) { + self.remove_expired_portconnector(); + + let in_guard = self.inner.input_ports.write().unwrap(); + + let mut iter = in_guard.iter(); + + let first_port = loop { + if let Some(first) = iter.next() { + if first.is_valid() { + break Some(first); + } + } else { + break None; + } + }; + + if let Some(first) = first_port { + //we hold a read guard, so nobody can mutate our in/inout list, so we are free to use unwrap here + let r = iter + .filter_map(|pc| pc.value()) + .fold(first.value().unwrap(), |e, s| e.resolve(&s)); + + self.inner + .output_ports + .write() + .unwrap() + .iter_mut() + .for_each(|p| p.set_value(r.clone())); + } + } +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::direction::InOut; + use crate::{Ieee1164, Ieee1164Value, Port}; + + #[test] + fn signal_no_value_no_port() { + let mut s = Signal::::new(); + let port = Port::<_, Input>::default(); + s.connect_as_output(&port); + assert_eq!(Ieee1164::default(), port.value()); + s.update(); + assert_eq!(Ieee1164::default(), port.value()); + for _ in 0..1_000 { + s.update(); + assert_eq!(Ieee1164::default(), port.value()); + } + } + + #[test] + fn signal_single_port() { + let i = Port::<_, Input>::default(); + let mut p = Port::<_, Output>::default(); + let mut s = Signal::new(); + + s.connect_as_output(&i); + s.connect_as_input(&p); + assert_eq!(Ieee1164::default(), i.value()); + s.update(); + assert_eq!(Ieee1164::Uninitialized, i.value()); + for _ in 0..1_000 { + s.update(); + assert_eq!(Ieee1164::Uninitialized, i.value()); + } + + let val = Ieee1164::Strong(Ieee1164Value::One); + p.set_value(val); + s.update(); + assert_eq!(val, i.value()); + + for _ in 0..1_000 { + s.update(); + assert_eq!(val, i.value()); + } + } + + #[test] + fn signal_after_remove() { + let val_a = Ieee1164::Strong(Ieee1164Value::One); + let val_b = Ieee1164::Strong(Ieee1164Value::Zero); + let mut p = Port::<_, InOut>::new(val_a); + let o = Port::<_, Input>::default(); + let mut s = Signal::new(); + s.connect_as_input(&p); + s.connect_as_output(&o); + s.update(); + assert_eq!(val_a, o.value()); + + s.disconnect_input(&p); + p.set_value(val_b); + s.update(); + assert_ne!(val_b, o.value()); + } + + #[test] + fn signal_multiple_ports() { + let val_a = Ieee1164::Weak(Ieee1164Value::One); + let val_b = Ieee1164::Strong(Ieee1164Value::Zero); + let p1 = Port::<_, InOut>::new(val_a); + let p2 = Port::<_, InOut>::new(val_b); + let o = Port::<_, Input>::new(Ieee1164::DontCare); + let mut s = Signal::new(); + + s.connect_as_input(&p1); + s.connect_as_input(&p2); + s.connect_as_output(&o); + s.update(); + assert_eq!(val_a.resolve(val_b), o.value()); + } + + #[test] + fn signal_port_out_of_scope() { + let mut s = Signal::new(); + + let val_a = Ieee1164::Strong(Ieee1164Value::One); + let val_b = Ieee1164::Strong(Ieee1164Value::Zero); + + let p1 = Port::<_, InOut>::new(val_a); + let o = Port::<_, Input>::default(); + s.connect_as_input(&p1); + s.connect_as_output(&o); + + { + let p2 = Port::<_, InOut>::new(val_b); + s.connect_as_input(&p2); + s.update(); + assert_eq!(val_a.resolve(val_b), o.value()); + } + + s.update(); + assert_eq!(val_a, o.value()); + } + + #[test] + fn disallow_multiple_connects() { + let mut s = Signal::new(); + + let val = Ieee1164::Strong(Ieee1164Value::One); + let p = Port::<_, InOut>::new(val); + s.connect_as_input(&p); + s.connect_as_input(&p); + assert_eq!(1, s.inner.input_ports.read().unwrap().len()); + + s.connect_as_output(&p); + s.connect_as_output(&p); + assert_eq!(1, s.inner.output_ports.read().unwrap().len()); + } +}