From c3ced4db9de05ee29555714d21874127cabb3957 Mon Sep 17 00:00:00 2001
From: Marcel Hellwig <git@cookiesoft.de>
Date: Tue, 27 Nov 2018 20:45:15 +0100
Subject: [PATCH] add bench, small changes

---
 Cargo.toml                         |  3 +-
 benches/logicvector.rs             | 54 ++++++++++++++++++++++++++++++
 src/lib.rs                         |  4 +++
 src/logicbit/logicvector.rs        | 17 +++++-----
 src/models/rtlib/inputs/ivector.rs |  0
 src/models/rtlib/inputs/mod.rs     |  0
 6 files changed, 68 insertions(+), 10 deletions(-)
 create mode 100644 benches/logicvector.rs
 create mode 100644 src/models/rtlib/inputs/ivector.rs
 create mode 100644 src/models/rtlib/inputs/mod.rs

diff --git a/Cargo.toml b/Cargo.toml
index 0d541d7..ff75ada 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -21,4 +21,5 @@ travis-ci = { repository = "hellow554/logical-rs" }
 chrono = "0.4"
 
 [dev-dependencies]
-proptest = "0.6"
\ No newline at end of file
+proptest = "0.6"
+pretty_assertions = "0.5"
diff --git a/benches/logicvector.rs b/benches/logicvector.rs
new file mode 100644
index 0000000..c1ed312
--- /dev/null
+++ b/benches/logicvector.rs
@@ -0,0 +1,54 @@
+#![feature(test)]
+extern crate test;
+
+use logical::Ieee1164;
+use logical::LogicVector;
+use test::black_box as bb;
+use test::Bencher;
+
+const NITER: u128 = 10_000;
+
+#[bench]
+fn create_from_int(b: &mut Bencher) {
+    b.iter(|| {
+        for i in 0..NITER {
+            bb(LogicVector::from_int_value(i, 128));
+        }
+    });
+}
+
+#[bench]
+fn create_from_vec(b: &mut Bencher) {
+    b.iter(|| {
+        for i in 0..NITER {
+            bb(LogicVector::from(vec![Ieee1164::_U; (i % 128) as usize]));
+        }
+    })
+}
+
+#[bench]
+fn create_from_str(b: &mut Bencher) {
+    b.iter(|| {
+        for i in 0..NITER {
+            bb("U".repeat((i % 128) as usize));
+        }
+    })
+}
+
+#[bench]
+fn create_width(b: &mut Bencher) {
+    b.iter(|| {
+        for i in 0..NITER {
+            bb(LogicVector::with_width((i % 128) as usize + 1));
+        }
+    })
+}
+
+#[bench]
+fn to_u128(b: &mut Bencher) {
+    b.iter(|| {
+        for i in 0..NITER {
+            assert_eq!(Some(i), bb(LogicVector::from_int_value(i, 128)).unwrap().as_u128());
+        }
+    })
+}
\ No newline at end of file
diff --git a/src/lib.rs b/src/lib.rs
index 0bdc7a1..4e269c9 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -71,6 +71,10 @@
 //! assert_eq!(Ieee1164::_0, to.value());
 //! ```
 
+#[cfg(test)]
+#[macro_use]
+extern crate pretty_assertions;
+
 #[macro_use]
 mod mac;
 mod circuit;
diff --git a/src/logicbit/logicvector.rs b/src/logicbit/logicvector.rs
index fa385b4..3e2f58b 100644
--- a/src/logicbit/logicvector.rs
+++ b/src/logicbit/logicvector.rs
@@ -264,7 +264,6 @@ mod tests {
 
     proptest! {
         #[test]
-        #[ignore]
         fn atm_ctor_value(value in 0u64..) {
             let v = LogicVector::with_value(value as u128, 128);
             prop_assert!(v.is_some());
@@ -278,14 +277,14 @@ mod tests {
             let v = LogicVector::with_width(width);
             assert_eq!(width, v.width());
             assert!(v.has_U(), "{:?}", v);
-            assert!(!v.has_X());
-            assert!(!v.has_0());
-            assert!(!v.has_1());
-            assert!(!v.has_Z());
-            assert!(!v.has_W());
-            assert!(!v.has_D());
-            assert!(!v.has_L());
-            assert!(!v.has_H());
+            assert!(!v.has_X(), "{:?}", v);
+            assert!(!v.has_0(), "{:?}", v);
+            assert!(!v.has_1(), "{:?}", v);
+            assert!(!v.has_Z(), "{:?}", v);
+            assert!(!v.has_W(), "{:?}", v);
+            assert!(!v.has_D(), "{:?}", v);
+            assert!(!v.has_L(), "{:?}", v);
+            assert!(!v.has_H(), "{:?}", v);
         }
     }
 
diff --git a/src/models/rtlib/inputs/ivector.rs b/src/models/rtlib/inputs/ivector.rs
new file mode 100644
index 0000000..e69de29
diff --git a/src/models/rtlib/inputs/mod.rs b/src/models/rtlib/inputs/mod.rs
new file mode 100644
index 0000000..e69de29