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Native ARM Co Pro: Implement X SWI Bit #210

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hoglet67 opened this issue May 8, 2024 · 1 comment
Open

Native ARM Co Pro: Implement X SWI Bit #210

hoglet67 opened this issue May 8, 2024 · 1 comment

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@hoglet67
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hoglet67 commented May 8, 2024

See discussion here:
https://stardot.org.uk/forums/viewtopic.php?p=424768#p424768

To correctly handle the X prefix, the SWI handler (in tube-swi.c) would need to install a temporary error handler. This would restore the original error handler, unwind the call and return to the caller with the V bit set. A non-error would also need to restore the original error handler and return with the V bit clear.

See #200 for how this was done in the RISC-V ECall Handler

hoglet67 added a commit that referenced this issue May 13, 2024
Change-Id: I5d603bd39baaff7c31b67a88901a6a2aeb776ccb
hoglet67 added a commit that referenced this issue May 13, 2024
Change-Id: Ib187ecb0fe438b7faf617bbf96fb8c0f6ee230d6
@hoglet67
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Started work on this, in the armnative_xbit branch

It's not currently working, because when generating an error the privilege level reduces to user mode . So the SWI handler ends up completing in user mode, and then hits a privileged instruction which causes an exception.

(Setjmp/Longjmp doesn't preserve the current privilege level)

There probably needs to be a way to specify that an error handler is run in supervisor mode.

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