From 9d8a34c9abb6c13f9bebc28d9c4c10fe512491d4 Mon Sep 17 00:00:00 2001 From: lean Date: Mon, 14 Jun 2021 20:08:28 +0800 Subject: [PATCH] ipq807x: add Xiaomi AX3600 and ath11k support --- package/firmware/ath11k-firmware/Makefile | 77 ++ package/kernel/mac80211/ath.mk | 21 +- target/linux/ipq807x/Makefile | 10 +- .../etc/hotplug.d/firmware/11-ath11k-caldata | 20 + target/linux/ipq807x/base-files/etc/inittab | 5 + .../ipq807x/{config-default => config-5.4} | 206 ++-- .../arm64/boot/dts/qcom/ipq8071-ax3600.dts | 262 ++++++ target/linux/ipq807x/generic/target.mk | 1 + target/linux/ipq807x/image/Makefile | 60 +- ...64-dts-qcom-add-gpio-ranges-property.patch | 42 + ...4-qcom-Re-arrange-dts-nodes-based-on.patch | 734 +++++++++++++++ ...-arm64-dts-ipq8074-enable-sdhci-node.patch | 56 ++ ...-set-BAM-mode-only-if-not-set-alread.patch | 42 + ...bindings-for-ipq6018-apss-clock-cont.patch | 31 + ...-nameservice-to-kernel-from-userspac.patch | 882 ++++++++++++++++++ ...-qrtr-Fix-error-pointer-vs-NULL-bugs.patch | 35 + ....7-net-qrtr-Respond-to-HELLO-message.patch | 104 +++ ...tr-Fix-FIXME-related-to-qrtr_ns_init.patch | 82 ++ ...-Use-size_t-type-for-len-in-da_to_va.patch | 222 +++++ ...-add-support-for-rpmsg-communication.patch | 37 + ...Introduce-helper-to-store-pil-info-i.patch | 190 ++++ ...roc-qcom-pil-info-Fix-shift-overflow.patch | 30 + ...m-Update-PIL-relocation-info-on-load.patch | 102 ++ ...devm_platform_get_and_ioremap_resour.patch | 76 ++ ...m64-dts-ipq8074-add-watchdog-support.patch | 30 + .../101-arm64-dts-ipq8074-add-PRNG-node.patch | 29 + ...64-dts-ipq8074-add-SPMI-arbiter-node.patch | 43 + ...om_spmi-Add-support-for-PMD9655-PMIC.patch | 47 + ...pmi-Add-support-for-VMPWM_CTL-subtyp.patch | 154 +++ ...pmi-Add-support-for-LD011-in-PMD9655.patch | 48 + ...-ipq8074-Add-PMD9655-SPMI-PMIC-nodes.patch | 84 ++ ...-01-clk-qcom-Add-IPQ8074-APSS-driver.patch | 154 +++ ...104-arm64-dts-ipq8074-Add-SMEM-nodes.patch | 65 ++ .../105-arm64-dts-ipq8074-Add-SCM-node.patch | 29 + ...te-hardcoded-param-using-driver-data.patch | 152 +++ ...d-non-pas-wcss-Q6-support-for-QCS404.patch | 809 ++++++++++++++++ ...itly-request-exclusive-reset-control.patch | 91 ++ ...remoteproc-qcom-Add-PRNG-proxy-clock.patch | 204 ++++ ...moteproc-qcom-Add-secure-PIL-support.patch | 192 ++++ ...upport-for-split-q6-m3-wlan-firmware.patch | 153 +++ ...oc-qcom-Add-ssr-subdevice-identifier.patch | 73 ++ ...ate-regmap-offsets-for-halt-register.patch | 129 +++ ...ngs-clock-qcom-Add-reset-for-WCSSAON.patch | 74 ++ .../106-10-clk-qcom-Add-WCSSAON-reset.patch | 74 ++ ...com-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch | 144 +++ .../107-arm64-dts-ipq8074-Add-WLAN-node.patch | 138 +++ .../901-arm64-qcom-dts-add-IPQ8074-dts.patch | 22 + .../patches-5.4/997-device_tree_cmdline.patch | 12 + 48 files changed, 6176 insertions(+), 101 deletions(-) create mode 100644 package/firmware/ath11k-firmware/Makefile create mode 100644 target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata create mode 100644 target/linux/ipq807x/base-files/etc/inittab rename target/linux/ipq807x/{config-default => config-5.4} (79%) create mode 100644 target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts create mode 100644 target/linux/ipq807x/generic/target.mk create mode 100644 target/linux/ipq807x/patches-5.4/0001-v5.7-ARM64-dts-qcom-add-gpio-ranges-property.patch create mode 100644 target/linux/ipq807x/patches-5.4/0002-v5.8-arm64-dts-ipq8074-qcom-Re-arrange-dts-nodes-based-on.patch create mode 100644 target/linux/ipq807x/patches-5.4/0003-v5.9-arm64-dts-ipq8074-enable-sdhci-node.patch create mode 100644 target/linux/ipq807x/patches-5.4/0005-v5.9-mtd-rawnand-qcom-set-BAM-mode-only-if-not-set-alread.patch create mode 100644 target/linux/ipq807x/patches-5.4/0006-v5.9-clk-qcom-Add-DT-bindings-for-ipq6018-apss-clock-cont.patch create mode 100644 target/linux/ipq807x/patches-5.4/0007-v5.7-net-qrtr-Migrate-nameservice-to-kernel-from-userspac.patch create mode 100644 target/linux/ipq807x/patches-5.4/0008-v5.7-net-qrtr-Fix-error-pointer-vs-NULL-bugs.patch create mode 100644 target/linux/ipq807x/patches-5.4/0009-v5.7-net-qrtr-Respond-to-HELLO-message.patch create mode 100644 target/linux/ipq807x/patches-5.4/0010-v5.7-net-qrtr-Fix-FIXME-related-to-qrtr_ns_init.patch create mode 100644 target/linux/ipq807x/patches-5.4/0011-v5.7-remoteproc-Use-size_t-type-for-len-in-da_to_va.patch create mode 100644 target/linux/ipq807x/patches-5.4/0012-v5.8-remoteproc-wcss-add-support-for-rpmsg-communication.patch create mode 100644 target/linux/ipq807x/patches-5.4/0013-v5.9-remoteproc-qcom-Introduce-helper-to-store-pil-info-i.patch create mode 100644 target/linux/ipq807x/patches-5.4/0014-v5.9-remoteproc-qcom-pil-info-Fix-shift-overflow.patch create mode 100644 target/linux/ipq807x/patches-5.4/0015-v5.9-remoteproc-qcom-Update-PIL-relocation-info-on-load.patch create mode 100644 target/linux/ipq807x/patches-5.4/0016-v5.7-drivers-provide-devm_platform_get_and_ioremap_resour.patch create mode 100644 target/linux/ipq807x/patches-5.4/100-arm64-dts-ipq8074-add-watchdog-support.patch create mode 100644 target/linux/ipq807x/patches-5.4/101-arm64-dts-ipq8074-add-PRNG-node.patch create mode 100644 target/linux/ipq807x/patches-5.4/102-01-arm64-dts-ipq8074-add-SPMI-arbiter-node.patch create mode 100644 target/linux/ipq807x/patches-5.4/102-02-regulator-qcom_spmi-Add-support-for-PMD9655-PMIC.patch create mode 100644 target/linux/ipq807x/patches-5.4/102-03-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch create mode 100644 target/linux/ipq807x/patches-5.4/102-04-regulator-qcom_spmi-Add-support-for-LD011-in-PMD9655.patch create mode 100644 target/linux/ipq807x/patches-5.4/102-05-arm64-dts-ipq8074-Add-PMD9655-SPMI-PMIC-nodes.patch create mode 100644 target/linux/ipq807x/patches-5.4/103-01-clk-qcom-Add-IPQ8074-APSS-driver.patch create mode 100644 target/linux/ipq807x/patches-5.4/104-arm64-dts-ipq8074-Add-SMEM-nodes.patch create mode 100644 target/linux/ipq807x/patches-5.4/105-arm64-dts-ipq8074-Add-SCM-node.patch create mode 100644 target/linux/ipq807x/patches-5.4/106-01-remoteproc-qcom-wcss-populate-hardcoded-param-using-driver-data.patch create mode 100644 target/linux/ipq807x/patches-5.4/106-02-remoteproc-qcom-wcss-Add-non-pas-wcss-Q6-support-for-QCS404.patch create mode 100644 target/linux/ipq807x/patches-5.4/106-03-remoteproc-qcom-wcss-explicitly-request-exclusive-reset-control.patch create mode 100644 target/linux/ipq807x/patches-5.4/106-04-remoteproc-qcom-Add-PRNG-proxy-clock.patch create mode 100644 target/linux/ipq807x/patches-5.4/106-05-remoteproc-qcom-Add-secure-PIL-support.patch create mode 100644 target/linux/ipq807x/patches-5.4/106-06-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-firmware.patch create mode 100644 target/linux/ipq807x/patches-5.4/106-07-remoteproc-qcom-Add-ssr-subdevice-identifier.patch create mode 100644 target/linux/ipq807x/patches-5.4/106-08-remoteproc-qcom-Update-regmap-offsets-for-halt-register.patch create mode 100644 target/linux/ipq807x/patches-5.4/106-09-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch create mode 100644 target/linux/ipq807x/patches-5.4/106-10-clk-qcom-Add-WCSSAON-reset.patch create mode 100644 target/linux/ipq807x/patches-5.4/106-11-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch create mode 100644 target/linux/ipq807x/patches-5.4/107-arm64-dts-ipq8074-Add-WLAN-node.patch create mode 100644 target/linux/ipq807x/patches-5.4/901-arm64-qcom-dts-add-IPQ8074-dts.patch create mode 100644 target/linux/ipq807x/patches-5.4/997-device_tree_cmdline.patch diff --git a/package/firmware/ath11k-firmware/Makefile b/package/firmware/ath11k-firmware/Makefile new file mode 100644 index 00000000000000..04ae90bbdbc941 --- /dev/null +++ b/package/firmware/ath11k-firmware/Makefile @@ -0,0 +1,77 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=ath11k-firmware +PKG_SOURCE_DATE:=2020-06-26 +PKG_SOURCE_VERSION:=ac35049edfa9e59fc0aa9988ba12ea91d28241f5 +PKG_MIRROR_HASH:=a5bbe673c7714447df3197de2bc86a09b13d402b89f7f9a813c4b400d897eb9e +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://github.com/kvalo/ath11k-firmware.git + +PKG_MAINTAINER:=Robert Marko + +include $(INCLUDE_DIR)/package.mk + +define Package/ath11k-firmware-default + SECTION:=firmware + CATEGORY:=Firmware + URL:=$(PKG_SOURCE_URL) + DEPENDS:= +endef + +define Package/ath11k-firmware-ipq6018 +$(Package/ath11k-firmware-default) + TITLE:=ath11k firmware for IPQ6018 devices + SECTION:=firmware + CATEGORY:=Firmware +endef + +define Package/ath11k-firmware-ipq8074 +$(Package/ath11k-firmware-default) + TITLE:=ath11k firmware for IPQ8074 devices + SECTION:=firmware + CATEGORY:=Firmware +endef + +define Package/ath11k-firmware-qca6390 +$(Package/ath11k-firmware-default) + TITLE:=ath11k firmware for QCA6390 devices + SECTION:=firmware + CATEGORY:=Firmware +endef + +define Build/Compile + +endef + +define Package/ath11k-firmware-ipq6018/install + $(INSTALL_DIR) $(1)/lib/firmware/IPQ6018 + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/IPQ6018/hw1.0/board-2.bin \ + $(1)/lib/firmware/IPQ6018/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/IPQ6018/hw1.0/2.1.0.1/WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2/* \ + $(1)/lib/firmware/IPQ6018 +endef + +define Package/ath11k-firmware-ipq8074/install + $(INSTALL_DIR) $(1)/lib/firmware/IPQ8074 + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/IPQ8074/hw2.0/board-2.bin \ + $(1)/lib/firmware/IPQ8074/ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/IPQ8074/hw2.0/2.1.0.1/WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2/* \ + $(1)/lib/firmware/IPQ8074 +endef + +define Package/ath11k-firmware-qca6390/install + $(INSTALL_DIR) $(1)/lib/firmware/QCA6390 + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/QCA6390/hw2.0/WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1/* \ + $(1)/lib/firmware/QCA6390 +endef + +$(eval $(call BuildPackage,ath11k-firmware-ipq6018)) +$(eval $(call BuildPackage,ath11k-firmware-ipq8074)) +$(eval $(call BuildPackage,ath11k-firmware-qca6390)) diff --git a/package/kernel/mac80211/ath.mk b/package/kernel/mac80211/ath.mk index 152f432b75661d..9ce735eb03c7a6 100644 --- a/package/kernel/mac80211/ath.mk +++ b/package/kernel/mac80211/ath.mk @@ -1,6 +1,6 @@ PKG_DRIVERS += \ ath ath5k ath6kl ath6kl-sdio ath6kl-usb ath9k ath9k-common ath9k-htc ath10k \ - carl9170 owl-loader ar5523 wil6210 + ath11k carl9170 owl-loader ar5523 wil6210 PKG_CONFIG_DEPENDS += \ CONFIG_PACKAGE_ATH_DEBUG \ @@ -19,6 +19,7 @@ ifdef CONFIG_PACKAGE_MAC80211_DEBUGFS ATH9K_DEBUGFS \ ATH9K_HTC_DEBUGFS \ ATH10K_DEBUGFS \ + ATH11K_DEBUGFS \ CARL9170_DEBUGFS \ ATH5K_DEBUG \ ATH6KL_DEBUG \ @@ -28,6 +29,7 @@ endif ifdef CONFIG_PACKAGE_MAC80211_TRACING config-y += \ ATH10K_TRACING \ + ATH11K_TRACING \ ATH6KL_TRACING \ ATH_TRACEPOINTS \ ATH5K_TRACER \ @@ -35,7 +37,7 @@ ifdef CONFIG_PACKAGE_MAC80211_TRACING endif config-$(call config_package,ath) += ATH_CARDS ATH_COMMON -config-$(CONFIG_PACKAGE_ATH_DEBUG) += ATH_DEBUG ATH10K_DEBUG ATH9K_STATION_STATISTICS +config-$(CONFIG_PACKAGE_ATH_DEBUG) += ATH_DEBUG ATH10K_DEBUG ATH11K_DEBUG ATH9K_STATION_STATISTICS config-$(CONFIG_PACKAGE_ATH_DFS) += ATH9K_DFS_CERTIFIED ATH10K_DFS_CERTIFIED config-$(CONFIG_PACKAGE_ATH_SPECTRAL) += ATH9K_COMMON_SPECTRAL ATH10K_SPECTRAL config-$(CONFIG_PACKAGE_ATH_DYNACK) += ATH9K_DYNACK @@ -55,6 +57,7 @@ config-$(CONFIG_ATH10K_THERMAL) += ATH10K_THERMAL config-$(call config_package,ath9k-htc) += ATH9K_HTC config-$(call config_package,ath10k) += ATH10K ATH10K_PCI +config-$(call config_package,ath11k) += ATH11K config-$(call config_package,ath5k) += ATH5K ifdef CONFIG_TARGET_ath25 @@ -282,6 +285,20 @@ define KernelPackage/ath10k/config endef +define KernelPackage/ath11k + $(call KernelPackage/mac80211/Default) + TITLE:=Qualcomm 802.11ax wireless chipset support + URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath11k + DEPENDS+= @TARGET_ipq807x +kmod-ath +@DRIVER_11N_SUPPORT +@DRIVER_11AC_SUPPORT +@DRIVER_11AX_SUPPORT +@DRIVER_11W_SUPPORT +kmod-crypto-michael-mic + FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath11k/ath11k.ko + AUTOLOAD:=$(call AutoProbe,ath11k) +endef + +define KernelPackage/ath11k/description +This module adds support for Qualcomm Technologies 802.11ax family of +chipsets. +endef + define KernelPackage/carl9170 $(call KernelPackage/mac80211/Default) TITLE:=Driver for Atheros AR9170 USB sticks diff --git a/target/linux/ipq807x/Makefile b/target/linux/ipq807x/Makefile index 9c0d183993185b..857702df85c0dd 100644 --- a/target/linux/ipq807x/Makefile +++ b/target/linux/ipq807x/Makefile @@ -2,14 +2,18 @@ include $(TOPDIR)/rules.mk ARCH:=aarch64 BOARD:=ipq807x -BOARDNAME:=Qualcomm Atheros IPQ807x -FEATURES:=squashfs ramdisk source-only -MAINTAINER:=John Crispin +BOARDNAME:=Qualcomm Atheros IPQ807X +FEATURES:=squashfs fpu ramdisk nand source-only KERNELNAME:=Image dtbs CPU_TYPE:=cortex-a53 +SUBTARGETS:=generic KERNEL_PATCHVER:=5.4 include $(INCLUDE_DIR)/target.mk +DEFAULT_PACKAGES += \ + kmod-leds-gpio kmod-gpio-button-hotplug \ + ath11k-firmware-ipq8074 kmod-ath11k \ + wpad-basic-wolfssl $(eval $(call BuildTarget)) diff --git a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata new file mode 100644 index 00000000000000..c2a980196106f8 --- /dev/null +++ b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata @@ -0,0 +1,20 @@ +#!/bin/sh -x + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 + +. /lib/functions/caldata.sh + +board=$(board_name) + +case "$FIRMWARE" in +"IPQ8074/caldata.bin") + case "$board" in + xiaomi,ax3600) + caldata_extract "0:ART" 0x1000 0x20000 + ;; + esac + ;; +*) + exit 1 + ;; +esac diff --git a/target/linux/ipq807x/base-files/etc/inittab b/target/linux/ipq807x/base-files/etc/inittab new file mode 100644 index 00000000000000..3181021a059272 --- /dev/null +++ b/target/linux/ipq807x/base-files/etc/inittab @@ -0,0 +1,5 @@ +# Copyright (c) 2013 The Linux Foundation. All rights reserved. +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +ttyMSM0::askfirst:/usr/libexec/login.sh +ttyMSM1::askfirst:/usr/libexec/login.sh diff --git a/target/linux/ipq807x/config-default b/target/linux/ipq807x/config-5.4 similarity index 79% rename from target/linux/ipq807x/config-default rename to target/linux/ipq807x/config-5.4 index 295a7b4200ea48..4c66e20178992f 100644 --- a/target/linux/ipq807x/config-default +++ b/target/linux/ipq807x/config-5.4 @@ -1,29 +1,38 @@ CONFIG_64BIT=y -# CONFIG_ACPI is not set # CONFIG_ALLOW_DEV_COREDUMP is not set # CONFIG_APQ_GCC_8084 is not set # CONFIG_APQ_MMCC_8084 is not set CONFIG_AQUANTIA_PHY=y CONFIG_ARCH_CLOCKSOURCE_DATA=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SG_CHAIN=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_ARCH_MMAP_RND_BITS_MAX=24 CONFIG_ARCH_MMAP_RND_BITS_MIN=18 @@ -34,7 +43,6 @@ CONFIG_ARCH_QCOM=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_SPARSEMEM_DEFAULT=y CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUPPORTS_ACPI=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_INT128=y @@ -43,17 +51,20 @@ CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_ARCH_USE_QUEUED_RWLOCKS=y CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_ARCH_WANT_FRAME_POINTERS=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_ARM64=y -# CONFIG_ARM64_16K_PAGES is not set CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_64K_PAGES is not set +CONFIG_ARM64_CNP=y CONFIG_ARM64_CONT_SHIFT=4 -# CONFIG_ARM64_CRYPTO is not set +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_1418040=y CONFIG_ARM64_ERRATUM_819472=y CONFIG_ARM64_ERRATUM_824069=y CONFIG_ARM64_ERRATUM_826319=y @@ -62,22 +73,21 @@ CONFIG_ARM64_ERRATUM_832075=y CONFIG_ARM64_ERRATUM_843419=y CONFIG_ARM64_ERRATUM_845719=y CONFIG_ARM64_HW_AFDBM=y -# CONFIG_ARM64_LSE_ATOMICS is not set CONFIG_ARM64_MODULE_PLTS=y CONFIG_ARM64_PAGE_SHIFT=12 CONFIG_ARM64_PAN=y CONFIG_ARM64_PA_BITS=48 CONFIG_ARM64_PA_BITS_48=y -# CONFIG_ARM64_PMEM is not set -# CONFIG_ARM64_PTDUMP_DEBUGFS is not set -# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +CONFIG_ARM64_PTR_AUTH=y CONFIG_ARM64_SSBD=y CONFIG_ARM64_SVE=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y CONFIG_ARM64_UAO=y CONFIG_ARM64_VA_BITS=39 CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARM64_VA_BITS_48 is not set CONFIG_ARM64_VHE=y +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y # CONFIG_ARMV8_DEPRECATED is not set CONFIG_ARM_AMBA=y CONFIG_ARM_ARCH_TIMER=y @@ -93,24 +103,26 @@ CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ARM_PMU=y +CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_QCOM_CPUFREQ_KRYO is not set +# CONFIG_ARM_QCOM_CPUFREQ_HW is not set +# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set # CONFIG_ARM_SCMI_PROTOCOL is not set -# CONFIG_ARM_SP805_WATCHDOG is not set CONFIG_ASN1=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_AT803X_PHY=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_NVME=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_BLK_MQ_PCI=y CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_PM=y CONFIG_BLOCK_COMPAT=y -CONFIG_BUILD_BIN2C=y +CONFIG_CAVIUM_TX2_ERRATUM_219=y +CONFIG_CC_HAS_KASAN_GENERIC=y # CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_CLEANCACHE=y @@ -119,7 +131,6 @@ CONFIG_CLONE_BACKWARDS=y CONFIG_CLZ_TAB=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_QCOM=y -CONFIG_COMMON_CLK_XGENE=y CONFIG_COMPAT=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_COMPAT_BINFMT_ELF=y @@ -130,7 +141,6 @@ CONFIG_COREDUMP=y CONFIG_CORESIGHT=y # CONFIG_CORESIGHT_CATU is not set # CONFIG_CORESIGHT_CPU_DEBUG is not set -# CONFIG_CORESIGHT_DYNAMIC_REPLICATOR is not set CONFIG_CORESIGHT_LINKS_AND_SINKS=y CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y # CONFIG_CORESIGHT_SINK_ETBV10 is not set @@ -139,7 +149,6 @@ CONFIG_CORESIGHT_SOURCE_ETM4X=y CONFIG_CORESIGHT_STM=y CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y -# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_ATTR_SET=y @@ -150,7 +159,6 @@ CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_STAT=y -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y @@ -173,7 +181,7 @@ CONFIG_CRYPTO_CMAC=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_DEFLATE=y -# CONFIG_CRYPTO_DEV_QCOM_RNG is not set +CONFIG_CRYPTO_DEV_QCOM_RNG=y CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_DRBG_HMAC=y CONFIG_CRYPTO_DRBG_MENU=y @@ -188,10 +196,12 @@ CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_RNG=y @@ -200,48 +210,41 @@ CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_ZSTD=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_GPIO=y CONFIG_DECOMPRESS_GZIP=y CONFIG_DEVMEM=y CONFIG_DMADEVICES=y -CONFIG_DMA_DIRECT_OPS=y +CONFIG_DMA_DIRECT_REMAP=y CONFIG_DMA_ENGINE=y CONFIG_DMA_OF=y +CONFIG_DMA_REMAP=y CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DMI=y -CONFIG_DMIID=y -# CONFIG_DMI_SYSFS is not set +CONFIG_DRM_RCAR_WRITEBACK=y CONFIG_DTC=y CONFIG_DT_IDLE_STATES=y CONFIG_DYNAMIC_DEBUG=y CONFIG_EDAC_SUPPORT=y -CONFIG_EFI=y -CONFIG_EFIVAR_FS=m -CONFIG_EFI_ARMSTUB=y -CONFIG_EFI_ARMSTUB_DTB_LOADER=y -# CONFIG_EFI_CAPSULE_LOADER is not set -CONFIG_EFI_ESRT=y -CONFIG_EFI_PARAMS_FROM_FDT=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_STUB=y -# CONFIG_EFI_TEST is not set -# CONFIG_EFI_VARS is not set +CONFIG_EFI_EARLYCON=y CONFIG_EXT4_FS=y # CONFIG_EXT4_USE_FOR_EXT2 is not set CONFIG_FB=y CONFIG_FB_CMDLINE=y -# CONFIG_FB_EFI is not set CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y # CONFIG_FLATMEM_MANUAL is not set +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y CONFIG_FRAME_POINTER=y CONFIG_FRAME_WARN=2048 CONFIG_FREEZER=y CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y +CONFIG_FUJITSU_ERRATUM_010001=y +CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_BUG=y @@ -252,6 +255,7 @@ CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_MIGRATION=y @@ -270,6 +274,7 @@ CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_HANDLE_DOMAIN_IRQ=y @@ -283,22 +288,27 @@ CONFIG_HAVE_ARCH_AUDITSYSCALL=y CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_HAVE_ARCH_HUGE_VMAP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y CONFIG_HAVE_ARCH_KGDB=y CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_HAVE_CMPXCHG_DOUBLE=y CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_HAVE_DEBUG_BUGVERBOSE=y CONFIG_HAVE_DEBUG_KMEMLEAK=y @@ -306,18 +316,20 @@ CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_EBPF_JIT=y CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FAST_GUP=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_GENERIC_GUP=y +CONFIG_HAVE_GENERIC_VDSO=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MEMBLOCK=y CONFIG_HAVE_MEMORY_PRESENT=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_HAVE_NET_DSA=y CONFIG_HAVE_PATA_PLATFORM=y +CONFIG_HAVE_PCI=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y @@ -330,10 +342,11 @@ CONFIG_HAVE_UID16=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HOLES_IN_ZONE=y CONFIG_HOTPLUG_CPU=y -# CONFIG_HUGETLBFS is not set CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_HW_RANDOM=y +CONFIG_HZ=250 +CONFIG_HZ_250=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y @@ -341,12 +354,9 @@ CONFIG_I2C_COMPAT=y CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_QUP=y CONFIG_IIO=y -# CONFIG_IIO_BUFFER is not set -# CONFIG_IIO_TRIGGER is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_INITRAMFS_SOURCE="" +CONFIG_IPQ_APSS_8074=y # CONFIG_IPQ_GCC_4019 is not set # CONFIG_IPQ_GCC_806X is not set CONFIG_IPQ_GCC_8074=y @@ -360,6 +370,7 @@ CONFIG_IRQ_WORK=y CONFIG_JBD2=y CONFIG_KEYS=y CONFIG_KEYS_COMPAT=y +# CONFIG_KPSS_XCC is not set # CONFIG_KVM is not set CONFIG_LEDS_TLC591XX=y CONFIG_LIBFDT=y @@ -390,6 +401,7 @@ CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_MSM=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_TIFM_SD is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_MPILIB=y @@ -405,16 +417,17 @@ CONFIG_MPILIB=y # CONFIG_MSM_MMCC_8974 is not set # CONFIG_MSM_MMCC_8996 is not set CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y CONFIG_MTD_NAND_QCOM=y +CONFIG_MTD_RAW_NAND=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPLIT_FIRMWARE=y CONFIG_MTD_SPLIT_FIT_FW=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set CONFIG_MTD_UBI_GLUEBI=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MUTEX_SPIN_ON_OWNER=y @@ -425,15 +438,12 @@ CONFIG_NET_PTP_CLASSIFY=y CONFIG_NET_SWITCHDEV=y # CONFIG_NET_VENDOR_CAVIUM is not set CONFIG_NLS=y -CONFIG_NO_BOOTMEM=y CONFIG_NO_HZ=y CONFIG_NO_HZ_COMMON=y CONFIG_NO_HZ_IDLE=y CONFIG_NR_CPUS=4 -# CONFIG_NUMA is not set CONFIG_NVMEM=y -CONFIG_NVME_CORE=y -# CONFIG_NVME_MULTIPATH is not set +# CONFIG_OCTEONTX2_AF is not set CONFIG_OF=y CONFIG_OF_ADDRESS=y CONFIG_OF_EARLY_FLATTREE=y @@ -443,29 +453,31 @@ CONFIG_OF_IRQ=y CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y CONFIG_OF_NET=y -CONFIG_OF_RESERVED_MEM=y CONFIG_OID_REGISTRY=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_PADATA=y CONFIG_PANIC_TIMEOUT=5 CONFIG_PARTITION_PERCPU=y CONFIG_PCI=y +# CONFIG_PCIE_AL is not set CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y CONFIG_PCIE_QCOM=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_LABEL=y CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PERF_EVENTS=y CONFIG_PGTABLE_LEVELS=3 CONFIG_PHYLIB=y CONFIG_PHYS_ADDR_T_64BIT=y # CONFIG_PHY_QCOM_APQ8064_SATA is not set # CONFIG_PHY_QCOM_IPQ806X_SATA is not set -# CONFIG_PHY_QCOM_QMP is not set -# CONFIG_PHY_QCOM_QUSB2 is not set +# CONFIG_PHY_QCOM_PCIE2 is not set +CONFIG_PHY_QCOM_QMP=y +CONFIG_PHY_QCOM_QUSB2=y # CONFIG_PHY_QCOM_UFS is not set +CONFIG_PID_IN_CONTEXTIDR=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_APQ8064 is not set # CONFIG_PINCTRL_APQ8084 is not set @@ -482,10 +494,15 @@ CONFIG_PINCTRL_MSM=y # CONFIG_PINCTRL_MSM8998 is not set CONFIG_PINCTRL_QCOM_SPMI_PMIC=y # CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set +# CONFIG_PINCTRL_QCS404 is not set +# CONFIG_PINCTRL_SC7180 is not set +# CONFIG_PINCTRL_SDM660 is not set # CONFIG_PINCTRL_SDM845 is not set +# CONFIG_PINCTRL_SM8150 is not set +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set CONFIG_PM=y +# CONFIG_PM8916_WATCHDOG is not set CONFIG_PM_CLK=y -# CONFIG_PM_DEBUG is not set CONFIG_PM_OPP=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y @@ -495,40 +512,71 @@ CONFIG_POWER_RESET_MSM=y CONFIG_POWER_SUPPLY=y CONFIG_PPS=y CONFIG_PREEMPT=y +CONFIG_PREEMPTION=y CONFIG_PREEMPT_COUNT=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_RCU=y CONFIG_PRINTK_TIME=y CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_STRIPPED is not set CONFIG_PTP_1588_CLOCK=y CONFIG_PWM=y CONFIG_PWM_SYSFS=y CONFIG_QCOM_A53PLL=y -# CONFIG_QCOM_APCS_IPC is not set +# CONFIG_QCOM_AOSS_QMP is not set +CONFIG_QCOM_APCS_IPC=y +# CONFIG_QCOM_APR is not set CONFIG_QCOM_BAM_DMA=y +# CONFIG_QCOM_CLK_APCS_MSM8916 is not set # CONFIG_QCOM_CLK_RPM is not set +# CONFIG_QCOM_CLK_RPMH is not set +# CONFIG_QCOM_CLK_SMD_RPM is not set # CONFIG_QCOM_COINCELL is not set # CONFIG_QCOM_COMMAND_DB is not set CONFIG_QCOM_EBI2=y +# CONFIG_QCOM_FASTRPC is not set # CONFIG_QCOM_GENI_SE is not set -CONFIG_QCOM_GSBI=y +CONFIG_QCOM_GLINK_SSR=y +# CONFIG_QCOM_GSBI is not set +# CONFIG_QCOM_HFPLL is not set # CONFIG_QCOM_LLCC is not set +CONFIG_QCOM_MDT_LOADER=y # CONFIG_QCOM_PDC is not set +CONFIG_QCOM_PIL_INFO=y +# CONFIG_QCOM_Q6V5_ADSP is not set +CONFIG_QCOM_Q6V5_COMMON=y +# CONFIG_QCOM_Q6V5_MSS is not set +# CONFIG_QCOM_Q6V5_PAS is not set +CONFIG_QCOM_Q6V5_WCSS=y CONFIG_QCOM_QFPROM=y +CONFIG_QCOM_QMI_HELPERS=y # CONFIG_QCOM_RMTFS_MEM is not set -# CONFIG_QCOM_RPMH is not set +CONFIG_QCOM_RPMH=y +CONFIG_QCOM_RPMPD=y +CONFIG_QCOM_RPROC_COMMON=y +CONFIG_QCOM_SCM=y +CONFIG_QCOM_SCM_64=y +# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set +CONFIG_QCOM_SMD_RPM=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SMEM_STATE=y CONFIG_QCOM_SMP2P=y # CONFIG_QCOM_SMSM is not set +CONFIG_QCOM_SOCINFO=y CONFIG_QCOM_SPMI_VADC=y +CONFIG_QCOM_SYSMON=y CONFIG_QCOM_TSENS=y CONFIG_QCOM_VADC_COMMON=y +CONFIG_QCOM_WCNSS_CTRL=y +CONFIG_QCOM_WCNSS_PIL=y CONFIG_QCOM_WDT=y -# CONFIG_QRTR is not set +# CONFIG_QCS_GCC_404 is not set +# CONFIG_QCS_TURING_404 is not set +CONFIG_QRTR=y +CONFIG_QRTR_SMD=y +# CONFIG_QRTR_TUN is not set CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y -# CONFIG_RANDOMIZE_BASE is not set CONFIG_RATIONAL=y CONFIG_RCU_CPU_STALL_TIMEOUT=21 # CONFIG_RCU_EXPERT is not set @@ -545,31 +593,40 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_QCOM_RPM=y +CONFIG_REGULATOR_QCOM_RPMH=y +CONFIG_REGULATOR_QCOM_SMD_RPM=y CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_RELAY=y CONFIG_REMOTEPROC=y -# CONFIG_RESET_ATTACK_MITIGATION is not set CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_QCOM_AOSS is not set +# CONFIG_RESET_QCOM_PDC is not set CONFIG_RFS_ACCEL=y -# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set -# CONFIG_RPMSG_QCOM_SMD is not set +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPMSG=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_QCOM_GLINK_NATIVE=y +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_RPMSG_QCOM_SMD=y CONFIG_RPS=y CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_EFI is not set # CONFIG_RTC_DRV_PM8XXX is not set CONFIG_RTC_I2C_AND_SPI=y CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y +# CONFIG_SDM_CAMCC_845 is not set # CONFIG_SDM_DISPCC_845 is not set +# CONFIG_SDM_GCC_660 is not set # CONFIG_SDM_GCC_845 is not set +# CONFIG_SDM_GPUCC_845 is not set +# CONFIG_SDM_LPASSCC_845 is not set # CONFIG_SDM_VIDEOCC_845 is not set # CONFIG_SERIAL_8250 is not set -# CONFIG_SERIAL_AMBA_PL011 is not set CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SGL_ALLOC=y CONFIG_SMP=y +# CONFIG_SM_GCC_8150 is not set CONFIG_SND=y # CONFIG_SND_COMPRESS_OFFLOAD is not set CONFIG_SND_JACK=y @@ -579,6 +636,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_I2C_AND_SPI=y CONFIG_SND_SOC_QCOM=y # CONFIG_SND_SOC_STORM is not set +CONFIG_SOC_BUS=y CONFIG_SOUND=y CONFIG_SOUND_OSS_CORE=y CONFIG_SOUND_OSS_CORE_PRECLAIM=y @@ -599,6 +657,8 @@ CONFIG_SPMI_MSM_PMIC_ARB=y CONFIG_SRCU=y # CONFIG_STAGING is not set CONFIG_STM=y +# CONFIG_STM_PROTO_BASIC is not set +# CONFIG_STM_PROTO_SYS_T is not set # CONFIG_STM_SOURCE_HEARTBEAT is not set # CONFIG_STRIP_ASM_SYMS is not set CONFIG_SUSPEND=y @@ -624,7 +684,10 @@ CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y CONFIG_TREE_SRCU=y CONFIG_UBIFS_FS=y -CONFIG_UCS2_STRING=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UBIFS_FS_ZSTD=y CONFIG_UEVENT_HELPER_PATH="" CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_UNMAP_KERNEL_AT_EL0=y @@ -641,8 +704,11 @@ CONFIG_WATCHDOG_CORE=y # CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set CONFIG_X509_CERTIFICATE_PARSER=y CONFIG_XPS=y +CONFIG_XXHASH=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_BCJ=y CONFIG_ZLIB_DEFLATE=y CONFIG_ZLIB_INFLATE=y CONFIG_ZONE_DMA32=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts new file mode 100644 index 00000000000000..6ca8ee7ca39643 --- /dev/null +++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include "ipq8074.dtsi" +#include +#include + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + model = "Xiaomi Mi AIoT Router AX3600"; + compatible = "xiaomi,ax3600", "qcom,ipq8074"; + interrupt-parent = <&intc>; + + aliases { + serial0 = &blsp1_uart5; + serial1 = &blsp1_uart3; + led-boot = &led_system_yellow; + led-failsafe = &led_system_yellow; + led-running = &led_system_blue; + led-upgrade = &led_system_yellow; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-append = " swiotlb=1"; + }; + + reserved-memory { + ranges; + #address-cells = <0x2>; + #size-cells = <0x2>; + + tz@4ac00000 { + reg = <0x0 0x4ac00000 0x0 0x400000>; + no-map; + }; + + wcnss@4b000000 { + reg = <0x0 0x4b000000 0x0 0x3700000>; + no-map; + }; + + rsvd2@50b00000 { + reg = <0x0 0x50b00000 0x0 0x400000>; + no-map; + }; + + wifi_dump@50500000 { + reg = <0x0 0x50500000 0x0 0x200000>; + no-map; + }; + + rsvd1@50700000 { + reg = <0x0 0x50700000 0x0 0x400000>; + no-map; + }; + + q6_etr_dump@4e700000 { + reg = <0x0 0x4e700000 0x0 0x100000>; + no-map; + }; + + sbl@4aa00000 { + reg = <0x0 0x4aa00000 0x0 0x100000>; + no-map; + }; + + uboot@4a600000 { + reg = <0x0 0x4a600000 0x0 0x400000>; + no-map; + }; + + nss@40000000 { + reg = <0x0 0x40000000 0x0 0x1000000>; + no-map; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_system_blue: system-blue { + label = "ax3600:blue:system"; + gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + }; + + led_system_yellow: system-yellow { + label = "ax3600:yellow:system"; + gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>; + }; + + network-yellow { + label = "ax3600:yellow:network"; + gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>; + }; + + network-blue { + label = "ax3600:blue:network"; + gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + }; + + aiot { + label = "ax3600:blue:aiot"; + gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&blsp1_uart3 { + status = "okay"; +}; + +&blsp1_uart5 { + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "0:SBL1"; + reg = <0x00000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "0:MIBIB"; + reg = <0x00100000 0x100000>; + read-only; + }; + + partition@200000 { + label = "0:QSEE"; + reg = <0x00200000 0x300000>; + read-only; + }; + + partition@500000 { + label = "0:DEVCFG"; + reg = <0x00500000 0x80000>; + read-only; + }; + + partition@580000 { + label = "0:RPM"; + reg = <0x00580000 0x80000>; + read-only; + }; + + partition@600000 { + label = "0:CDT"; + reg = <0x00600000 0x80000>; + read-only; + }; + + partition@680000 { + label = "0:APPSBLENV"; + reg = <0x00680000 0x80000>; + }; + + partition@700000 { + label = "0:APPSBL"; + reg = <0x00700000 0x100000>; + read-only; + }; + + partition@800000 { + label = "0:ART"; + reg = <0x00800000 0x80000>; + read-only; + }; + + partition@880000 { + label = "bdata"; + reg = <0x00880000 0x80000>; + read-only; + }; + + partition@900000 { + label = "crash"; + reg = <0x00900000 0x80000>; + read-only; + }; + + partition@980000 { + label = "crash_syslog"; + reg = <0x00980000 0x80000>; + read-only; + }; + + partition@a00000 { + label = "rootfs"; + reg = <0x00a00000 0x23c0000>; + }; + + partition@2dc0000 { + label = "rootfs_1"; + reg = <0x02dc0000 0x23c0000>; + }; + + partition@5180000 { + label = "overlay"; + reg = <0x05180000 0x1ec0000>; + }; + + partition@7040000 { + label = "rsvd0"; + reg = <0x07040000 0x80000>; + }; + }; + }; +}; + +&wifi0 { + status = "okay"; +}; + +&tlmm { + button_pins: button-pins { + pins = "gpio34"; + function = "gpio"; + bias-pull-up; + drive-strength = <8>; + }; + + led_pins: led-pins { + pins = "gpio21", "gpio22", "gpio42", "gpio43", "gpio51"; + function = "gpio"; + bias-pull-down; + drive-strength = <8>; + }; +}; diff --git a/target/linux/ipq807x/generic/target.mk b/target/linux/ipq807x/generic/target.mk new file mode 100644 index 00000000000000..f5cb1fb19b943f --- /dev/null +++ b/target/linux/ipq807x/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic diff --git a/target/linux/ipq807x/image/Makefile b/target/linux/ipq807x/image/Makefile index 2a0c74554f46aa..d7bb5ff1f2b4c2 100644 --- a/target/linux/ipq807x/image/Makefile +++ b/target/linux/ipq807x/image/Makefile @@ -1,40 +1,48 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/image.mk -IPQ807X_KERNEL_LOADADDR = 0x41080000 -DEVICE_DTS_CONFIG = "config@hk01" - -define Image/BuildKernel/FIT - gzip -9 -c $(KDIR)/Image > $(KDIR)/Image.gz - $(call CompressLzma,$(KDIR)/Image,$(KDIR)/Image.gz) - $(call Image/BuildKernel/MkFIT,$(1), $(KDIR)/Image.gz, $(DTS_DIR)/qcom/$(1).dtb,gzip,$(2),$(2)) - $(CP) $(KDIR)/fit-$(1).itb $(BIN_DIR)/$(IMG_PREFIX)-$(1)-fit-uImage.itb - mkdir -p $(BIN_DIR)/dtbs/ - $(CP) $(DTS_DIR)/qcom/ipq*.dtb $(BIN_DIR)/dtbs/ - $(CP) $(KDIR)/Image $(BIN_DIR)/dtbs/ -endef - -define Image/BuildKernel/FITInitramfs - $(CP) $(KDIR)/Image-initramfs $(BIN_DIR)/dtbs/ - $(CP) $(KDIR)/Image-initramfs $(BIN_DIR)/$(IMG_PREFIX)-vmlinux-initramfs.bin - $(call Image/BuildKernel/MkFIT,$(1), $(KDIR)/Image-initramfs, $(DTS_DIR)/qcom/$(1).dtb, none,$(2),$(2),-initramfs) - $(CP) $(KDIR)/fit-$(1)-initramfs.itb $(BIN_DIR)/$(IMG_PREFIX)-$(1)-fit-uImage-initramfs.itb +define Device/Default + PROFILES := Default + KERNEL_DEPENDS = $$(wildcard $(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dts) + KERNEL_INITRAMFS_PREFIX := $$(IMG_PREFIX)-$(1)-initramfs + KERNEL_PREFIX := $$(IMAGE_PREFIX) + KERNEL_LOADADDR := 0x41080000 + DEVICE_DTS_DIR := $(DTS_DIR)/qcom + DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1))) + SUPPORTED_DEVICES := $(subst _,$(comma),$(1)) + IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata + IMAGE/sysupgrade.bin/squashfs := endef -define Image/Build/squashfs - $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) +define Device/FitImage + KERNEL_SUFFIX := -fit-uImage.itb + KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL_NAME := Image endef -define Image/BuildKernel - $(call Image/BuildKernel/FIT,ipq8074-hk01,$(IPQ807X_KERNEL_LOADADDR)) +define Device/FitImageLzma + KERNEL_SUFFIX := -fit-uImage.itb + KERNEL = kernel-bin | lzma | fit lzma $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL_NAME := Image endef -define Image/BuildKernel/Initramfs - $(call Image/BuildKernel/FITInitramfs,ipq8074-hk01,$(IPQ807X_KERNEL_LOADADDR)) +define Device/UbiFit + KERNEL_IN_UBI := 1 + IMAGES := nand-factory.ubi nand-sysupgrade.bin + IMAGE/nand-factory.ubi := append-ubi + IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata endef -define Image/Build - $(call Image/Build/$(1),$(1)) +define Device/xiaomi_ax3600 + $(call Device/FitImage) + $(call Device/UbiFit) + DEVICE_VENDOR := Xiaomi + DEVICE_MODEL := Mi AIoT Router AX3600 + BLOCKSIZE := 128k + PAGESIZE := 2048 + DEVICE_DTS_CONFIG := config@ac04 + SOC := ipq8071 endef +TARGET_DEVICES += xiaomi_ax3600 $(eval $(call BuildImage)) diff --git a/target/linux/ipq807x/patches-5.4/0001-v5.7-ARM64-dts-qcom-add-gpio-ranges-property.patch b/target/linux/ipq807x/patches-5.4/0001-v5.7-ARM64-dts-qcom-add-gpio-ranges-property.patch new file mode 100644 index 00000000000000..db860dde2aeb1a --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0001-v5.7-ARM64-dts-qcom-add-gpio-ranges-property.patch @@ -0,0 +1,42 @@ +From 297177a45b95097ae4f25a6f6d191d592e1bb018 Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Wed, 8 Jan 2020 13:54:57 +0100 +Subject: [PATCH] ARM64: dts: qcom: add gpio-ranges property + +This patch adds the gpio-ranges property to almost all of +the Qualcomm ARM platforms that utilize the pinctrl-msm +framework. + +The gpio-ranges property is part of the gpiolib subsystem. +As a result, the binding text is available in section +"2.1 gpio- and pin-controller interaction" of +Documentation/devicetree/bindings/gpio/gpio.txt + +For more information please see the patch titled: +"pinctrl: msm: fix gpio-hog related boot issues" from +this series. + +Reported-by: Sven Eckelmann +Tested-by: Sven Eckelmann [ipq4019] +Reviewed-by: Bjorn Andersson +Reviewed-by: Linus Walleij +Signed-off-by: Christian Lamparter +Tested-by: Robert Marko [ipq4019] +Cc: Luka Perkov +Signed-off-by: Robert Marko +Link: https://lore.kernel.org/r/20200108125455.308969-2-robert.marko@sartura.hr +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 + + 1 files changed, 1 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -21,6 +21,7 @@ + reg = <0x1000000 0x300000>; + interrupts = ; + gpio-controller; ++ gpio-ranges = <&tlmm 0 0 70>; + #gpio-cells = <0x2>; + interrupt-controller; + #interrupt-cells = <0x2>; diff --git a/target/linux/ipq807x/patches-5.4/0002-v5.8-arm64-dts-ipq8074-qcom-Re-arrange-dts-nodes-based-on.patch b/target/linux/ipq807x/patches-5.4/0002-v5.8-arm64-dts-ipq8074-qcom-Re-arrange-dts-nodes-based-on.patch new file mode 100644 index 00000000000000..9f72b935ff0c0b --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0002-v5.8-arm64-dts-ipq8074-qcom-Re-arrange-dts-nodes-based-on.patch @@ -0,0 +1,734 @@ +From e8a7fdc505bb06625a176f23293811d12d7d24eb Mon Sep 17 00:00:00 2001 +From: Sivaprakash Murugesan +Date: Sat, 11 Apr 2020 08:10:30 +0530 +Subject: [PATCH] arm64: dts: ipq8074: qcom: Re-arrange dts nodes based on + address + +This patch re-arranges ipq8074 device nodes based on node address +followed by node names followed by node labels. + +Suggested-by: Bjorn Andersson +Signed-off-by: Sivaprakash Murugesan +Link: https://lore.kernel.org/r/1586572830-22727-1-git-send-email-sivaprak@codeaurora.org +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 112 +++-- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 474 +++++++++++----------- + 2 files changed, 292 insertions(+), 294 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts ++++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +@@ -24,63 +24,61 @@ + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x20000000>; + }; ++}; ++ ++&blsp1_i2c2 { ++ status = "ok"; ++}; ++ ++&blsp1_spi1 { ++ status = "ok"; ++ ++ m25p80@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <50000000>; ++ }; ++}; ++ ++&blsp1_uart3 { ++ status = "ok"; ++}; ++ ++&blsp1_uart5 { ++ status = "ok"; ++}; ++ ++&pcie0 { ++ status = "ok"; ++ perst-gpio = <&tlmm 61 0x1>; ++}; ++ ++&pcie1 { ++ status = "ok"; ++ perst-gpio = <&tlmm 58 0x1>; ++}; ++ ++&pcie_phy0 { ++ status = "ok"; ++}; ++ ++&pcie_phy1 { ++ status = "ok"; ++}; ++ ++&qpic_bam { ++ status = "ok"; ++}; ++ ++&qpic_nand { ++ status = "ok"; + +- soc { +- serial@78b3000 { +- status = "ok"; +- }; +- +- spi@78b5000 { +- status = "ok"; +- +- m25p80@0 { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <50000000>; +- }; +- }; +- +- serial@78b1000 { +- status = "ok"; +- }; +- +- i2c@78b6000 { +- status = "ok"; +- }; +- +- dma@7984000 { +- status = "ok"; +- }; +- +- nand@79b0000 { +- status = "ok"; +- +- nand@0 { +- reg = <0>; +- nand-ecc-strength = <4>; +- nand-ecc-step-size = <512>; +- nand-bus-width = <8>; +- }; +- }; +- +- phy@86000 { +- status = "ok"; +- }; +- +- phy@8e000 { +- status = "ok"; +- }; +- +- pci@20000000 { +- status = "ok"; +- perst-gpio = <&tlmm 58 0x1>; +- }; +- +- pci@10000000 { +- status = "ok"; +- perst-gpio = <&tlmm 61 0x1>; +- }; ++ nand@0 { ++ reg = <0>; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ nand-bus-width = <8>; + }; + }; +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -10,15 +10,111 @@ + model = "Qualcomm Technologies, Inc. IPQ8074"; + compatible = "qcom,ipq8074"; + ++ clocks { ++ sleep_clk: sleep_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++ #clock-cells = <0>; ++ }; ++ ++ xo: xo { ++ compatible = "fixed-clock"; ++ clock-frequency = <19200000>; ++ #clock-cells = <0>; ++ }; ++ }; ++ ++ cpus { ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ ++ CPU0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x0>; ++ next-level-cache = <&L2_0>; ++ enable-method = "psci"; ++ }; ++ ++ CPU1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ enable-method = "psci"; ++ reg = <0x1>; ++ next-level-cache = <&L2_0>; ++ }; ++ ++ CPU2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ enable-method = "psci"; ++ reg = <0x2>; ++ next-level-cache = <&L2_0>; ++ }; ++ ++ CPU3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ enable-method = "psci"; ++ reg = <0x3>; ++ next-level-cache = <&L2_0>; ++ }; ++ ++ L2_0: l2-cache { ++ compatible = "cache"; ++ cache-level = <0x2>; ++ }; ++ }; ++ ++ pmu { ++ compatible = "arm,armv8-pmuv3"; ++ interrupts = ; ++ }; ++ ++ psci { ++ compatible = "arm,psci-1.0"; ++ method = "smc"; ++ }; ++ + soc: soc { + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + ++ pcie_phy0: phy@86000 { ++ compatible = "qcom,ipq8074-qmp-pcie-phy"; ++ reg = <0x00086000 0x1000>; ++ #phy-cells = <0>; ++ clocks = <&gcc GCC_PCIE0_PIPE_CLK>; ++ clock-names = "pipe_clk"; ++ clock-output-names = "pcie20_phy0_pipe_clk"; ++ ++ resets = <&gcc GCC_PCIE0_PHY_BCR>, ++ <&gcc GCC_PCIE0PHY_PHY_BCR>; ++ reset-names = "phy", ++ "common"; ++ status = "disabled"; ++ }; ++ ++ pcie_phy1: phy@8e000 { ++ compatible = "qcom,ipq8074-qmp-pcie-phy"; ++ reg = <0x0008e000 0x1000>; ++ #phy-cells = <0>; ++ clocks = <&gcc GCC_PCIE1_PIPE_CLK>; ++ clock-names = "pipe_clk"; ++ clock-output-names = "pcie20_phy1_pipe_clk"; ++ ++ resets = <&gcc GCC_PCIE1_PHY_BCR>, ++ <&gcc GCC_PCIE1PHY_PHY_BCR>; ++ reset-names = "phy", ++ "common"; ++ status = "disabled"; ++ }; ++ + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq8074-pinctrl"; +- reg = <0x1000000 0x300000>; ++ reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 70>; +@@ -66,102 +162,16 @@ + }; + }; + +- intc: interrupt-controller@b000000 { +- compatible = "qcom,msm-qgic2"; +- interrupt-controller; +- #interrupt-cells = <0x3>; +- reg = <0xb000000 0x1000>, <0xb002000 0x1000>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- timer@b120000 { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- compatible = "arm,armv7-timer-mem"; +- reg = <0xb120000 0x1000>; +- clock-frequency = <19200000>; +- +- frame@b120000 { +- frame-number = <0>; +- interrupts = , +- ; +- reg = <0xb121000 0x1000>, +- <0xb122000 0x1000>; +- }; +- +- frame@b123000 { +- frame-number = <1>; +- interrupts = ; +- reg = <0xb123000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b124000 { +- frame-number = <2>; +- interrupts = ; +- reg = <0xb124000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b125000 { +- frame-number = <3>; +- interrupts = ; +- reg = <0xb125000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b126000 { +- frame-number = <4>; +- interrupts = ; +- reg = <0xb126000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b127000 { +- frame-number = <5>; +- interrupts = ; +- reg = <0xb127000 0x1000>; +- status = "disabled"; +- }; +- +- frame@b128000 { +- frame-number = <6>; +- interrupts = ; +- reg = <0xb128000 0x1000>; +- status = "disabled"; +- }; +- }; +- + gcc: gcc@1800000 { + compatible = "qcom,gcc-ipq8074"; +- reg = <0x1800000 0x80000>; ++ reg = <0x01800000 0x80000>; + #clock-cells = <0x1>; + #reset-cells = <0x1>; + }; + +- blsp1_uart5: serial@78b3000 { +- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x78b3000 0x200>; +- interrupts = ; +- clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, +- <&gcc GCC_BLSP1_AHB_CLK>; +- clock-names = "core", "iface"; +- pinctrl-0 = <&serial_4_pins>; +- pinctrl-names = "default"; +- status = "disabled"; +- }; +- + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; +- reg = <0x7884000 0x2b000>; ++ reg = <0x07884000 0x2b000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; +@@ -171,7 +181,7 @@ + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x78af000 0x200>; ++ reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; +@@ -181,7 +191,7 @@ + + blsp1_uart3: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; +- reg = <0x78b1000 0x200>; ++ reg = <0x078b1000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; +@@ -194,11 +204,23 @@ + status = "disabled"; + }; + ++ blsp1_uart5: serial@78b3000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x078b3000 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ pinctrl-0 = <&serial_4_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ + blsp1_spi1: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; +- reg = <0x78b5000 0x600>; ++ reg = <0x078b5000 0x600>; + interrupts = ; + spi-max-frequency = <50000000>; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, +@@ -215,7 +237,7 @@ + compatible = "qcom,i2c-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; +- reg = <0x78b6000 0x600>; ++ reg = <0x078b6000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; +@@ -232,7 +254,7 @@ + compatible = "qcom,i2c-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; +- reg = <0x78b7000 0x600>; ++ reg = <0x078b7000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; +@@ -245,7 +267,7 @@ + + qpic_bam: dma@7984000 { + compatible = "qcom,bam-v1.7.0"; +- reg = <0x7984000 0x1a000>; ++ reg = <0x07984000 0x1a000>; + interrupts = ; + clocks = <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "bam_clk"; +@@ -256,7 +278,7 @@ + + qpic_nand: nand@79b0000 { + compatible = "qcom,ipq8074-nand"; +- reg = <0x79b0000 0x10000>; ++ reg = <0x079b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, +@@ -272,104 +294,85 @@ + status = "disabled"; + }; + +- pcie_phy0: phy@86000 { +- compatible = "qcom,ipq8074-qmp-pcie-phy"; +- reg = <0x86000 0x1000>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_PCIE0_PIPE_CLK>; +- clock-names = "pipe_clk"; +- clock-output-names = "pcie20_phy0_pipe_clk"; ++ intc: interrupt-controller@b000000 { ++ compatible = "qcom,msm-qgic2"; ++ interrupt-controller; ++ #interrupt-cells = <0x3>; ++ reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; ++ }; + +- resets = <&gcc GCC_PCIE0_PHY_BCR>, +- <&gcc GCC_PCIE0PHY_PHY_BCR>; +- reset-names = "phy", +- "common"; +- status = "disabled"; ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; + }; + +- pcie0: pci@20000000 { +- compatible = "qcom,pcie-ipq8074"; +- reg = <0x20000000 0xf1d +- 0x20000f20 0xa8 +- 0x80000 0x2000 +- 0x20100000 0x1000>; +- reg-names = "dbi", "elbi", "parf", "config"; +- device_type = "pci"; +- linux,pci-domain = <0>; +- bus-range = <0x00 0xff>; +- num-lanes = <1>; +- #address-cells = <3>; +- #size-cells = <2>; ++ timer@b120000 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ compatible = "arm,armv7-timer-mem"; ++ reg = <0x0b120000 0x1000>; ++ clock-frequency = <19200000>; + +- phys = <&pcie_phy0>; +- phy-names = "pciephy"; ++ frame@b120000 { ++ frame-number = <0>; ++ interrupts = , ++ ; ++ reg = <0x0b121000 0x1000>, ++ <0x0b122000 0x1000>; ++ }; + +- ranges = <0x81000000 0 0x20200000 0x20200000 +- 0 0x100000 /* downstream I/O */ +- 0x82000000 0 0x20300000 0x20300000 +- 0 0xd00000>; /* non-prefetchable memory */ ++ frame@b123000 { ++ frame-number = <1>; ++ interrupts = ; ++ reg = <0x0b123000 0x1000>; ++ status = "disabled"; ++ }; + +- interrupts = ; +- interrupt-names = "msi"; +- #interrupt-cells = <1>; +- interrupt-map-mask = <0 0 0 0x7>; +- interrupt-map = <0 0 0 1 &intc 0 75 +- IRQ_TYPE_LEVEL_HIGH>, /* int_a */ +- <0 0 0 2 &intc 0 78 +- IRQ_TYPE_LEVEL_HIGH>, /* int_b */ +- <0 0 0 3 &intc 0 79 +- IRQ_TYPE_LEVEL_HIGH>, /* int_c */ +- <0 0 0 4 &intc 0 83 +- IRQ_TYPE_LEVEL_HIGH>; /* int_d */ ++ frame@b124000 { ++ frame-number = <2>; ++ interrupts = ; ++ reg = <0x0b124000 0x1000>; ++ status = "disabled"; ++ }; + +- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, +- <&gcc GCC_PCIE0_AXI_M_CLK>, +- <&gcc GCC_PCIE0_AXI_S_CLK>, +- <&gcc GCC_PCIE0_AHB_CLK>, +- <&gcc GCC_PCIE0_AUX_CLK>; ++ frame@b125000 { ++ frame-number = <3>; ++ interrupts = ; ++ reg = <0x0b125000 0x1000>; ++ status = "disabled"; ++ }; + +- clock-names = "iface", +- "axi_m", +- "axi_s", +- "ahb", +- "aux"; +- resets = <&gcc GCC_PCIE0_PIPE_ARES>, +- <&gcc GCC_PCIE0_SLEEP_ARES>, +- <&gcc GCC_PCIE0_CORE_STICKY_ARES>, +- <&gcc GCC_PCIE0_AXI_MASTER_ARES>, +- <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, +- <&gcc GCC_PCIE0_AHB_ARES>, +- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; +- reset-names = "pipe", +- "sleep", +- "sticky", +- "axi_m", +- "axi_s", +- "ahb", +- "axi_m_sticky"; +- status = "disabled"; +- }; ++ frame@b126000 { ++ frame-number = <4>; ++ interrupts = ; ++ reg = <0x0b126000 0x1000>; ++ status = "disabled"; ++ }; + +- pcie_phy1: phy@8e000 { +- compatible = "qcom,ipq8074-qmp-pcie-phy"; +- reg = <0x8e000 0x1000>; +- #phy-cells = <0>; +- clocks = <&gcc GCC_PCIE1_PIPE_CLK>; +- clock-names = "pipe_clk"; +- clock-output-names = "pcie20_phy1_pipe_clk"; ++ frame@b127000 { ++ frame-number = <5>; ++ interrupts = ; ++ reg = <0x0b127000 0x1000>; ++ status = "disabled"; ++ }; + +- resets = <&gcc GCC_PCIE1_PHY_BCR>, +- <&gcc GCC_PCIE1PHY_PHY_BCR>; +- reset-names = "phy", +- "common"; +- status = "disabled"; ++ frame@b128000 { ++ frame-number = <6>; ++ interrupts = ; ++ reg = <0x0b128000 0x1000>; ++ status = "disabled"; ++ }; + }; + + pcie1: pci@10000000 { + compatible = "qcom,pcie-ipq8074"; + reg = <0x10000000 0xf1d + 0x10000f20 0xa8 +- 0x88000 0x2000 ++ 0x00088000 0x2000 + 0x10100000 0x1000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; +@@ -426,71 +429,68 @@ + "axi_m_sticky"; + status = "disabled"; + }; +- }; +- +- cpus { +- #address-cells = <0x1>; +- #size-cells = <0x0>; +- +- CPU0: cpu@0 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- reg = <0x0>; +- next-level-cache = <&L2_0>; +- enable-method = "psci"; +- }; +- +- CPU1: cpu@1 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x1>; +- next-level-cache = <&L2_0>; +- }; + +- CPU2: cpu@2 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x2>; +- next-level-cache = <&L2_0>; +- }; +- +- CPU3: cpu@3 { +- device_type = "cpu"; +- compatible = "arm,cortex-a53"; +- enable-method = "psci"; +- reg = <0x3>; +- next-level-cache = <&L2_0>; +- }; ++ pcie0: pci@20000000 { ++ compatible = "qcom,pcie-ipq8074"; ++ reg = <0x20000000 0xf1d ++ 0x20000f20 0xa8 ++ 0x00080000 0x2000 ++ 0x20100000 0x1000>; ++ reg-names = "dbi", "elbi", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <0>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; + +- L2_0: l2-cache { +- compatible = "cache"; +- cache-level = <0x2>; +- }; +- }; ++ phys = <&pcie_phy0>; ++ phy-names = "pciephy"; + +- psci { +- compatible = "arm,psci-1.0"; +- method = "smc"; +- }; ++ ranges = <0x81000000 0 0x20200000 0x20200000 ++ 0 0x100000 /* downstream I/O */ ++ 0x82000000 0 0x20300000 0x20300000 ++ 0 0xd00000>; /* non-prefetchable memory */ + +- pmu { +- compatible = "arm,armv8-pmuv3"; +- interrupts = ; +- }; ++ interrupts = ; ++ interrupt-names = "msi"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 75 ++ IRQ_TYPE_LEVEL_HIGH>, /* int_a */ ++ <0 0 0 2 &intc 0 78 ++ IRQ_TYPE_LEVEL_HIGH>, /* int_b */ ++ <0 0 0 3 &intc 0 79 ++ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ++ <0 0 0 4 &intc 0 83 ++ IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + +- clocks { +- sleep_clk: sleep_clk { +- compatible = "fixed-clock"; +- clock-frequency = <32000>; +- #clock-cells = <0>; +- }; ++ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, ++ <&gcc GCC_PCIE0_AXI_M_CLK>, ++ <&gcc GCC_PCIE0_AXI_S_CLK>, ++ <&gcc GCC_PCIE0_AHB_CLK>, ++ <&gcc GCC_PCIE0_AUX_CLK>; + +- xo: xo { +- compatible = "fixed-clock"; +- clock-frequency = <19200000>; +- #clock-cells = <0>; ++ clock-names = "iface", ++ "axi_m", ++ "axi_s", ++ "ahb", ++ "aux"; ++ resets = <&gcc GCC_PCIE0_PIPE_ARES>, ++ <&gcc GCC_PCIE0_SLEEP_ARES>, ++ <&gcc GCC_PCIE0_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_MASTER_ARES>, ++ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, ++ <&gcc GCC_PCIE0_AHB_ARES>, ++ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; ++ reset-names = "pipe", ++ "sleep", ++ "sticky", ++ "axi_m", ++ "axi_s", ++ "ahb", ++ "axi_m_sticky"; ++ status = "disabled"; + }; + }; + }; diff --git a/target/linux/ipq807x/patches-5.4/0003-v5.9-arm64-dts-ipq8074-enable-sdhci-node.patch b/target/linux/ipq807x/patches-5.4/0003-v5.9-arm64-dts-ipq8074-enable-sdhci-node.patch new file mode 100644 index 00000000000000..92aefcd897da6b --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0003-v5.9-arm64-dts-ipq8074-enable-sdhci-node.patch @@ -0,0 +1,56 @@ +From cbc142c89543eb8c506ae0e0f0a36c82d91b5171 Mon Sep 17 00:00:00 2001 +From: Sivaprakash Murugesan +Date: Tue, 9 Jun 2020 17:05:11 +0530 +Subject: [PATCH] arm64: dts: ipq8074: enable sdhci node + +Enable mmc device found on ipq8074 devices + +Signed-off-by: Sivaprakash Murugesan +Link: https://lore.kernel.org/r/1591702511-18571-1-git-send-email-sivaprak@codeaurora.org +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 4 ++++ + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 22 ++++++++++++++++++++++ + 2 files changed, 26 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts ++++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +@@ -82,3 +82,7 @@ + nand-bus-width = <8>; + }; + }; ++ ++&sdhc_1 { ++ status = "ok"; ++}; +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -169,6 +169,28 @@ + #reset-cells = <0x1>; + }; + ++ sdhc_1: sdhci@7824900 { ++ compatible = "qcom,sdhci-msm-v4"; ++ reg = <0x7824900 0x500>, <0x7824000 0x800>; ++ reg-names = "hc_mem", "core_mem"; ++ ++ interrupts = , ++ ; ++ interrupt-names = "hc_irq", "pwr_irq"; ++ ++ clocks = <&xo>, ++ <&gcc GCC_SDCC1_AHB_CLK>, ++ <&gcc GCC_SDCC1_APPS_CLK>; ++ clock-names = "xo", "iface", "core"; ++ max-frequency = <384000000>; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ bus-width = <8>; ++ ++ status = "disabled"; ++ }; ++ + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x2b000>; diff --git a/target/linux/ipq807x/patches-5.4/0005-v5.9-mtd-rawnand-qcom-set-BAM-mode-only-if-not-set-alread.patch b/target/linux/ipq807x/patches-5.4/0005-v5.9-mtd-rawnand-qcom-set-BAM-mode-only-if-not-set-alread.patch new file mode 100644 index 00000000000000..fd3ac1571a2a08 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0005-v5.9-mtd-rawnand-qcom-set-BAM-mode-only-if-not-set-alread.patch @@ -0,0 +1,42 @@ +From cb272395dceef1652247dad08a50ed4153ffbd43 Mon Sep 17 00:00:00 2001 +From: Sivaprakash Murugesan +Date: Fri, 12 Jun 2020 13:28:16 +0530 +Subject: [PATCH] mtd: rawnand: qcom: set BAM mode only if not set already + +BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver +is set by writing BAM_MODE_EN bit on NAND_CTRL register. + +NAND_CTRL is an operational register and in BAM mode operational +registers are read only. + +So, before enabling BAM mode by writing the NAND_CTRL register, check +if BAM mode was already enabled by the bootloader, and enable BAM mode +only if it is not enabled already. + +Signed-off-by: Sivaprakash Murugesan +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/1591948696-16015-3-git-send-email-sivaprak@codeaurora.org +--- + drivers/mtd/nand/raw/qcom_nandc.c | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/nand/raw/qcom_nandc.c ++++ b/drivers/mtd/nand/raw/qcom_nandc.c +@@ -2761,7 +2761,16 @@ static int qcom_nandc_setup(struct qcom_ + /* enable ADM or BAM DMA */ + if (nandc->props->is_bam) { + nand_ctrl = nandc_read(nandc, NAND_CTRL); +- nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); ++ ++ /* ++ *NAND_CTRL is an operational registers, and CPU ++ * access to operational registers are read only ++ * in BAM mode. So update the NAND_CTRL register ++ * only if it is not in BAM mode. In most cases BAM ++ * mode will be enabled in bootloader ++ */ ++ if (!(nand_ctrl & BAM_MODE_EN)) ++ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); + } else { + nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN); + } diff --git a/target/linux/ipq807x/patches-5.4/0006-v5.9-clk-qcom-Add-DT-bindings-for-ipq6018-apss-clock-cont.patch b/target/linux/ipq807x/patches-5.4/0006-v5.9-clk-qcom-Add-DT-bindings-for-ipq6018-apss-clock-cont.patch new file mode 100644 index 00000000000000..ef130a1c7b3d12 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0006-v5.9-clk-qcom-Add-DT-bindings-for-ipq6018-apss-clock-cont.patch @@ -0,0 +1,31 @@ +From 49bcaef86eba1a8097980f341e243ba01177a685 Mon Sep 17 00:00:00 2001 +From: Sivaprakash Murugesan +Date: Mon, 22 Jun 2020 09:58:11 +0530 +Subject: [PATCH] clk: qcom: Add DT bindings for ipq6018 apss clock controller + +Add dt-binding for ipq6018 apss clock controller + +Acked-by: Rob Herring +Signed-off-by: Sivaprakash Murugesan +Link: https://lore.kernel.org/r/1592800092-20533-4-git-send-email-sivaprak@codeaurora.org +Signed-off-by: Stephen Boyd +--- + include/dt-bindings/clock/qcom,apss-ipq.h | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h + +--- /dev/null ++++ b/include/dt-bindings/clock/qcom,apss-ipq.h +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (c) 2018, The Linux Foundation. All rights reserved. ++ */ ++ ++#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H ++#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H ++ ++#define APCS_ALIAS0_CLK_SRC 0 ++#define APCS_ALIAS0_CORE_CLK 1 ++ ++#endif diff --git a/target/linux/ipq807x/patches-5.4/0007-v5.7-net-qrtr-Migrate-nameservice-to-kernel-from-userspac.patch b/target/linux/ipq807x/patches-5.4/0007-v5.7-net-qrtr-Migrate-nameservice-to-kernel-from-userspac.patch new file mode 100644 index 00000000000000..22957d8fceebef --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0007-v5.7-net-qrtr-Migrate-nameservice-to-kernel-from-userspac.patch @@ -0,0 +1,882 @@ +From 0c2204a4ad710d95d348ea006f14ba926e842ffd Mon Sep 17 00:00:00 2001 +From: Manivannan Sadhasivam +Date: Thu, 20 Feb 2020 20:43:26 +0530 +Subject: [PATCH] net: qrtr: Migrate nameservice to kernel from userspace + +The QRTR nameservice has been maintained in userspace for some time. This +commit migrates it to Linux kernel. This change is required in order to +eliminate the need of starting a userspace daemon for making the WiFi +functional for ath11k based devices. Since the QRTR NS is not usually +packed in most of the distros, users need to clone, build and install it +to get the WiFi working. It will become a hassle when the user doesn't +have any other source of network connectivity. + +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: David S. Miller +--- + net/qrtr/Makefile | 2 +- + net/qrtr/ns.c | 751 ++++++++++++++++++++++++++++++++++++++++++++++ + net/qrtr/qrtr.c | 48 +-- + net/qrtr/qrtr.h | 4 + + 4 files changed, 766 insertions(+), 39 deletions(-) + create mode 100644 net/qrtr/ns.c + +--- a/net/qrtr/Makefile ++++ b/net/qrtr/Makefile +@@ -1,5 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0-only +-obj-$(CONFIG_QRTR) := qrtr.o ++obj-$(CONFIG_QRTR) := qrtr.o ns.o + + obj-$(CONFIG_QRTR_SMD) += qrtr-smd.o + qrtr-smd-y := smd.o +--- /dev/null ++++ b/net/qrtr/ns.c +@@ -0,0 +1,751 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* ++ * Copyright (c) 2015, Sony Mobile Communications Inc. ++ * Copyright (c) 2013, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2020, Linaro Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "qrtr.h" ++ ++static RADIX_TREE(nodes, GFP_KERNEL); ++ ++static struct { ++ struct socket *sock; ++ struct sockaddr_qrtr bcast_sq; ++ struct list_head lookups; ++ struct workqueue_struct *workqueue; ++ struct work_struct work; ++ int local_node; ++} qrtr_ns; ++ ++static const char * const qrtr_ctrl_pkt_strings[] = { ++ [QRTR_TYPE_HELLO] = "hello", ++ [QRTR_TYPE_BYE] = "bye", ++ [QRTR_TYPE_NEW_SERVER] = "new-server", ++ [QRTR_TYPE_DEL_SERVER] = "del-server", ++ [QRTR_TYPE_DEL_CLIENT] = "del-client", ++ [QRTR_TYPE_RESUME_TX] = "resume-tx", ++ [QRTR_TYPE_EXIT] = "exit", ++ [QRTR_TYPE_PING] = "ping", ++ [QRTR_TYPE_NEW_LOOKUP] = "new-lookup", ++ [QRTR_TYPE_DEL_LOOKUP] = "del-lookup", ++}; ++ ++struct qrtr_server_filter { ++ unsigned int service; ++ unsigned int instance; ++ unsigned int ifilter; ++}; ++ ++struct qrtr_lookup { ++ unsigned int service; ++ unsigned int instance; ++ ++ struct sockaddr_qrtr sq; ++ struct list_head li; ++}; ++ ++struct qrtr_server { ++ unsigned int service; ++ unsigned int instance; ++ ++ unsigned int node; ++ unsigned int port; ++ ++ struct list_head qli; ++}; ++ ++struct qrtr_node { ++ unsigned int id; ++ struct radix_tree_root servers; ++}; ++ ++static struct qrtr_node *node_get(unsigned int node_id) ++{ ++ struct qrtr_node *node; ++ ++ node = radix_tree_lookup(&nodes, node_id); ++ if (node) ++ return node; ++ ++ /* If node didn't exist, allocate and insert it to the tree */ ++ node = kzalloc(sizeof(*node), GFP_KERNEL); ++ if (!node) ++ return ERR_PTR(-ENOMEM); ++ ++ node->id = node_id; ++ ++ radix_tree_insert(&nodes, node_id, node); ++ ++ return node; ++} ++ ++static int server_match(const struct qrtr_server *srv, ++ const struct qrtr_server_filter *f) ++{ ++ unsigned int ifilter = f->ifilter; ++ ++ if (f->service != 0 && srv->service != f->service) ++ return 0; ++ if (!ifilter && f->instance) ++ ifilter = ~0; ++ ++ return (srv->instance & ifilter) == f->instance; ++} ++ ++static int service_announce_new(struct sockaddr_qrtr *dest, ++ struct qrtr_server *srv) ++{ ++ struct qrtr_ctrl_pkt pkt; ++ struct msghdr msg = { }; ++ struct kvec iv; ++ ++ trace_printk("advertising new server [%d:%x]@[%d:%d]\n", ++ srv->service, srv->instance, srv->node, srv->port); ++ ++ iv.iov_base = &pkt; ++ iv.iov_len = sizeof(pkt); ++ ++ memset(&pkt, 0, sizeof(pkt)); ++ pkt.cmd = cpu_to_le32(QRTR_TYPE_NEW_SERVER); ++ pkt.server.service = cpu_to_le32(srv->service); ++ pkt.server.instance = cpu_to_le32(srv->instance); ++ pkt.server.node = cpu_to_le32(srv->node); ++ pkt.server.port = cpu_to_le32(srv->port); ++ ++ msg.msg_name = (struct sockaddr *)dest; ++ msg.msg_namelen = sizeof(*dest); ++ ++ return kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); ++} ++ ++static int service_announce_del(struct sockaddr_qrtr *dest, ++ struct qrtr_server *srv) ++{ ++ struct qrtr_ctrl_pkt pkt; ++ struct msghdr msg = { }; ++ struct kvec iv; ++ int ret; ++ ++ trace_printk("advertising removal of server [%d:%x]@[%d:%d]\n", ++ srv->service, srv->instance, srv->node, srv->port); ++ ++ iv.iov_base = &pkt; ++ iv.iov_len = sizeof(pkt); ++ ++ memset(&pkt, 0, sizeof(pkt)); ++ pkt.cmd = cpu_to_le32(QRTR_TYPE_DEL_SERVER); ++ pkt.server.service = cpu_to_le32(srv->service); ++ pkt.server.instance = cpu_to_le32(srv->instance); ++ pkt.server.node = cpu_to_le32(srv->node); ++ pkt.server.port = cpu_to_le32(srv->port); ++ ++ msg.msg_name = (struct sockaddr *)dest; ++ msg.msg_namelen = sizeof(*dest); ++ ++ ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); ++ if (ret < 0) ++ pr_err("failed to announce del serivce\n"); ++ ++ return ret; ++} ++ ++static void lookup_notify(struct sockaddr_qrtr *to, struct qrtr_server *srv, ++ bool new) ++{ ++ struct qrtr_ctrl_pkt pkt; ++ struct msghdr msg = { }; ++ struct kvec iv; ++ int ret; ++ ++ iv.iov_base = &pkt; ++ iv.iov_len = sizeof(pkt); ++ ++ memset(&pkt, 0, sizeof(pkt)); ++ pkt.cmd = new ? cpu_to_le32(QRTR_TYPE_NEW_SERVER) : ++ cpu_to_le32(QRTR_TYPE_DEL_SERVER); ++ if (srv) { ++ pkt.server.service = cpu_to_le32(srv->service); ++ pkt.server.instance = cpu_to_le32(srv->instance); ++ pkt.server.node = cpu_to_le32(srv->node); ++ pkt.server.port = cpu_to_le32(srv->port); ++ } ++ ++ msg.msg_name = (struct sockaddr *)to; ++ msg.msg_namelen = sizeof(*to); ++ ++ ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); ++ if (ret < 0) ++ pr_err("failed to send lookup notification\n"); ++} ++ ++static int announce_servers(struct sockaddr_qrtr *sq) ++{ ++ struct radix_tree_iter iter; ++ struct qrtr_server *srv; ++ struct qrtr_node *node; ++ void __rcu **slot; ++ int ret; ++ ++ node = node_get(qrtr_ns.local_node); ++ if (!node) ++ return 0; ++ ++ /* Announce the list of servers registered in this node */ ++ radix_tree_for_each_slot(slot, &node->servers, &iter, 0) { ++ srv = radix_tree_deref_slot(slot); ++ ++ ret = service_announce_new(sq, srv); ++ if (ret < 0) { ++ pr_err("failed to announce new service\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static struct qrtr_server *server_add(unsigned int service, ++ unsigned int instance, ++ unsigned int node_id, ++ unsigned int port) ++{ ++ struct qrtr_server *srv; ++ struct qrtr_server *old; ++ struct qrtr_node *node; ++ ++ if (!service || !port) ++ return NULL; ++ ++ srv = kzalloc(sizeof(*srv), GFP_KERNEL); ++ if (!srv) ++ return ERR_PTR(-ENOMEM); ++ ++ srv->service = service; ++ srv->instance = instance; ++ srv->node = node_id; ++ srv->port = port; ++ ++ node = node_get(node_id); ++ if (!node) ++ goto err; ++ ++ /* Delete the old server on the same port */ ++ old = radix_tree_lookup(&node->servers, port); ++ if (old) { ++ radix_tree_delete(&node->servers, port); ++ kfree(old); ++ } ++ ++ radix_tree_insert(&node->servers, port, srv); ++ ++ trace_printk("add server [%d:%x]@[%d:%d]\n", srv->service, ++ srv->instance, srv->node, srv->port); ++ ++ return srv; ++ ++err: ++ kfree(srv); ++ return NULL; ++} ++ ++static int server_del(struct qrtr_node *node, unsigned int port) ++{ ++ struct qrtr_lookup *lookup; ++ struct qrtr_server *srv; ++ struct list_head *li; ++ ++ srv = radix_tree_lookup(&node->servers, port); ++ if (!srv) ++ return -ENOENT; ++ ++ radix_tree_delete(&node->servers, port); ++ ++ /* Broadcast the removal of local servers */ ++ if (srv->node == qrtr_ns.local_node) ++ service_announce_del(&qrtr_ns.bcast_sq, srv); ++ ++ /* Announce the service's disappearance to observers */ ++ list_for_each(li, &qrtr_ns.lookups) { ++ lookup = container_of(li, struct qrtr_lookup, li); ++ if (lookup->service && lookup->service != srv->service) ++ continue; ++ if (lookup->instance && lookup->instance != srv->instance) ++ continue; ++ ++ lookup_notify(&lookup->sq, srv, false); ++ } ++ ++ kfree(srv); ++ ++ return 0; ++} ++ ++/* Announce the list of servers registered on the local node */ ++static int ctrl_cmd_hello(struct sockaddr_qrtr *sq) ++{ ++ return announce_servers(sq); ++} ++ ++static int ctrl_cmd_bye(struct sockaddr_qrtr *from) ++{ ++ struct qrtr_node *local_node; ++ struct radix_tree_iter iter; ++ struct qrtr_ctrl_pkt pkt; ++ struct qrtr_server *srv; ++ struct sockaddr_qrtr sq; ++ struct msghdr msg = { }; ++ struct qrtr_node *node; ++ void __rcu **slot; ++ struct kvec iv; ++ int ret; ++ ++ iv.iov_base = &pkt; ++ iv.iov_len = sizeof(pkt); ++ ++ node = node_get(from->sq_node); ++ if (!node) ++ return 0; ++ ++ /* Advertise removal of this client to all servers of remote node */ ++ radix_tree_for_each_slot(slot, &node->servers, &iter, 0) { ++ srv = radix_tree_deref_slot(slot); ++ server_del(node, srv->port); ++ } ++ ++ /* Advertise the removal of this client to all local servers */ ++ local_node = node_get(qrtr_ns.local_node); ++ if (!local_node) ++ return 0; ++ ++ memset(&pkt, 0, sizeof(pkt)); ++ pkt.cmd = cpu_to_le32(QRTR_TYPE_BYE); ++ pkt.client.node = cpu_to_le32(from->sq_node); ++ ++ radix_tree_for_each_slot(slot, &local_node->servers, &iter, 0) { ++ srv = radix_tree_deref_slot(slot); ++ ++ sq.sq_family = AF_QIPCRTR; ++ sq.sq_node = srv->node; ++ sq.sq_port = srv->port; ++ ++ msg.msg_name = (struct sockaddr *)&sq; ++ msg.msg_namelen = sizeof(sq); ++ ++ ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); ++ if (ret < 0) { ++ pr_err("failed to send bye cmd\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int ctrl_cmd_del_client(struct sockaddr_qrtr *from, ++ unsigned int node_id, unsigned int port) ++{ ++ struct qrtr_node *local_node; ++ struct radix_tree_iter iter; ++ struct qrtr_lookup *lookup; ++ struct qrtr_ctrl_pkt pkt; ++ struct msghdr msg = { }; ++ struct qrtr_server *srv; ++ struct sockaddr_qrtr sq; ++ struct qrtr_node *node; ++ struct list_head *tmp; ++ struct list_head *li; ++ void __rcu **slot; ++ struct kvec iv; ++ int ret; ++ ++ iv.iov_base = &pkt; ++ iv.iov_len = sizeof(pkt); ++ ++ /* Don't accept spoofed messages */ ++ if (from->sq_node != node_id) ++ return -EINVAL; ++ ++ /* Local DEL_CLIENT messages comes from the port being closed */ ++ if (from->sq_node == qrtr_ns.local_node && from->sq_port != port) ++ return -EINVAL; ++ ++ /* Remove any lookups by this client */ ++ list_for_each_safe(li, tmp, &qrtr_ns.lookups) { ++ lookup = container_of(li, struct qrtr_lookup, li); ++ if (lookup->sq.sq_node != node_id) ++ continue; ++ if (lookup->sq.sq_port != port) ++ continue; ++ ++ list_del(&lookup->li); ++ kfree(lookup); ++ } ++ ++ /* Remove the server belonging to this port */ ++ node = node_get(node_id); ++ if (node) ++ server_del(node, port); ++ ++ /* Advertise the removal of this client to all local servers */ ++ local_node = node_get(qrtr_ns.local_node); ++ if (!local_node) ++ return 0; ++ ++ memset(&pkt, 0, sizeof(pkt)); ++ pkt.cmd = cpu_to_le32(QRTR_TYPE_DEL_CLIENT); ++ pkt.client.node = cpu_to_le32(node_id); ++ pkt.client.port = cpu_to_le32(port); ++ ++ radix_tree_for_each_slot(slot, &local_node->servers, &iter, 0) { ++ srv = radix_tree_deref_slot(slot); ++ ++ sq.sq_family = AF_QIPCRTR; ++ sq.sq_node = srv->node; ++ sq.sq_port = srv->port; ++ ++ msg.msg_name = (struct sockaddr *)&sq; ++ msg.msg_namelen = sizeof(sq); ++ ++ ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); ++ if (ret < 0) { ++ pr_err("failed to send del client cmd\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int ctrl_cmd_new_server(struct sockaddr_qrtr *from, ++ unsigned int service, unsigned int instance, ++ unsigned int node_id, unsigned int port) ++{ ++ struct qrtr_lookup *lookup; ++ struct qrtr_server *srv; ++ struct list_head *li; ++ int ret = 0; ++ ++ /* Ignore specified node and port for local servers */ ++ if (from->sq_node == qrtr_ns.local_node) { ++ node_id = from->sq_node; ++ port = from->sq_port; ++ } ++ ++ /* Don't accept spoofed messages */ ++ if (from->sq_node != node_id) ++ return -EINVAL; ++ ++ srv = server_add(service, instance, node_id, port); ++ if (!srv) ++ return -EINVAL; ++ ++ if (srv->node == qrtr_ns.local_node) { ++ ret = service_announce_new(&qrtr_ns.bcast_sq, srv); ++ if (ret < 0) { ++ pr_err("failed to announce new service\n"); ++ return ret; ++ } ++ } ++ ++ /* Notify any potential lookups about the new server */ ++ list_for_each(li, &qrtr_ns.lookups) { ++ lookup = container_of(li, struct qrtr_lookup, li); ++ if (lookup->service && lookup->service != service) ++ continue; ++ if (lookup->instance && lookup->instance != instance) ++ continue; ++ ++ lookup_notify(&lookup->sq, srv, true); ++ } ++ ++ return ret; ++} ++ ++static int ctrl_cmd_del_server(struct sockaddr_qrtr *from, ++ unsigned int service, unsigned int instance, ++ unsigned int node_id, unsigned int port) ++{ ++ struct qrtr_node *node; ++ ++ /* Ignore specified node and port for local servers*/ ++ if (from->sq_node == qrtr_ns.local_node) { ++ node_id = from->sq_node; ++ port = from->sq_port; ++ } ++ ++ /* Don't accept spoofed messages */ ++ if (from->sq_node != node_id) ++ return -EINVAL; ++ ++ /* Local servers may only unregister themselves */ ++ if (from->sq_node == qrtr_ns.local_node && from->sq_port != port) ++ return -EINVAL; ++ ++ node = node_get(node_id); ++ if (!node) ++ return -ENOENT; ++ ++ return server_del(node, port); ++} ++ ++static int ctrl_cmd_new_lookup(struct sockaddr_qrtr *from, ++ unsigned int service, unsigned int instance) ++{ ++ struct radix_tree_iter node_iter; ++ struct qrtr_server_filter filter; ++ struct radix_tree_iter srv_iter; ++ struct qrtr_lookup *lookup; ++ struct qrtr_node *node; ++ void __rcu **node_slot; ++ void __rcu **srv_slot; ++ ++ /* Accept only local observers */ ++ if (from->sq_node != qrtr_ns.local_node) ++ return -EINVAL; ++ ++ lookup = kzalloc(sizeof(*lookup), GFP_KERNEL); ++ if (!lookup) ++ return -ENOMEM; ++ ++ lookup->sq = *from; ++ lookup->service = service; ++ lookup->instance = instance; ++ list_add_tail(&lookup->li, &qrtr_ns.lookups); ++ ++ memset(&filter, 0, sizeof(filter)); ++ filter.service = service; ++ filter.instance = instance; ++ ++ radix_tree_for_each_slot(node_slot, &nodes, &node_iter, 0) { ++ node = radix_tree_deref_slot(node_slot); ++ ++ radix_tree_for_each_slot(srv_slot, &node->servers, ++ &srv_iter, 0) { ++ struct qrtr_server *srv; ++ ++ srv = radix_tree_deref_slot(srv_slot); ++ if (!server_match(srv, &filter)) ++ continue; ++ ++ lookup_notify(from, srv, true); ++ } ++ } ++ ++ /* Empty notification, to indicate end of listing */ ++ lookup_notify(from, NULL, true); ++ ++ return 0; ++} ++ ++static void ctrl_cmd_del_lookup(struct sockaddr_qrtr *from, ++ unsigned int service, unsigned int instance) ++{ ++ struct qrtr_lookup *lookup; ++ struct list_head *tmp; ++ struct list_head *li; ++ ++ list_for_each_safe(li, tmp, &qrtr_ns.lookups) { ++ lookup = container_of(li, struct qrtr_lookup, li); ++ if (lookup->sq.sq_node != from->sq_node) ++ continue; ++ if (lookup->sq.sq_port != from->sq_port) ++ continue; ++ if (lookup->service != service) ++ continue; ++ if (lookup->instance && lookup->instance != instance) ++ continue; ++ ++ list_del(&lookup->li); ++ kfree(lookup); ++ } ++} ++ ++static int say_hello(void) ++{ ++ struct qrtr_ctrl_pkt pkt; ++ struct msghdr msg = { }; ++ struct kvec iv; ++ int ret; ++ ++ iv.iov_base = &pkt; ++ iv.iov_len = sizeof(pkt); ++ ++ memset(&pkt, 0, sizeof(pkt)); ++ pkt.cmd = cpu_to_le32(QRTR_TYPE_HELLO); ++ ++ msg.msg_name = (struct sockaddr *)&qrtr_ns.bcast_sq; ++ msg.msg_namelen = sizeof(qrtr_ns.bcast_sq); ++ ++ ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); ++ if (ret < 0) ++ pr_err("failed to send hello msg\n"); ++ ++ return ret; ++} ++ ++static void qrtr_ns_worker(struct work_struct *work) ++{ ++ const struct qrtr_ctrl_pkt *pkt; ++ size_t recv_buf_size = 4096; ++ struct sockaddr_qrtr sq; ++ struct msghdr msg = { }; ++ unsigned int cmd; ++ ssize_t msglen; ++ void *recv_buf; ++ struct kvec iv; ++ int ret; ++ ++ msg.msg_name = (struct sockaddr *)&sq; ++ msg.msg_namelen = sizeof(sq); ++ ++ recv_buf = kzalloc(recv_buf_size, GFP_KERNEL); ++ if (!recv_buf) ++ return; ++ ++ for (;;) { ++ iv.iov_base = recv_buf; ++ iv.iov_len = recv_buf_size; ++ ++ msglen = kernel_recvmsg(qrtr_ns.sock, &msg, &iv, 1, ++ iv.iov_len, MSG_DONTWAIT); ++ ++ if (msglen == -EAGAIN) ++ break; ++ ++ if (msglen < 0) { ++ pr_err("error receiving packet: %zd\n", msglen); ++ break; ++ } ++ ++ pkt = recv_buf; ++ cmd = le32_to_cpu(pkt->cmd); ++ if (cmd < ARRAY_SIZE(qrtr_ctrl_pkt_strings) && ++ qrtr_ctrl_pkt_strings[cmd]) ++ trace_printk("%s from %d:%d\n", ++ qrtr_ctrl_pkt_strings[cmd], sq.sq_node, ++ sq.sq_port); ++ ++ ret = 0; ++ switch (cmd) { ++ case QRTR_TYPE_HELLO: ++ ret = ctrl_cmd_hello(&sq); ++ break; ++ case QRTR_TYPE_BYE: ++ ret = ctrl_cmd_bye(&sq); ++ break; ++ case QRTR_TYPE_DEL_CLIENT: ++ ret = ctrl_cmd_del_client(&sq, ++ le32_to_cpu(pkt->client.node), ++ le32_to_cpu(pkt->client.port)); ++ break; ++ case QRTR_TYPE_NEW_SERVER: ++ ret = ctrl_cmd_new_server(&sq, ++ le32_to_cpu(pkt->server.service), ++ le32_to_cpu(pkt->server.instance), ++ le32_to_cpu(pkt->server.node), ++ le32_to_cpu(pkt->server.port)); ++ break; ++ case QRTR_TYPE_DEL_SERVER: ++ ret = ctrl_cmd_del_server(&sq, ++ le32_to_cpu(pkt->server.service), ++ le32_to_cpu(pkt->server.instance), ++ le32_to_cpu(pkt->server.node), ++ le32_to_cpu(pkt->server.port)); ++ break; ++ case QRTR_TYPE_EXIT: ++ case QRTR_TYPE_PING: ++ case QRTR_TYPE_RESUME_TX: ++ break; ++ case QRTR_TYPE_NEW_LOOKUP: ++ ret = ctrl_cmd_new_lookup(&sq, ++ le32_to_cpu(pkt->server.service), ++ le32_to_cpu(pkt->server.instance)); ++ break; ++ case QRTR_TYPE_DEL_LOOKUP: ++ ctrl_cmd_del_lookup(&sq, ++ le32_to_cpu(pkt->server.service), ++ le32_to_cpu(pkt->server.instance)); ++ break; ++ } ++ ++ if (ret < 0) ++ pr_err("failed while handling packet from %d:%d", ++ sq.sq_node, sq.sq_port); ++ } ++ ++ kfree(recv_buf); ++} ++ ++static void qrtr_ns_data_ready(struct sock *sk) ++{ ++ queue_work(qrtr_ns.workqueue, &qrtr_ns.work); ++} ++ ++void qrtr_ns_init(struct work_struct *work) ++{ ++ struct sockaddr_qrtr sq; ++ int ret; ++ ++ INIT_LIST_HEAD(&qrtr_ns.lookups); ++ INIT_WORK(&qrtr_ns.work, qrtr_ns_worker); ++ ++ ret = sock_create_kern(&init_net, AF_QIPCRTR, SOCK_DGRAM, ++ PF_QIPCRTR, &qrtr_ns.sock); ++ if (ret < 0) ++ return; ++ ++ ret = kernel_getsockname(qrtr_ns.sock, (struct sockaddr *)&sq); ++ if (ret < 0) { ++ pr_err("failed to get socket name\n"); ++ goto err_sock; ++ } ++ ++ qrtr_ns.sock->sk->sk_data_ready = qrtr_ns_data_ready; ++ ++ sq.sq_port = QRTR_PORT_CTRL; ++ qrtr_ns.local_node = sq.sq_node; ++ ++ ret = kernel_bind(qrtr_ns.sock, (struct sockaddr *)&sq, sizeof(sq)); ++ if (ret < 0) { ++ pr_err("failed to bind to socket\n"); ++ goto err_sock; ++ } ++ ++ qrtr_ns.bcast_sq.sq_family = AF_QIPCRTR; ++ qrtr_ns.bcast_sq.sq_node = QRTR_NODE_BCAST; ++ qrtr_ns.bcast_sq.sq_port = QRTR_PORT_CTRL; ++ ++ qrtr_ns.workqueue = alloc_workqueue("qrtr_ns_handler", WQ_UNBOUND, 1); ++ if (!qrtr_ns.workqueue) ++ goto err_sock; ++ ++ ret = say_hello(); ++ if (ret < 0) ++ goto err_wq; ++ ++ return; ++ ++err_wq: ++ destroy_workqueue(qrtr_ns.workqueue); ++err_sock: ++ sock_release(qrtr_ns.sock); ++} ++EXPORT_SYMBOL_GPL(qrtr_ns_init); ++ ++void qrtr_ns_remove(void) ++{ ++ cancel_work_sync(&qrtr_ns.work); ++ destroy_workqueue(qrtr_ns.workqueue); ++ sock_release(qrtr_ns.sock); ++} ++EXPORT_SYMBOL_GPL(qrtr_ns_remove); ++ ++MODULE_AUTHOR("Manivannan Sadhasivam "); ++MODULE_DESCRIPTION("Qualcomm IPC Router Nameservice"); ++MODULE_LICENSE("Dual BSD/GPL"); +--- a/net/qrtr/qrtr.c ++++ b/net/qrtr/qrtr.c +@@ -8,6 +8,7 @@ + #include + #include /* For TIOCINQ/OUTQ */ + #include ++#include + + #include + +@@ -107,6 +108,8 @@ static DEFINE_MUTEX(qrtr_node_lock); + static DEFINE_IDR(qrtr_ports); + static DEFINE_MUTEX(qrtr_port_lock); + ++static struct delayed_work qrtr_ns_work; ++ + /** + * struct qrtr_node - endpoint node + * @ep_lock: lock for endpoint management and callbacks +@@ -1072,38 +1075,6 @@ static int qrtr_create(struct net *net, + return 0; + } + +-static const struct nla_policy qrtr_policy[IFA_MAX + 1] = { +- [IFA_LOCAL] = { .type = NLA_U32 }, +-}; +- +-static int qrtr_addr_doit(struct sk_buff *skb, struct nlmsghdr *nlh, +- struct netlink_ext_ack *extack) +-{ +- struct nlattr *tb[IFA_MAX + 1]; +- struct ifaddrmsg *ifm; +- int rc; +- +- if (!netlink_capable(skb, CAP_NET_ADMIN)) +- return -EPERM; +- +- if (!netlink_capable(skb, CAP_SYS_ADMIN)) +- return -EPERM; +- +- ASSERT_RTNL(); +- +- rc = nlmsg_parse_deprecated(nlh, sizeof(*ifm), tb, IFA_MAX, +- qrtr_policy, extack); +- if (rc < 0) +- return rc; +- +- ifm = nlmsg_data(nlh); +- if (!tb[IFA_LOCAL]) +- return -EINVAL; +- +- qrtr_local_nid = nla_get_u32(tb[IFA_LOCAL]); +- return 0; +-} +- + static const struct net_proto_family qrtr_family = { + .owner = THIS_MODULE, + .family = AF_QIPCRTR, +@@ -1124,11 +1095,11 @@ static int __init qrtr_proto_init(void) + return rc; + } + +- rc = rtnl_register_module(THIS_MODULE, PF_QIPCRTR, RTM_NEWADDR, qrtr_addr_doit, NULL, 0); +- if (rc) { +- sock_unregister(qrtr_family.family); +- proto_unregister(&qrtr_proto); +- } ++ /* FIXME: Currently, this 2s delay is required to catch the NEW_SERVER ++ * messages from routers. But the fix could be somewhere else. ++ */ ++ INIT_DELAYED_WORK(&qrtr_ns_work, qrtr_ns_init); ++ schedule_delayed_work(&qrtr_ns_work, msecs_to_jiffies(2000)); + + return rc; + } +@@ -1136,7 +1107,8 @@ postcore_initcall(qrtr_proto_init); + + static void __exit qrtr_proto_fini(void) + { +- rtnl_unregister(PF_QIPCRTR, RTM_NEWADDR); ++ cancel_delayed_work_sync(&qrtr_ns_work); ++ qrtr_ns_remove(); + sock_unregister(qrtr_family.family); + proto_unregister(&qrtr_proto); + } +--- a/net/qrtr/qrtr.h ++++ b/net/qrtr/qrtr.h +@@ -29,4 +29,8 @@ void qrtr_endpoint_unregister(struct qrt + + int qrtr_endpoint_post(struct qrtr_endpoint *ep, const void *data, size_t len); + ++void qrtr_ns_init(struct work_struct *work); ++ ++void qrtr_ns_remove(void); ++ + #endif diff --git a/target/linux/ipq807x/patches-5.4/0008-v5.7-net-qrtr-Fix-error-pointer-vs-NULL-bugs.patch b/target/linux/ipq807x/patches-5.4/0008-v5.7-net-qrtr-Fix-error-pointer-vs-NULL-bugs.patch new file mode 100644 index 00000000000000..49ad3915bf8dcb --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0008-v5.7-net-qrtr-Fix-error-pointer-vs-NULL-bugs.patch @@ -0,0 +1,35 @@ +From 9baeea50718fdd55c7ae4d61c15f2a71aef6e050 Mon Sep 17 00:00:00 2001 +From: Dan Carpenter +Date: Wed, 26 Feb 2020 17:51:53 +0300 +Subject: [PATCH] net: qrtr: Fix error pointer vs NULL bugs + +The callers only expect NULL pointers, so returning an error pointer +will lead to an Oops. + +Fixes: 0c2204a4ad71 ("net: qrtr: Migrate nameservice to kernel from userspace") +Signed-off-by: Dan Carpenter +Signed-off-by: David S. Miller +--- + net/qrtr/ns.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/net/qrtr/ns.c ++++ b/net/qrtr/ns.c +@@ -76,7 +76,7 @@ static struct qrtr_node *node_get(unsign + /* If node didn't exist, allocate and insert it to the tree */ + node = kzalloc(sizeof(*node), GFP_KERNEL); + if (!node) +- return ERR_PTR(-ENOMEM); ++ return NULL; + + node->id = node_id; + +@@ -224,7 +224,7 @@ static struct qrtr_server *server_add(un + + srv = kzalloc(sizeof(*srv), GFP_KERNEL); + if (!srv) +- return ERR_PTR(-ENOMEM); ++ return NULL; + + srv->service = service; + srv->instance = instance; diff --git a/target/linux/ipq807x/patches-5.4/0009-v5.7-net-qrtr-Respond-to-HELLO-message.patch b/target/linux/ipq807x/patches-5.4/0009-v5.7-net-qrtr-Respond-to-HELLO-message.patch new file mode 100644 index 00000000000000..59e5b688fcb5eb --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0009-v5.7-net-qrtr-Respond-to-HELLO-message.patch @@ -0,0 +1,104 @@ +From a1dc1d6a05a730b62b45828975a088db577d3139 Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Sun, 1 Mar 2020 23:03:04 -0800 +Subject: [PATCH] net: qrtr: Respond to HELLO message + +Lost in the translation from the user space implementation was the +detail that HELLO mesages must be exchanged between each node pair. As +such the incoming HELLO must be replied to. + +Similar to the previous implementation no effort is made to prevent two +Linux boxes from continuously sending HELLO messages back and forth, +this is left to a follow up patch. + +say_hello() is moved, to facilitate the new call site. + +Fixes: 0c2204a4ad71 ("net: qrtr: Migrate nameservice to kernel from userspace") +Reviewed-by: Manivannan Sadhasivam +Tested-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Andersson +Signed-off-by: David S. Miller +--- + net/qrtr/ns.c | 54 ++++++++++++++++++++++++++++----------------------- + 1 file changed, 30 insertions(+), 24 deletions(-) + +--- a/net/qrtr/ns.c ++++ b/net/qrtr/ns.c +@@ -286,9 +286,38 @@ static int server_del(struct qrtr_node * + return 0; + } + ++static int say_hello(struct sockaddr_qrtr *dest) ++{ ++ struct qrtr_ctrl_pkt pkt; ++ struct msghdr msg = { }; ++ struct kvec iv; ++ int ret; ++ ++ iv.iov_base = &pkt; ++ iv.iov_len = sizeof(pkt); ++ ++ memset(&pkt, 0, sizeof(pkt)); ++ pkt.cmd = cpu_to_le32(QRTR_TYPE_HELLO); ++ ++ msg.msg_name = (struct sockaddr *)dest; ++ msg.msg_namelen = sizeof(*dest); ++ ++ ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); ++ if (ret < 0) ++ pr_err("failed to send hello msg\n"); ++ ++ return ret; ++} ++ + /* Announce the list of servers registered on the local node */ + static int ctrl_cmd_hello(struct sockaddr_qrtr *sq) + { ++ int ret; ++ ++ ret = say_hello(sq); ++ if (ret < 0) ++ return ret; ++ + return announce_servers(sq); + } + +@@ -566,29 +595,6 @@ static void ctrl_cmd_del_lookup(struct s + } + } + +-static int say_hello(void) +-{ +- struct qrtr_ctrl_pkt pkt; +- struct msghdr msg = { }; +- struct kvec iv; +- int ret; +- +- iv.iov_base = &pkt; +- iv.iov_len = sizeof(pkt); +- +- memset(&pkt, 0, sizeof(pkt)); +- pkt.cmd = cpu_to_le32(QRTR_TYPE_HELLO); +- +- msg.msg_name = (struct sockaddr *)&qrtr_ns.bcast_sq; +- msg.msg_namelen = sizeof(qrtr_ns.bcast_sq); +- +- ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt)); +- if (ret < 0) +- pr_err("failed to send hello msg\n"); +- +- return ret; +-} +- + static void qrtr_ns_worker(struct work_struct *work) + { + const struct qrtr_ctrl_pkt *pkt; +@@ -725,7 +731,7 @@ void qrtr_ns_init(struct work_struct *wo + if (!qrtr_ns.workqueue) + goto err_sock; + +- ret = say_hello(); ++ ret = say_hello(&qrtr_ns.bcast_sq); + if (ret < 0) + goto err_wq; + diff --git a/target/linux/ipq807x/patches-5.4/0010-v5.7-net-qrtr-Fix-FIXME-related-to-qrtr_ns_init.patch b/target/linux/ipq807x/patches-5.4/0010-v5.7-net-qrtr-Fix-FIXME-related-to-qrtr_ns_init.patch new file mode 100644 index 00000000000000..9d71b0a5799fbd --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0010-v5.7-net-qrtr-Fix-FIXME-related-to-qrtr_ns_init.patch @@ -0,0 +1,82 @@ +From 71046abfffe9d34ae90c82cf9c8e44355c2e114c Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Sun, 1 Mar 2020 23:03:05 -0800 +Subject: [PATCH] net: qrtr: Fix FIXME related to qrtr_ns_init() + +The 2 second delay before calling qrtr_ns_init() meant that the remote +processors would register as endpoints in qrtr and the say_hello() call +would therefor broadcast the outgoing HELLO to them. With the HELLO +handshake corrected this delay is no longer needed. + +Reviewed-by: Manivannan Sadhasivam +Tested-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Andersson +Signed-off-by: David S. Miller +--- + net/qrtr/ns.c | 2 +- + net/qrtr/qrtr.c | 10 +--------- + net/qrtr/qrtr.h | 2 +- + 3 files changed, 3 insertions(+), 11 deletions(-) + +--- a/net/qrtr/ns.c ++++ b/net/qrtr/ns.c +@@ -693,7 +693,7 @@ static void qrtr_ns_data_ready(struct so + queue_work(qrtr_ns.workqueue, &qrtr_ns.work); + } + +-void qrtr_ns_init(struct work_struct *work) ++void qrtr_ns_init(void) + { + struct sockaddr_qrtr sq; + int ret; +--- a/net/qrtr/qrtr.c ++++ b/net/qrtr/qrtr.c +@@ -8,7 +8,6 @@ + #include + #include /* For TIOCINQ/OUTQ */ + #include +-#include + + #include + +@@ -108,8 +107,6 @@ static DEFINE_MUTEX(qrtr_node_lock); + static DEFINE_IDR(qrtr_ports); + static DEFINE_MUTEX(qrtr_port_lock); + +-static struct delayed_work qrtr_ns_work; +- + /** + * struct qrtr_node - endpoint node + * @ep_lock: lock for endpoint management and callbacks +@@ -1095,11 +1092,7 @@ static int __init qrtr_proto_init(void) + return rc; + } + +- /* FIXME: Currently, this 2s delay is required to catch the NEW_SERVER +- * messages from routers. But the fix could be somewhere else. +- */ +- INIT_DELAYED_WORK(&qrtr_ns_work, qrtr_ns_init); +- schedule_delayed_work(&qrtr_ns_work, msecs_to_jiffies(2000)); ++ qrtr_ns_init(); + + return rc; + } +@@ -1107,7 +1100,6 @@ postcore_initcall(qrtr_proto_init); + + static void __exit qrtr_proto_fini(void) + { +- cancel_delayed_work_sync(&qrtr_ns_work); + qrtr_ns_remove(); + sock_unregister(qrtr_family.family); + proto_unregister(&qrtr_proto); +--- a/net/qrtr/qrtr.h ++++ b/net/qrtr/qrtr.h +@@ -29,7 +29,7 @@ void qrtr_endpoint_unregister(struct qrt + + int qrtr_endpoint_post(struct qrtr_endpoint *ep, const void *data, size_t len); + +-void qrtr_ns_init(struct work_struct *work); ++void qrtr_ns_init(void); + + void qrtr_ns_remove(void); + diff --git a/target/linux/ipq807x/patches-5.4/0011-v5.7-remoteproc-Use-size_t-type-for-len-in-da_to_va.patch b/target/linux/ipq807x/patches-5.4/0011-v5.7-remoteproc-Use-size_t-type-for-len-in-da_to_va.patch new file mode 100644 index 00000000000000..020fc266584e54 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0011-v5.7-remoteproc-Use-size_t-type-for-len-in-da_to_va.patch @@ -0,0 +1,222 @@ +From 9ce3bf225e5a908756b90b8f7bbc38834427296b Mon Sep 17 00:00:00 2001 +From: Clement Leger +Date: Mon, 2 Mar 2020 10:38:55 +0100 +Subject: [PATCH] remoteproc: Use size_t type for len in da_to_va + +With upcoming changes in elf loader for elf64 support, section size will +be a u64. When used with da_to_va, this will potentially lead to +overflow if using the current "int" type for len argument. Change +da_to_va prototype to use a size_t for len and fix all users of this +function. + +Reviewed-by: Bjorn Andersson +Reviewed-by: Mathieu Poirier +Signed-off-by: Clement Leger +Link: https://lore.kernel.org/r/20200302093902.27849-2-cleger@kalray.eu +Signed-off-by: Bjorn Andersson +--- + drivers/remoteproc/imx_rproc.c | 11 ++++++----- + drivers/remoteproc/keystone_remoteproc.c | 4 ++-- + drivers/remoteproc/qcom_q6v5_adsp.c | 2 +- + drivers/remoteproc/qcom_q6v5_mss.c | 2 +- + drivers/remoteproc/qcom_q6v5_pas.c | 2 +- + drivers/remoteproc/qcom_q6v5_wcss.c | 2 +- + drivers/remoteproc/qcom_wcnss.c | 2 +- + drivers/remoteproc/remoteproc_core.c | 2 +- + drivers/remoteproc/remoteproc_internal.h | 2 +- + drivers/remoteproc/st_slim_rproc.c | 4 ++-- + drivers/remoteproc/wkup_m3_rproc.c | 4 ++-- + include/linux/remoteproc.h | 2 +- + 12 files changed, 20 insertions(+), 19 deletions(-) + +--- a/drivers/remoteproc/imx_rproc.c ++++ b/drivers/remoteproc/imx_rproc.c +@@ -186,7 +186,7 @@ static int imx_rproc_stop(struct rproc * + } + + static int imx_rproc_da_to_sys(struct imx_rproc *priv, u64 da, +- int len, u64 *sys) ++ size_t len, u64 *sys) + { + const struct imx_rproc_dcfg *dcfg = priv->dcfg; + int i; +@@ -203,19 +203,19 @@ static int imx_rproc_da_to_sys(struct im + } + } + +- dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%x\n", ++ dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%zx\n", + da, len); + return -ENOENT; + } + +-static void *imx_rproc_da_to_va(struct rproc *rproc, u64 da, int len) ++static void *imx_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) + { + struct imx_rproc *priv = rproc->priv; + void *va = NULL; + u64 sys; + int i; + +- if (len <= 0) ++ if (len == 0) + return NULL; + + /* +@@ -235,7 +235,8 @@ static void *imx_rproc_da_to_va(struct r + } + } + +- dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%x va = 0x%p\n", da, len, va); ++ dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%p\n", ++ da, len, va); + + return va; + } +--- a/drivers/remoteproc/keystone_remoteproc.c ++++ b/drivers/remoteproc/keystone_remoteproc.c +@@ -246,7 +246,7 @@ static void keystone_rproc_kick(struct r + * can be used either by the remoteproc core for loading (when using kernel + * remoteproc loader), or by any rpmsg bus drivers. + */ +-static void *keystone_rproc_da_to_va(struct rproc *rproc, u64 da, int len) ++static void *keystone_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) + { + struct keystone_rproc *ksproc = rproc->priv; + void __iomem *va = NULL; +@@ -255,7 +255,7 @@ static void *keystone_rproc_da_to_va(str + size_t size; + int i; + +- if (len <= 0) ++ if (len == 0) + return NULL; + + for (i = 0; i < ksproc->num_mems; i++) { +--- a/drivers/remoteproc/qcom_q6v5_adsp.c ++++ b/drivers/remoteproc/qcom_q6v5_adsp.c +@@ -270,7 +270,7 @@ static int adsp_stop(struct rproc *rproc + return ret; + } + +-static void *adsp_da_to_va(struct rproc *rproc, u64 da, int len) ++static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len) + { + struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; + int offset; +--- a/drivers/remoteproc/qcom_q6v5_mss.c ++++ b/drivers/remoteproc/qcom_q6v5_mss.c +@@ -1186,7 +1186,7 @@ static int q6v5_stop(struct rproc *rproc + return 0; + } + +-static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len) ++static void *q6v5_da_to_va(struct rproc *rproc, u64 da, size_t len) + { + struct q6v5 *qproc = rproc->priv; + int offset; +--- a/drivers/remoteproc/qcom_q6v5_pas.c ++++ b/drivers/remoteproc/qcom_q6v5_pas.c +@@ -159,7 +159,7 @@ static int adsp_stop(struct rproc *rproc + return ret; + } + +-static void *adsp_da_to_va(struct rproc *rproc, u64 da, int len) ++static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len) + { + struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; + int offset; +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -406,7 +406,7 @@ static int q6v5_wcss_stop(struct rproc * + return 0; + } + +-static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, int len) ++static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, size_t len) + { + struct q6v5_wcss *wcss = rproc->priv; + int offset; +--- a/drivers/remoteproc/qcom_wcnss.c ++++ b/drivers/remoteproc/qcom_wcnss.c +@@ -287,7 +287,7 @@ static int wcnss_stop(struct rproc *rpro + return ret; + } + +-static void *wcnss_da_to_va(struct rproc *rproc, u64 da, int len) ++static void *wcnss_da_to_va(struct rproc *rproc, u64 da, size_t len) + { + struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; + int offset; +--- a/drivers/remoteproc/remoteproc_core.c ++++ b/drivers/remoteproc/remoteproc_core.c +@@ -187,7 +187,7 @@ EXPORT_SYMBOL(rproc_va_to_pa); + * here the output of the DMA API for the carveouts, which should be more + * correct. + */ +-void *rproc_da_to_va(struct rproc *rproc, u64 da, int len) ++void *rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) + { + struct rproc_mem_entry *carveout; + void *ptr = NULL; +--- a/drivers/remoteproc/remoteproc_internal.h ++++ b/drivers/remoteproc/remoteproc_internal.h +@@ -50,7 +50,7 @@ void rproc_exit_sysfs(void); + void rproc_free_vring(struct rproc_vring *rvring); + int rproc_alloc_vring(struct rproc_vdev *rvdev, int i); + +-void *rproc_da_to_va(struct rproc *rproc, u64 da, int len); ++void *rproc_da_to_va(struct rproc *rproc, u64 da, size_t len); + phys_addr_t rproc_va_to_pa(void *cpu_addr); + int rproc_trigger_recovery(struct rproc *rproc); + +--- a/drivers/remoteproc/st_slim_rproc.c ++++ b/drivers/remoteproc/st_slim_rproc.c +@@ -174,7 +174,7 @@ static int slim_rproc_stop(struct rproc + return 0; + } + +-static void *slim_rproc_da_to_va(struct rproc *rproc, u64 da, int len) ++static void *slim_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) + { + struct st_slim_rproc *slim_rproc = rproc->priv; + void *va = NULL; +@@ -191,7 +191,7 @@ static void *slim_rproc_da_to_va(struct + } + } + +- dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%x va = 0x%pK\n", ++ dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%pK\n", + da, len, va); + + return va; +--- a/drivers/remoteproc/wkup_m3_rproc.c ++++ b/drivers/remoteproc/wkup_m3_rproc.c +@@ -80,14 +80,14 @@ static int wkup_m3_rproc_stop(struct rpr + return 0; + } + +-static void *wkup_m3_rproc_da_to_va(struct rproc *rproc, u64 da, int len) ++static void *wkup_m3_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) + { + struct wkup_m3_rproc *wkupm3 = rproc->priv; + void *va = NULL; + int i; + u32 offset; + +- if (len <= 0) ++ if (len == 0) + return NULL; + + for (i = 0; i < WKUPM3_MEM_MAX; i++) { +--- a/include/linux/remoteproc.h ++++ b/include/linux/remoteproc.h +@@ -374,7 +374,7 @@ struct rproc_ops { + int (*start)(struct rproc *rproc); + int (*stop)(struct rproc *rproc); + void (*kick)(struct rproc *rproc, int vqid); +- void * (*da_to_va)(struct rproc *rproc, u64 da, int len); ++ void * (*da_to_va)(struct rproc *rproc, u64 da, size_t len); + int (*parse_fw)(struct rproc *rproc, const struct firmware *fw); + int (*handle_rsc)(struct rproc *rproc, u32 rsc_type, void *rsc, + int offset, int avail); diff --git a/target/linux/ipq807x/patches-5.4/0012-v5.8-remoteproc-wcss-add-support-for-rpmsg-communication.patch b/target/linux/ipq807x/patches-5.4/0012-v5.8-remoteproc-wcss-add-support-for-rpmsg-communication.patch new file mode 100644 index 00000000000000..e41fad6cd37b68 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0012-v5.8-remoteproc-wcss-add-support-for-rpmsg-communication.patch @@ -0,0 +1,37 @@ +From 8a226e2c71bb3763e27a063d36eac5fa4ea53c3f Mon Sep 17 00:00:00 2001 +From: Sivaprakash Murugesan +Date: Fri, 1 May 2020 21:58:12 +0530 +Subject: [PATCH] remoteproc: wcss: add support for rpmsg communication + +add glink and ssr subdevices for wcss rproc to enable rpmsg +communication. + +Signed-off-by: Sivaprakash Murugesan +Link: https://lore.kernel.org/r/1588350492-4663-1-git-send-email-sivaprak@codeaurora.org +Signed-off-by: Bjorn Andersson +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -91,6 +91,9 @@ struct q6v5_wcss { + phys_addr_t mem_reloc; + void *mem_region; + size_t mem_size; ++ ++ struct qcom_rproc_glink glink_subdev; ++ struct qcom_rproc_ssr ssr_subdev; + }; + + static int q6v5_wcss_reset(struct q6v5_wcss *wcss) +@@ -557,6 +560,9 @@ static int q6v5_wcss_probe(struct platfo + if (ret) + goto free_rproc; + ++ qcom_add_glink_subdev(rproc, &wcss->glink_subdev); ++ qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss"); ++ + ret = rproc_add(rproc); + if (ret) + goto free_rproc; diff --git a/target/linux/ipq807x/patches-5.4/0013-v5.9-remoteproc-qcom-Introduce-helper-to-store-pil-info-i.patch b/target/linux/ipq807x/patches-5.4/0013-v5.9-remoteproc-qcom-Introduce-helper-to-store-pil-info-i.patch new file mode 100644 index 00000000000000..7c63388edff3f6 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0013-v5.9-remoteproc-qcom-Introduce-helper-to-store-pil-info-i.patch @@ -0,0 +1,190 @@ +From 549b67da660d634e3a4a50a325bd1f5609ddb84b Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Mon, 22 Jun 2020 12:19:39 -0700 +Subject: [PATCH] remoteproc: qcom: Introduce helper to store pil info in IMEM + +A region in IMEM is used to communicate load addresses of remoteproc to +post mortem debug tools. Implement a helper function that can be used to +store this information in order to enable these tools to process +collected ramdumps. + +Reviewed-by: Mathieu Poirier +Reviewed-by: Vinod Koul +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20200622191942.255460-3-bjorn.andersson@linaro.org +Signed-off-by: Bjorn Andersson +--- + drivers/remoteproc/Kconfig | 3 + + drivers/remoteproc/Makefile | 1 + + drivers/remoteproc/qcom_pil_info.c | 129 +++++++++++++++++++++++++++++ + drivers/remoteproc/qcom_pil_info.h | 9 ++ + 4 files changed, 142 insertions(+) + create mode 100644 drivers/remoteproc/qcom_pil_info.c + create mode 100644 drivers/remoteproc/qcom_pil_info.h + +--- a/drivers/remoteproc/Kconfig ++++ b/drivers/remoteproc/Kconfig +@@ -85,6 +85,9 @@ config KEYSTONE_REMOTEPROC + It's safe to say N here if you're not interested in the Keystone + DSPs or just want to use a bare minimum kernel. + ++config QCOM_PIL_INFO ++ tristate ++ + config QCOM_RPROC_COMMON + tristate + +--- a/drivers/remoteproc/Makefile ++++ b/drivers/remoteproc/Makefile +@@ -14,6 +14,7 @@ obj-$(CONFIG_OMAP_REMOTEPROC) += omap_r + obj-$(CONFIG_WKUP_M3_RPROC) += wkup_m3_rproc.o + obj-$(CONFIG_DA8XX_REMOTEPROC) += da8xx_remoteproc.o + obj-$(CONFIG_KEYSTONE_REMOTEPROC) += keystone_remoteproc.o ++obj-$(CONFIG_QCOM_PIL_INFO) += qcom_pil_info.o + obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o + obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o + obj-$(CONFIG_QCOM_Q6V5_ADSP) += qcom_q6v5_adsp.o +--- /dev/null ++++ b/drivers/remoteproc/qcom_pil_info.c +@@ -0,0 +1,129 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2019-2020 Linaro Ltd. ++ */ ++#include ++#include ++#include ++#include ++#include "qcom_pil_info.h" ++ ++/* ++ * The PIL relocation information region is used to communicate memory regions ++ * occupied by co-processor firmware for post mortem crash analysis. ++ * ++ * It consists of an array of entries with an 8 byte textual identifier of the ++ * region followed by a 64 bit base address and 32 bit size, both little ++ * endian. ++ */ ++#define PIL_RELOC_NAME_LEN 8 ++#define PIL_RELOC_ENTRY_SIZE (PIL_RELOC_NAME_LEN + sizeof(__le64) + sizeof(__le32)) ++ ++struct pil_reloc { ++ void __iomem *base; ++ size_t num_entries; ++}; ++ ++static struct pil_reloc _reloc __read_mostly; ++static DEFINE_MUTEX(pil_reloc_lock); ++ ++static int qcom_pil_info_init(void) ++{ ++ struct device_node *np; ++ struct resource imem; ++ void __iomem *base; ++ int ret; ++ ++ /* Already initialized? */ ++ if (_reloc.base) ++ return 0; ++ ++ np = of_find_compatible_node(NULL, NULL, "qcom,pil-reloc-info"); ++ if (!np) ++ return -ENOENT; ++ ++ ret = of_address_to_resource(np, 0, &imem); ++ of_node_put(np); ++ if (ret < 0) ++ return ret; ++ ++ base = ioremap(imem.start, resource_size(&imem)); ++ if (!base) { ++ pr_err("failed to map PIL relocation info region\n"); ++ return -ENOMEM; ++ } ++ ++ memset_io(base, 0, resource_size(&imem)); ++ ++ _reloc.base = base; ++ _reloc.num_entries = resource_size(&imem) / PIL_RELOC_ENTRY_SIZE; ++ ++ return 0; ++} ++ ++/** ++ * qcom_pil_info_store() - store PIL information of image in IMEM ++ * @image: name of the image ++ * @base: base address of the loaded image ++ * @size: size of the loaded image ++ * ++ * Return: 0 on success, negative errno on failure ++ */ ++int qcom_pil_info_store(const char *image, phys_addr_t base, size_t size) ++{ ++ char buf[PIL_RELOC_NAME_LEN]; ++ void __iomem *entry; ++ int ret; ++ int i; ++ ++ mutex_lock(&pil_reloc_lock); ++ ret = qcom_pil_info_init(); ++ if (ret < 0) { ++ mutex_unlock(&pil_reloc_lock); ++ return ret; ++ } ++ ++ for (i = 0; i < _reloc.num_entries; i++) { ++ entry = _reloc.base + i * PIL_RELOC_ENTRY_SIZE; ++ ++ memcpy_fromio(buf, entry, PIL_RELOC_NAME_LEN); ++ ++ /* ++ * An empty record means we didn't find it, given that the ++ * records are packed. ++ */ ++ if (!buf[0]) ++ goto found_unused; ++ ++ if (!strncmp(buf, image, PIL_RELOC_NAME_LEN)) ++ goto found_existing; ++ } ++ ++ pr_warn("insufficient PIL info slots\n"); ++ mutex_unlock(&pil_reloc_lock); ++ return -ENOMEM; ++ ++found_unused: ++ memcpy_toio(entry, image, PIL_RELOC_NAME_LEN); ++found_existing: ++ /* Use two writel() as base is only aligned to 4 bytes on odd entries */ ++ writel(base, entry + PIL_RELOC_NAME_LEN); ++ writel(base >> 32, entry + PIL_RELOC_NAME_LEN + 4); ++ writel(size, entry + PIL_RELOC_NAME_LEN + sizeof(__le64)); ++ mutex_unlock(&pil_reloc_lock); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(qcom_pil_info_store); ++ ++static void __exit pil_reloc_exit(void) ++{ ++ mutex_lock(&pil_reloc_lock); ++ iounmap(_reloc.base); ++ _reloc.base = NULL; ++ mutex_unlock(&pil_reloc_lock); ++} ++module_exit(pil_reloc_exit); ++ ++MODULE_DESCRIPTION("Qualcomm PIL relocation info"); ++MODULE_LICENSE("GPL v2"); +--- /dev/null ++++ b/drivers/remoteproc/qcom_pil_info.h +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef __QCOM_PIL_INFO_H__ ++#define __QCOM_PIL_INFO_H__ ++ ++#include ++ ++int qcom_pil_info_store(const char *image, phys_addr_t base, size_t size); ++ ++#endif diff --git a/target/linux/ipq807x/patches-5.4/0014-v5.9-remoteproc-qcom-pil-info-Fix-shift-overflow.patch b/target/linux/ipq807x/patches-5.4/0014-v5.9-remoteproc-qcom-pil-info-Fix-shift-overflow.patch new file mode 100644 index 00000000000000..1f7d747e5aa987 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0014-v5.9-remoteproc-qcom-pil-info-Fix-shift-overflow.patch @@ -0,0 +1,30 @@ +From 90ec257c380ebdcebf332b698f3e809cd1157202 Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Wed, 15 Jul 2020 22:48:17 -0700 +Subject: [PATCH] remoteproc: qcom: pil-info: Fix shift overflow + +On platforms with 32-bit phys_addr_t the shift to get the upper word of +the base address of the memory region is invalid. Cast the base to 64 +bit to resolv this. + +Fixes: 549b67da660d ("remoteproc: qcom: Introduce helper to store pil info in IMEM") +Tested-by: Nathan Chancellor # build +Reported-by: Lee Jones +Reported-by: Nathan Chancellor +Link: https://lore.kernel.org/r/20200716054817.157608-1-bjorn.andersson@linaro.org +Signed-off-by: Bjorn Andersson +--- + drivers/remoteproc/qcom_pil_info.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/remoteproc/qcom_pil_info.c ++++ b/drivers/remoteproc/qcom_pil_info.c +@@ -108,7 +108,7 @@ found_unused: + found_existing: + /* Use two writel() as base is only aligned to 4 bytes on odd entries */ + writel(base, entry + PIL_RELOC_NAME_LEN); +- writel(base >> 32, entry + PIL_RELOC_NAME_LEN + 4); ++ writel((u64)base >> 32, entry + PIL_RELOC_NAME_LEN + 4); + writel(size, entry + PIL_RELOC_NAME_LEN + sizeof(__le64)); + mutex_unlock(&pil_reloc_lock); + diff --git a/target/linux/ipq807x/patches-5.4/0015-v5.9-remoteproc-qcom-Update-PIL-relocation-info-on-load.patch b/target/linux/ipq807x/patches-5.4/0015-v5.9-remoteproc-qcom-Update-PIL-relocation-info-on-load.patch new file mode 100644 index 00000000000000..2b60998d6a67b1 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0015-v5.9-remoteproc-qcom-Update-PIL-relocation-info-on-load.patch @@ -0,0 +1,102 @@ +From d4c78d2167913b3f7af0d2189fd3d76f6614a1bf Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Mon, 22 Jun 2020 12:19:40 -0700 +Subject: [PATCH] remoteproc: qcom: Update PIL relocation info on load + +Update the PIL relocation information in IMEM with information about +where the firmware for various remoteprocs are loaded. + +Reviewed-by: Vinod Koul +Reviewed-by: Stephen Boyd +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20200622191942.255460-4-bjorn.andersson@linaro.org +Signed-off-by: Bjorn Andersson +--- + drivers/remoteproc/Kconfig | 5 +++++ + drivers/remoteproc/qcom_q6v5_adsp.c | 16 +++++++++++++--- + drivers/remoteproc/qcom_q6v5_mss.c | 3 +++ + drivers/remoteproc/qcom_q6v5_pas.c | 15 ++++++++++++--- + drivers/remoteproc/qcom_q6v5_wcss.c | 14 +++++++++++--- + drivers/remoteproc/qcom_wcnss.c | 14 +++++++++++--- + 6 files changed, 55 insertions(+), 12 deletions(-) + +--- a/drivers/remoteproc/Kconfig ++++ b/drivers/remoteproc/Kconfig +@@ -153,6 +153,7 @@ config QCOM_Q6V5_WCSS + depends on QCOM_SYSMON || QCOM_SYSMON=n + select MFD_SYSCON + select QCOM_MDT_LOADER ++ select QCOM_PIL_INFO + select QCOM_Q6V5_COMMON + select QCOM_RPROC_COMMON + select QCOM_SCM +@@ -183,6 +184,7 @@ config QCOM_WCNSS_PIL + depends on QCOM_SMEM + depends on QCOM_SYSMON || QCOM_SYSMON=n + select QCOM_MDT_LOADER ++ select QCOM_PIL_INFO + select QCOM_RPROC_COMMON + select QCOM_SCM + help +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -14,6 +14,7 @@ + #include + #include + #include "qcom_common.h" ++#include "qcom_pil_info.h" + #include "qcom_q6v5.h" + + #define WCSS_CRASH_REASON 421 +@@ -424,10 +425,17 @@ static void *q6v5_wcss_da_to_va(struct r + static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) + { + struct q6v5_wcss *wcss = rproc->priv; ++ int ret; ++ ++ ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, ++ 0, wcss->mem_region, wcss->mem_phys, ++ wcss->mem_size, &wcss->mem_reloc); ++ if (ret) ++ return ret; ++ ++ qcom_pil_info_store("wcnss", wcss->mem_phys, wcss->mem_size); + +- return qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, +- 0, wcss->mem_region, wcss->mem_phys, +- wcss->mem_size, &wcss->mem_reloc); ++ return ret; + } + + static const struct rproc_ops q6v5_wcss_ops = { +--- a/drivers/remoteproc/qcom_wcnss.c ++++ b/drivers/remoteproc/qcom_wcnss.c +@@ -27,6 +27,7 @@ + + #include "qcom_common.h" + #include "remoteproc_internal.h" ++#include "qcom_pil_info.h" + #include "qcom_wcnss.h" + + #define WCNSS_CRASH_REASON_SMEM 422 +@@ -145,10 +146,17 @@ void qcom_wcnss_assign_iris(struct qcom_ + static int wcnss_load(struct rproc *rproc, const struct firmware *fw) + { + struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; ++ int ret; + +- return qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID, +- wcnss->mem_region, wcnss->mem_phys, +- wcnss->mem_size, &wcnss->mem_reloc); ++ ret = qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID, ++ wcnss->mem_region, wcnss->mem_phys, ++ wcnss->mem_size, &wcnss->mem_reloc); ++ if (ret) ++ return ret; ++ ++ qcom_pil_info_store("wcnss", wcnss->mem_phys, wcnss->mem_size); ++ ++ return 0; + } + + static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss) diff --git a/target/linux/ipq807x/patches-5.4/0016-v5.7-drivers-provide-devm_platform_get_and_ioremap_resour.patch b/target/linux/ipq807x/patches-5.4/0016-v5.7-drivers-provide-devm_platform_get_and_ioremap_resour.patch new file mode 100644 index 00000000000000..72f4f0111e37e1 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/0016-v5.7-drivers-provide-devm_platform_get_and_ioremap_resour.patch @@ -0,0 +1,76 @@ +From 890cc39a879906b63912482dfc41944579df2dc6 Mon Sep 17 00:00:00 2001 +From: Dejin Zheng +Date: Tue, 24 Mar 2020 00:06:08 +0800 +Subject: [PATCH] drivers: provide devm_platform_get_and_ioremap_resource() + +Since commit "drivers: provide devm_platform_ioremap_resource()", +it was wrap platform_get_resource() and devm_ioremap_resource() as +single helper devm_platform_ioremap_resource(). but now, many drivers +still used platform_get_resource() and devm_ioremap_resource() +together in the kernel tree. The reason can not be replaced is they +still need use the resource variables obtained by platform_get_resource(). +so provide this helper. + +Suggested-by: Geert Uytterhoeven +Suggested-by: Sergei Shtylyov +Reviewed-by: Geert Uytterhoeven +Signed-off-by: Dejin Zheng +Link: https://lore.kernel.org/r/20200323160612.17277-2-zhengdejin5@gmail.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/base/platform.c | 22 ++++++++++++++++++++++ + include/linux/platform_device.h | 3 +++ + 2 files changed, 25 insertions(+) + +--- a/drivers/base/platform.c ++++ b/drivers/base/platform.c +@@ -61,6 +61,29 @@ struct resource *platform_get_resource(s + } + EXPORT_SYMBOL_GPL(platform_get_resource); + ++#ifdef CONFIG_HAS_IOMEM ++/** ++ * devm_platform_get_and_ioremap_resource - call devm_ioremap_resource() for a ++ * platform device and get resource ++ * ++ * @pdev: platform device to use both for memory resource lookup as well as ++ * resource management ++ * @index: resource index ++ * @res: optional output parameter to store a pointer to the obtained resource. ++ */ ++void __iomem * ++devm_platform_get_and_ioremap_resource(struct platform_device *pdev, ++ unsigned int index, struct resource **res) ++{ ++ struct resource *r; ++ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, index); ++ if (res) ++ *res = r; ++ return devm_ioremap_resource(&pdev->dev, r); ++} ++EXPORT_SYMBOL_GPL(devm_platform_get_and_ioremap_resource); ++ + /** + * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform + * device +@@ -69,7 +92,6 @@ EXPORT_SYMBOL_GPL(platform_get_resource) + * resource management + * @index: resource index + */ +-#ifdef CONFIG_HAS_IOMEM + void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev, + unsigned int index) + { +--- a/include/linux/platform_device.h ++++ b/include/linux/platform_device.h +@@ -55,6 +55,9 @@ extern struct device * + platform_find_device_by_driver(struct device *start, + const struct device_driver *drv); + extern void __iomem * ++devm_platform_get_and_ioremap_resource(struct platform_device *pdev, ++ unsigned int index, struct resource **res); ++extern void __iomem * + devm_platform_ioremap_resource(struct platform_device *pdev, + unsigned int index); + extern int platform_get_irq(struct platform_device *, unsigned int); diff --git a/target/linux/ipq807x/patches-5.4/100-arm64-dts-ipq8074-add-watchdog-support.patch b/target/linux/ipq807x/patches-5.4/100-arm64-dts-ipq8074-add-watchdog-support.patch new file mode 100644 index 00000000000000..18845162352e32 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/100-arm64-dts-ipq8074-add-watchdog-support.patch @@ -0,0 +1,30 @@ +From 50b0dbf203d321257a6422ec51052dc2ed775bfc Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 20 Aug 2020 15:51:18 +0200 +Subject: [PATCH] arm64: dts: ipq8074: add watchdog support + +IPQ8074 has a secure version of KPSS watchdog that is already supported. +So lets add the node to enable it. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -323,6 +323,14 @@ + reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + }; + ++ watchdog@b017000 { ++ compatible = "qcom,kpss-wdt"; ++ interrupts = ; ++ reg = <0x0b017000 0x40>; ++ clocks = <&sleep_clk>; ++ timeout-sec = <10>; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupts = , diff --git a/target/linux/ipq807x/patches-5.4/101-arm64-dts-ipq8074-add-PRNG-node.patch b/target/linux/ipq807x/patches-5.4/101-arm64-dts-ipq8074-add-PRNG-node.patch new file mode 100644 index 00000000000000..c2e8393f939f6e --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/101-arm64-dts-ipq8074-add-PRNG-node.patch @@ -0,0 +1,29 @@ +From d623ff8bfd51896d553866f783985d32040bf584 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 20 Aug 2020 20:19:29 +0200 +Subject: [PATCH] arm64: dts: ipq8074: add PRNG node + +PRNG found in IPQ8074 is already supported so lets add the node +to enable it. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -82,6 +82,13 @@ + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + ++ prng: qrng@e1000 { ++ compatible = "qcom,prng-ee"; ++ reg = <0xe3000 0x1000>; ++ clocks = <&gcc GCC_PRNG_AHB_CLK>; ++ clock-names = "core"; ++ }; ++ + pcie_phy0: phy@86000 { + compatible = "qcom,ipq8074-qmp-pcie-phy"; + reg = <0x00086000 0x1000>; diff --git a/target/linux/ipq807x/patches-5.4/102-01-arm64-dts-ipq8074-add-SPMI-arbiter-node.patch b/target/linux/ipq807x/patches-5.4/102-01-arm64-dts-ipq8074-add-SPMI-arbiter-node.patch new file mode 100644 index 00000000000000..afb7465801b61d --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/102-01-arm64-dts-ipq8074-add-SPMI-arbiter-node.patch @@ -0,0 +1,43 @@ +From 5866b2675eb4aba6ddc1e64d5afce60a4e8ccb0f Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 21 Aug 2020 15:26:00 +0200 +Subject: [PATCH] arm64: dts: ipq8074: add SPMI arbiter node + +IPQ8074 uses the SPMI arbiter to control the PM8074 PMIC connected +to it. +So lets add the SPMI node to enable the arbiter. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -529,5 +529,26 @@ + "axi_m_sticky"; + status = "disabled"; + }; ++ ++ spmi@200f000 { ++ compatible = "qcom,spmi-pmic-arb"; ++ reg = <0x200f000 0x1000>, ++ <0x2400000 0x800000>, ++ <0x2c00000 0x800000>, ++ <0x3800000 0x200000>, ++ <0x200a000 0x000700>; ++ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; ++ interrupts = ; ++ interrupt-names = "periph_irq"; ++ ++ qcom,ee = <0>; ++ qcom,channel = <0>; ++ ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ interrupt-controller; ++ #interrupt-cells = <4>; ++ }; + }; + }; diff --git a/target/linux/ipq807x/patches-5.4/102-02-regulator-qcom_spmi-Add-support-for-PMD9655-PMIC.patch b/target/linux/ipq807x/patches-5.4/102-02-regulator-qcom_spmi-Add-support-for-PMD9655-PMIC.patch new file mode 100644 index 00000000000000..e4e2337de5ff5a --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/102-02-regulator-qcom_spmi-Add-support-for-PMD9655-PMIC.patch @@ -0,0 +1,47 @@ +From 9547df62c4fe30ceeb5b0e99c3283c810d2b89e0 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 20 Aug 2020 22:53:15 +0200 +Subject: [PATCH] regulator: qcom_spmi: Add support for PMD9655 PMIC + +Add support for PMD9655 for in SPMI regulator. +All 4 cores are supplied by a single common buck which +is the S3. +S4 buck powers the UBI cores and this support is required to provide access to NSS +voltage scaling. + +Signed-off-by: Robert Marko +--- + drivers/regulator/qcom_spmi-regulator.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -470,6 +470,7 @@ static struct spmi_voltage_range ln_ldo_ + static struct spmi_voltage_range smps_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), + SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000), ++ SPMI_VOLTAGE_RANGE(2, 670000, 670000, 990000, 990000, 8000), + }; + + static struct spmi_voltage_range ftsmps_ranges[] = { +@@ -1940,6 +1941,12 @@ static const struct spmi_regulator_data + { } + }; + ++static const struct spmi_regulator_data pmd9655_regulators[] = { ++ { "s3", 0x1a00, "vdd_s3", }, ++ { "s4", 0x1d00, "vdd_s4", }, ++ { } ++}; ++ + static const struct of_device_id qcom_spmi_regulator_match[] = { + { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators }, + { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators }, +@@ -1948,6 +1955,7 @@ static const struct of_device_id qcom_sp + { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators }, + { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators }, + { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators }, ++ { .compatible = "qcom,pmd9655-regulators", .data = &pmd9655_regulators }, + { } + }; + MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match); diff --git a/target/linux/ipq807x/patches-5.4/102-03-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch b/target/linux/ipq807x/patches-5.4/102-03-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch new file mode 100644 index 00000000000000..c1da46ae67323e --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/102-03-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch @@ -0,0 +1,154 @@ +From 2f42b1f07c78c06bd7d5b0d812f48a7b1d96968a Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Thu, 20 Aug 2020 23:06:23 +0200 +Subject: [PATCH] regulator: qcom_spmi: Add support for VMPWM_CTL subtype + +Support for Voltage Mode PWM Controller (VMPWM_CTL). +Set/Get microvolts functions added. Function to find the +voltage range for this particular subtype added. + +Signed-off-by: Robert Marko +--- + drivers/regulator/qcom_spmi-regulator.c | 82 +++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 82 insertions(+) + +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -151,6 +151,7 @@ enum spmi_regulator_subtype { + SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f, + SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, + SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, ++ SPMI_REGULATOR_SUBTYPE_VMPWM_CTL = 0x0a, + }; + + enum spmi_common_regulator_registers { +@@ -276,6 +277,10 @@ enum spmi_common_control_register_index + #define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07 + #define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0 + ++#define SPMI_SMPS_VMPWM_VSET_UB_SHIFT 8 ++#define SPMI_SMPS_VMPWM_VSET_UB_MASK 0xf00 ++#define SPMI_SMPS_VMPWM_VSET_LB_MASK 0xff ++ + /* Clock rate in kHz of the FTSMPS regulator reference clock. */ + #define SPMI_FTSMPS_CLOCK_RATE 19200 + +@@ -473,6 +478,10 @@ static struct spmi_voltage_range smps_ra + SPMI_VOLTAGE_RANGE(2, 670000, 670000, 990000, 990000, 8000), + }; + ++static struct spmi_voltage_range smps_vmpwm_ranges[] = { ++ SPMI_VOLTAGE_RANGE(0, 664000, 664000, 1104000, 1104000, 8000), ++}; ++ + static struct spmi_voltage_range ftsmps_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000), + SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000), +@@ -522,6 +531,7 @@ static DEFINE_SPMI_SET_POINTS(nldo2); + static DEFINE_SPMI_SET_POINTS(nldo3); + static DEFINE_SPMI_SET_POINTS(ln_ldo); + static DEFINE_SPMI_SET_POINTS(smps); ++static DEFINE_SPMI_SET_POINTS(smps_vmpwm); + static DEFINE_SPMI_SET_POINTS(ftsmps); + static DEFINE_SPMI_SET_POINTS(ftsmps2p5); + static DEFINE_SPMI_SET_POINTS(ftsmps426); +@@ -708,6 +718,24 @@ spmi_regulator_find_range(struct spmi_re + return NULL; + } + ++static const struct spmi_voltage_range * ++spmi_regulator_find_uV_range(struct spmi_regulator *vreg, int min, int max) ++{ ++ const struct spmi_voltage_range *range, *end; ++ ++ if (!vreg->set_points || !vreg->set_points->count) ++ return 0; ++ ++ range = vreg->set_points->range; ++ end = range + vreg->set_points->count; ++ ++ for (; range < end; range++) ++ if ((range->min_uV <= min) && (range->max_uV >= max)) ++ return range; ++ ++ return 0; ++} ++ + static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg, + int min_uV, int max_uV) + { +@@ -929,6 +957,47 @@ static int spmi_regulator_ult_lo_smps_ge + return spmi_hw_selector_to_sw(vreg, voltage_sel, range); + } + ++static int spmi_regulator_smps_vmpwm_set_vol_uV(struct regulator_dev *rdev, ++ int min_uV, int max_uV, unsigned *selector) ++{ ++ struct spmi_regulator *vreg = rdev_get_drvdata(rdev); ++ const struct spmi_voltage_range *range; ++ int req_vol; ++ u8 reg[2]; ++ ++ range = spmi_regulator_find_uV_range(vreg, min_uV, max_uV); ++ if (!range) ++ return -EINVAL; ++ ++ *selector = spmi_regulator_select_voltage(vreg, min_uV, max_uV); ++ req_vol = range->set_point_min_uV + (range->step_uV * (*selector)); ++ ++ /* Convert uV to mV as the register supports mV */ ++ req_vol = req_vol/1000; ++ ++ /* ++ * Voltage set point bits<7:0>. 2-Byte Word (lower byte word) ++ */ ++ reg[0] = req_vol & SPMI_SMPS_VMPWM_VSET_LB_MASK; ++ /* ++ * Voltage set point bit <11:8>. 2-Byte Word (upper byte word) ++ */ ++ reg[1] = (req_vol & SPMI_SMPS_VMPWM_VSET_UB_MASK) ++ >> SPMI_SMPS_VMPWM_VSET_UB_SHIFT; ++ ++ return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, reg, 2); ++} ++ ++static int spmi_regulator_smps_vmpwm_get_vol_uV(struct regulator_dev *rdev) ++{ ++ struct spmi_regulator *vreg = rdev_get_drvdata(rdev); ++ u8 reg[2]; ++ ++ spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, reg, 2); ++ ++ return ((reg[1] << SPMI_SMPS_VMPWM_VSET_UB_SHIFT) | reg[0]) * 1000; ++} ++ + static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, + unsigned selector) + { +@@ -1277,6 +1346,18 @@ static struct regulator_ops spmi_smps_op + .set_pull_down = spmi_regulator_common_set_pull_down, + }; + ++static struct regulator_ops spmi_smps_vmpwm_ops = { ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .set_voltage = spmi_regulator_smps_vmpwm_set_vol_uV, ++ .get_voltage = spmi_regulator_smps_vmpwm_get_vol_uV, ++ .map_voltage = spmi_regulator_common_map_voltage, ++ .list_voltage = spmi_regulator_common_list_voltage, ++ .set_mode = spmi_regulator_common_set_mode, ++ .get_mode = spmi_regulator_common_get_mode, ++}; ++ + static struct regulator_ops spmi_ldo_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, +@@ -1424,6 +1505,7 @@ static const struct spmi_regulator_mappi + /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ + SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), + SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), ++ SPMI_VREG(BUCK, VMPWM_CTL, 0, INF, SMPS, smps_vmpwm, smps_vmpwm, 0), + SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), + SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000), + SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000), diff --git a/target/linux/ipq807x/patches-5.4/102-04-regulator-qcom_spmi-Add-support-for-LD011-in-PMD9655.patch b/target/linux/ipq807x/patches-5.4/102-04-regulator-qcom_spmi-Add-support-for-LD011-in-PMD9655.patch new file mode 100644 index 00000000000000..08ef88c322243d --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/102-04-regulator-qcom_spmi-Add-support-for-LD011-in-PMD9655.patch @@ -0,0 +1,48 @@ +From 44de637a650e23153abf663b9d896287a9619e18 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 21 Aug 2020 16:56:49 +0200 +Subject: [PATCH] regulator: qcom_spmi: Add support for LD011 in PMD9655 + +LDO11 in PMD9655 is used for SD card support. + +Signed-off-by: Robert Marko +--- + drivers/regulator/qcom_spmi-regulator.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/regulator/qcom_spmi-regulator.c ++++ b/drivers/regulator/qcom_spmi-regulator.c +@@ -152,6 +152,7 @@ enum spmi_regulator_subtype { + SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, + SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, + SPMI_REGULATOR_SUBTYPE_VMPWM_CTL = 0x0a, ++ SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35, + }; + + enum spmi_common_regulator_registers { +@@ -479,7 +480,8 @@ static struct spmi_voltage_range smps_ra + }; + + static struct spmi_voltage_range smps_vmpwm_ranges[] = { +- SPMI_VOLTAGE_RANGE(0, 664000, 664000, 1104000, 1104000, 8000), ++ SPMI_VOLTAGE_RANGE(0, 664000, 664000, 1104000, 1104000, 8000), ++ SPMI_VOLTAGE_RANGE(1, 1104000, 1104000, 3300000, 3300000, 8000), + }; + + static struct spmi_voltage_range ftsmps_ranges[] = { +@@ -1526,6 +1528,7 @@ static const struct spmi_regulator_mappi + SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000), + SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000), + SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000), ++ SPMI_VREG(LDO, HT_P150, 0, INF, LDO, smps_vmpwm, smps_vmpwm, 0), + SPMI_VREG_VS(LV100, 0, INF), + SPMI_VREG_VS(LV300, 0, INF), + SPMI_VREG_VS(MV300, 0, INF), +@@ -2026,6 +2029,7 @@ static const struct spmi_regulator_data + static const struct spmi_regulator_data pmd9655_regulators[] = { + { "s3", 0x1a00, "vdd_s3", }, + { "s4", 0x1d00, "vdd_s4", }, ++ { "ldo11", 0x4a00, "vdd_ldo11", }, + { } + }; + diff --git a/target/linux/ipq807x/patches-5.4/102-05-arm64-dts-ipq8074-Add-PMD9655-SPMI-PMIC-nodes.patch b/target/linux/ipq807x/patches-5.4/102-05-arm64-dts-ipq8074-Add-PMD9655-SPMI-PMIC-nodes.patch new file mode 100644 index 00000000000000..ad63cccafb5406 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/102-05-arm64-dts-ipq8074-Add-PMD9655-SPMI-PMIC-nodes.patch @@ -0,0 +1,84 @@ +From 99007c6f1c4d4d97db51d59808f69505a8bad4fa Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 21 Aug 2020 17:19:00 +0200 +Subject: [PATCH] arm64: dts: ipq8074: Add PMD9655 SPMI PMIC nodes + +IPQ8074 uses these for CPU scaling, UBI/NSS scaling and +SD card. + +So lets add the nodes. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 46 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -5,6 +5,7 @@ + + #include + #include ++#include + + / { + model = "Qualcomm Technologies, Inc. IPQ8074"; +@@ -76,6 +77,15 @@ + method = "smc"; + }; + ++ e_smps1_reg: fixed-regulator@0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "e-smps1-reg"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ + soc: soc { + #address-cells = <0x1>; + #size-cells = <0x1>; +@@ -549,6 +559,42 @@ + + interrupt-controller; + #interrupt-cells = <4>; ++ ++ pmic@1 { ++ compatible = "qcom,spmi-pmic"; ++ reg = <0x1 SPMI_USID>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ regulators { ++ compatible = "qcom,pmd9655-regulators"; ++ vdd_s3-supply = <&e_smps1_reg>; ++ vdd_s4-supply = <&e_smps1_reg>; ++ vdd_ldo11-supply = <&e_smps1_reg>; ++ ++ s3: s3 { ++ regulator-name = "pmd9655_s3"; ++ regulator-min-microvolt = <592000>; ++ regulator-max-microvolt = <1064000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ s4: s4 { ++ regulator-name = "pmd9655_s4"; ++ regulator-min-microvolt = <712000>; ++ regulator-max-microvolt = <992000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ ldo11: ldo11 { ++ regulator-name = "pmd9655_ldo11"; ++ regulator-min-microvolt = <1104000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ }; ++ }; + }; + }; + }; diff --git a/target/linux/ipq807x/patches-5.4/103-01-clk-qcom-Add-IPQ8074-APSS-driver.patch b/target/linux/ipq807x/patches-5.4/103-01-clk-qcom-Add-IPQ8074-APSS-driver.patch new file mode 100644 index 00000000000000..f0ed363f2782df --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/103-01-clk-qcom-Add-IPQ8074-APSS-driver.patch @@ -0,0 +1,154 @@ +From 0da5c2a83cd8a920889297e83639b92de4eb497c Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 22 Aug 2020 15:40:05 +0200 +Subject: [PATCH] clk: qcom: Add IPQ8074 APSS driver + +APSS clks are needed for CPU scaling. + +Signed-off-by: Robert Marko +--- + drivers/clk/qcom/Kconfig | 10 +++ + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/apss-ipq8074.c | 107 ++++++++++++++++++++++++++++++++ + 3 files changed, 118 insertions(+) + create mode 100644 drivers/clk/qcom/apss-ipq8074.c + +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -88,6 +88,16 @@ config APQ_MMCC_8084 + Say Y if you want to support multimedia devices such as display, + graphics, video encode/decode, camera, etc. + ++config IPQ_APSS_8074 ++ tristate "IPQ8074 APSS Clock Controller" ++ depends on QCOM_APCS_IPC || COMPILE_TEST ++ help ++ Support for APSS clock controller on IPQ8074 platforms. The ++ APSS clock controller manages the Mux and enable block that feeds the ++ CPUs. ++ Say Y if you want to support CPU frequency scaling on ++ IPQ8074 based devices. ++ + config IPQ_GCC_4019 + tristate "IPQ4019 Global Clock Controller" + help +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -19,6 +19,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o + # Keep alphabetically sorted by config + obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o + obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o ++obj-$(CONFIG_IPQ_APSS_8074) += apss-ipq8074.o + obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o + obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o + obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o +--- /dev/null ++++ b/drivers/clk/qcom/apss-ipq8074.c +@@ -0,0 +1,107 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2018, The Linux Foundation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "common.h" ++#include "clk-regmap.h" ++#include "clk-branch.h" ++#include "clk-alpha-pll.h" ++#include "clk-regmap-mux.h" ++ ++enum { ++ P_XO, ++ P_APSS_PLL_EARLY, ++}; ++ ++static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { ++ { .fw_name = "xo" }, ++ { .fw_name = "pll" }, ++}; ++ ++static const struct parent_map parents_apcs_alias0_clk_src_map[] = { ++ { P_XO, 0 }, ++ { P_APSS_PLL_EARLY, 5 }, ++}; ++ ++static struct clk_regmap_mux apcs_alias0_clk_src = { ++ .reg = 0x0050, ++ .width = 3, ++ .shift = 7, ++ .parent_map = parents_apcs_alias0_clk_src_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "apcs_alias0_clk_src", ++ .parent_data = parents_apcs_alias0_clk_src, ++ .num_parents = 2, ++ .ops = &clk_regmap_mux_closest_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static struct clk_branch apcs_alias0_core_clk = { ++ .halt_reg = 0x0058, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x0058, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "apcs_alias0_core_clk", ++ .parent_hws = (const struct clk_hw *[]){ ++ &apcs_alias0_clk_src.clkr.hw }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct regmap_config apss_ipq8074_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x1000, ++ .fast_io = true, ++}; ++ ++static struct clk_regmap *apss_ipq8074_clks[] = { ++ [APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr, ++ [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr, ++}; ++ ++static const struct qcom_cc_desc apss_ipq8074_desc = { ++ .config = &apss_ipq8074_regmap_config, ++ .clks = apss_ipq8074_clks, ++ .num_clks = ARRAY_SIZE(apss_ipq8074_clks), ++}; ++ ++static int apss_ipq8074_probe(struct platform_device *pdev) ++{ ++ struct regmap *regmap; ++ ++ regmap = dev_get_regmap(pdev->dev.parent, NULL); ++ if (!regmap) ++ return -ENODEV; ++ ++ return qcom_cc_really_probe(pdev, &apss_ipq8074_desc, regmap); ++} ++ ++static struct platform_driver apss_ipq8074_driver = { ++ .probe = apss_ipq8074_probe, ++ .driver = { ++ .name = "qcom,apss-ipq8074-clk", ++ }, ++}; ++ ++module_platform_driver(apss_ipq8074_driver); ++ ++MODULE_DESCRIPTION("QCOM APSS IPQ 8074 CLK Driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq807x/patches-5.4/104-arm64-dts-ipq8074-Add-SMEM-nodes.patch b/target/linux/ipq807x/patches-5.4/104-arm64-dts-ipq8074-Add-SMEM-nodes.patch new file mode 100644 index 00000000000000..edd0fd01ff5ed8 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/104-arm64-dts-ipq8074-Add-SMEM-nodes.patch @@ -0,0 +1,65 @@ +From c335321e14848fb02b05fa6b8896f3ff1cd22051 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 22 Aug 2020 16:26:34 +0200 +Subject: [PATCH 1/2] arm64: dts: ipq8074: Add SMEM nodes + +SMEM is later needed for all kinds of HW support, its supported +by existing drivers. +So lets add the required nodes. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -67,6 +67,12 @@ + }; + }; + ++ tcsr_mutex: hwlock { ++ compatible = "qcom,tcsr-mutex"; ++ syscon = <&tcsr_mutex_regs 0 0x80>; ++ #hwlock-cells = <1>; ++ }; ++ + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; +@@ -86,6 +92,23 @@ + regulator-boot-on; + }; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ smem_region: smem@4ab00000 { ++ reg = <0x0 0x4ab00000 0x0 0x100000>; ++ no-map; ++ }; ++ }; ++ ++ smem { ++ compatible = "qcom,smem"; ++ memory-region = <&smem_region>; ++ hwlocks = <&tcsr_mutex 0>; ++ }; ++ + soc: soc { + #address-cells = <0x1>; + #size-cells = <0x1>; +@@ -186,6 +209,11 @@ + #reset-cells = <0x1>; + }; + ++ tcsr_mutex_regs: syscon@1905000 { ++ compatible = "syscon"; ++ reg = <0x1905000 0x8000>; ++ }; ++ + sdhc_1: sdhci@7824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x7824900 0x500>, <0x7824000 0x800>; diff --git a/target/linux/ipq807x/patches-5.4/105-arm64-dts-ipq8074-Add-SCM-node.patch b/target/linux/ipq807x/patches-5.4/105-arm64-dts-ipq8074-Add-SCM-node.patch new file mode 100644 index 00000000000000..702255cf090a08 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/105-arm64-dts-ipq8074-Add-SCM-node.patch @@ -0,0 +1,29 @@ +From 2d9b6b37afc0da0982715c65a50f74983967154e Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sat, 22 Aug 2020 16:29:25 +0200 +Subject: [PATCH 2/2] arm64: dts: ipq8074: Add SCM node + +SCM is used to communicate to all kinds of FW running on the board, +its supported by existing drivers. +So lets add the node to enable it. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -67,6 +67,12 @@ + }; + }; + ++ firmware { ++ scm { ++ compatible = "qcom,scm"; ++ }; ++ }; ++ + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x80>; diff --git a/target/linux/ipq807x/patches-5.4/106-01-remoteproc-qcom-wcss-populate-hardcoded-param-using-driver-data.patch b/target/linux/ipq807x/patches-5.4/106-01-remoteproc-qcom-wcss-populate-hardcoded-param-using-driver-data.patch new file mode 100644 index 00000000000000..4e028f450890da --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/106-01-remoteproc-qcom-wcss-populate-hardcoded-param-using-driver-data.patch @@ -0,0 +1,152 @@ +From patchwork Thu Jul 30 12:14:01 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Gokul Sriram Palanisamy +X-Patchwork-Id: 11692903 +Return-Path: +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D0FF717CA + for ; + Thu, 30 Jul 2020 12:14:32 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id C220E20838 + for ; + Thu, 30 Jul 2020 12:14:32 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1726781AbgG3MOc (ORCPT + ); + Thu, 30 Jul 2020 08:14:32 -0400 +Received: from alexa-out.qualcomm.com ([129.46.98.28]:15938 "EHLO + alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1726967AbgG3MOb (ORCPT + ); + Thu, 30 Jul 2020 08:14:31 -0400 +Received: from ironmsg07-lv.qualcomm.com (HELO ironmsg07-lv.qulacomm.com) + ([10.47.202.151]) + by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:14:31 -0700 +Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) + by ironmsg07-lv.qulacomm.com with ESMTP/TLS/AES256-SHA; + 30 Jul 2020 05:14:29 -0700 +Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) + by ironmsg01-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:44:06 +0530 +Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) + id 20D2D213B6; Thu, 30 Jul 2020 17:44:04 +0530 (IST) +From: Gokul Sriram Palanisamy +To: bjorn.andersson@linaro.org, linux-remoteproc@vger.kernel.org, + sboyd@kernel.org, linux-clk@vger.kernel.org, + linux-arm-msm@vger.kernel.org +Cc: agross@kernel.org, linux-soc@vger.kernel.org, + devicetree@vger.kernel.org, govinds@codeaurora.org, + sricharan@codeaurora.org, gokulsri@codeaurora.org +Subject: [PATCH v8 1/4] remoteproc: qcom: wcss: populate hardcoded param using + driver data +Date: Thu, 30 Jul 2020 17:44:01 +0530 +Message-Id: <1596111244-28411-2-git-send-email-gokulsri@codeaurora.org> +X-Mailer: git-send-email 2.7.4 +In-Reply-To: <1596111244-28411-1-git-send-email-gokulsri@codeaurora.org> +References: <1596111244-28411-1-git-send-email-gokulsri@codeaurora.org> +Sender: linux-arm-msm-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-arm-msm@vger.kernel.org + +From: Govind Singh + +Q6 based WiFi fw loading is supported across +different targets, ex: IPQ8074/QCS404. In order to +support different fw names/pas id etc, populate +hardcoded param using driver data. + +Signed-off-by: Govind Singh +Signed-off-by: Gokul Sriram Palanisamy +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 29 ++++++++++++++++++++++++----- + 1 file changed, 24 insertions(+), 5 deletions(-) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -71,6 +71,11 @@ + #define TCSR_WCSS_CLK_MASK 0x1F + #define TCSR_WCSS_CLK_ENABLE 0x14 + ++struct wcss_data { ++ const char *firmware_name; ++ unsigned int crash_reason_smem; ++}; ++ + struct q6v5_wcss { + struct device *dev; + +@@ -93,6 +98,8 @@ struct q6v5_wcss { + void *mem_region; + size_t mem_size; + ++ unsigned int crash_reason_smem; ++ + struct qcom_rproc_glink glink_subdev; + struct qcom_rproc_ssr ssr_subdev; + }; +@@ -438,7 +445,7 @@ static int q6v5_wcss_load(struct rproc * + return ret; + } + +-static const struct rproc_ops q6v5_wcss_ops = { ++static const struct rproc_ops q6v5_wcss_ipq8074_ops = { + .start = q6v5_wcss_start, + .stop = q6v5_wcss_stop, + .da_to_va = q6v5_wcss_da_to_va, +@@ -538,12 +545,17 @@ static int q6v5_alloc_memory_region(stru + + static int q6v5_wcss_probe(struct platform_device *pdev) + { ++ const struct wcss_data *desc; + struct q6v5_wcss *wcss; + struct rproc *rproc; + int ret; + +- rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ops, +- "IPQ8074/q6_fw.mdt", sizeof(*wcss)); ++ desc = device_get_match_data(&pdev->dev); ++ if (!desc) ++ return -EINVAL; ++ ++ rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops, ++ desc->firmware_name, sizeof(*wcss)); + if (!rproc) { + dev_err(&pdev->dev, "failed to allocate rproc\n"); + return -ENOMEM; +@@ -551,6 +563,7 @@ static int q6v5_wcss_probe(struct platfo + + wcss = rproc->priv; + wcss->dev = &pdev->dev; ++ wcss->crash_reason_smem = desc->crash_reason_smem; + + ret = q6v5_wcss_init_mmio(wcss, pdev); + if (ret) +@@ -564,7 +577,8 @@ static int q6v5_wcss_probe(struct platfo + if (ret) + goto free_rproc; + +- ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, WCSS_CRASH_REASON, NULL); ++ ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, ++ NULL); + if (ret) + goto free_rproc; + +@@ -595,8 +609,13 @@ static int q6v5_wcss_remove(struct platf + return 0; + } + ++static const struct wcss_data wcss_ipq8074_res_init = { ++ .firmware_name = "IPQ8074/q6_fw.mdt", ++ .crash_reason_smem = WCSS_CRASH_REASON, ++}; ++ + static const struct of_device_id q6v5_wcss_of_match[] = { +- { .compatible = "qcom,ipq8074-wcss-pil" }, ++ { .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init }, + { }, + }; + MODULE_DEVICE_TABLE(of, q6v5_wcss_of_match); diff --git a/target/linux/ipq807x/patches-5.4/106-02-remoteproc-qcom-wcss-Add-non-pas-wcss-Q6-support-for-QCS404.patch b/target/linux/ipq807x/patches-5.4/106-02-remoteproc-qcom-wcss-Add-non-pas-wcss-Q6-support-for-QCS404.patch new file mode 100644 index 00000000000000..12fee40703f3ac --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/106-02-remoteproc-qcom-wcss-Add-non-pas-wcss-Q6-support-for-QCS404.patch @@ -0,0 +1,809 @@ +From patchwork Thu Jul 30 12:14:03 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Gokul Sriram Palanisamy +X-Patchwork-Id: 11692923 +Return-Path: +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F13D81746 + for ; + Thu, 30 Jul 2020 12:14:40 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id DA5CA22BEA + for ; + Thu, 30 Jul 2020 12:14:40 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1726967AbgG3MOk (ORCPT + ); + Thu, 30 Jul 2020 08:14:40 -0400 +Received: from alexa-out.qualcomm.com ([129.46.98.28]:22096 "EHLO + alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1727837AbgG3MOj (ORCPT + ); + Thu, 30 Jul 2020 08:14:39 -0400 +Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) + by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:14:34 -0700 +Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) + by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; + 30 Jul 2020 05:14:31 -0700 +Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) + by ironmsg01-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:44:06 +0530 +Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) + id 5CF85218A5; Thu, 30 Jul 2020 17:44:04 +0530 (IST) +From: Gokul Sriram Palanisamy +To: bjorn.andersson@linaro.org, linux-remoteproc@vger.kernel.org, + sboyd@kernel.org, linux-clk@vger.kernel.org, + linux-arm-msm@vger.kernel.org +Cc: agross@kernel.org, linux-soc@vger.kernel.org, + devicetree@vger.kernel.org, govinds@codeaurora.org, + sricharan@codeaurora.org, gokulsri@codeaurora.org +Subject: [PATCH v8 3/4] remoteproc: qcom: wcss: Add non pas wcss Q6 support + for QCS404 +Date: Thu, 30 Jul 2020 17:44:03 +0530 +Message-Id: <1596111244-28411-4-git-send-email-gokulsri@codeaurora.org> +X-Mailer: git-send-email 2.7.4 +In-Reply-To: <1596111244-28411-1-git-send-email-gokulsri@codeaurora.org> +References: <1596111244-28411-1-git-send-email-gokulsri@codeaurora.org> +Sender: linux-arm-msm-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-arm-msm@vger.kernel.org + +From: Govind Singh + +Add non PAS WCSS remoteproc driver support for QCS404 SOC. +Add WCSS q6 bootup and shutdown sequence handled from +Application Processor SubSystem(APSS). + +Signed-off-by: Govind Singh +Signed-off-by: Gokul Sriram Palanisamy +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 564 +++++++++++++++++++++++++++++++++--- + 1 file changed, 526 insertions(+), 38 deletions(-) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -4,13 +4,18 @@ + * Copyright (C) 2014 Sony Mobile Communications AB + * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. + */ ++#include ++#include ++#include + #include + #include + #include + #include ++#include + #include + #include + #include ++#include + #include + #include + #include "qcom_common.h" +@@ -24,6 +29,9 @@ + #define Q6SS_GFMUX_CTL_REG 0x020 + #define Q6SS_PWR_CTL_REG 0x030 + #define Q6SS_MEM_PWR_CTL 0x0B0 ++#define Q6SS_STRAP_ACC 0x110 ++#define Q6SS_CGC_OVERRIDE 0x034 ++#define Q6SS_BCR_REG 0x6000 + + /* AXI Halt Register Offsets */ + #define AXI_HALTREQ_REG 0x0 +@@ -37,14 +45,19 @@ + #define Q6SS_CORE_ARES BIT(1) + #define Q6SS_BUS_ARES_ENABLE BIT(2) + ++/* Q6SS_BRC_RESET */ ++#define Q6SS_BRC_BLK_ARES BIT(0) ++ + /* Q6SS_GFMUX_CTL */ + #define Q6SS_CLK_ENABLE BIT(1) ++#define Q6SS_SWITCH_CLK_SRC BIT(8) + + /* Q6SS_PWR_CTL */ + #define Q6SS_L2DATA_STBY_N BIT(18) + #define Q6SS_SLP_RET_N BIT(19) + #define Q6SS_CLAMP_IO BIT(20) + #define QDSS_BHS_ON BIT(21) ++#define QDSS_Q6_MEMORIES GENMASK(15, 0) + + /* Q6SS parameters */ + #define Q6SS_LDO_BYP BIT(25) +@@ -53,6 +66,7 @@ + #define Q6SS_CLAMP_QMC_MEM BIT(22) + #define HALT_CHECK_MAX_LOOPS 200 + #define Q6SS_XO_CBCR GENMASK(5, 3) ++#define Q6SS_SLEEP_CBCR GENMASK(5, 2) + + /* Q6SS config/status registers */ + #define TCSR_GLOBAL_CFG0 0x0 +@@ -71,9 +85,23 @@ + #define TCSR_WCSS_CLK_MASK 0x1F + #define TCSR_WCSS_CLK_ENABLE 0x14 + ++#define MAX_HALT_REG 3 ++enum { ++ WCSS_IPQ8074, ++ WCSS_QCS404, ++}; ++ + struct wcss_data { + const char *firmware_name; + unsigned int crash_reason_smem; ++ u32 version; ++ bool aon_reset_required; ++ bool wcss_q6_reset_required; ++ const char *ssr_name; ++ const char *sysmon_name; ++ int ssctl_id; ++ const struct rproc_ops *ops; ++ bool requires_force_stop; + }; + + struct q6v5_wcss { +@@ -87,9 +115,26 @@ struct q6v5_wcss { + u32 halt_wcss; + u32 halt_nc; + ++ struct clk *xo; ++ struct clk *ahbfabric_cbcr_clk; ++ struct clk *gcc_abhs_cbcr; ++ struct clk *gcc_axim_cbcr; ++ struct clk *lcc_csr_cbcr; ++ struct clk *ahbs_cbcr; ++ struct clk *tcm_slave_cbcr; ++ struct clk *qdsp6ss_abhm_cbcr; ++ struct clk *qdsp6ss_sleep_cbcr; ++ struct clk *qdsp6ss_axim_cbcr; ++ struct clk *qdsp6ss_xo_cbcr; ++ struct clk *qdsp6ss_core_gfmux; ++ struct clk *lcc_bcr_sleep; ++ struct regulator *cx_supply; ++ struct qcom_sysmon *sysmon; ++ + struct reset_control *wcss_aon_reset; + struct reset_control *wcss_reset; + struct reset_control *wcss_q6_reset; ++ struct reset_control *wcss_q6_bcr_reset; + + struct qcom_q6v5 q6v5; + +@@ -99,6 +144,8 @@ struct q6v5_wcss { + size_t mem_size; + + unsigned int crash_reason_smem; ++ u32 version; ++ bool requires_force_stop; + + struct qcom_rproc_glink glink_subdev; + struct qcom_rproc_ssr ssr_subdev; +@@ -244,6 +291,207 @@ wcss_reset: + return ret; + } + ++static int q6v5_wcss_qcs404_power_on(struct q6v5_wcss *wcss) ++{ ++ unsigned long val; ++ int ret, idx; ++ ++ /* Toggle the restart */ ++ reset_control_assert(wcss->wcss_reset); ++ usleep_range(200, 300); ++ reset_control_deassert(wcss->wcss_reset); ++ usleep_range(200, 300); ++ ++ /* Enable GCC_WDSP_Q6SS_AHBS_CBCR clock */ ++ ret = clk_prepare_enable(wcss->gcc_abhs_cbcr); ++ if (ret) ++ return ret; ++ ++ /* Remove reset to the WCNSS QDSP6SS */ ++ reset_control_deassert(wcss->wcss_q6_bcr_reset); ++ ++ /* Enable Q6SSTOP_AHBFABRIC_CBCR clock */ ++ ret = clk_prepare_enable(wcss->ahbfabric_cbcr_clk); ++ if (ret) ++ goto disable_gcc_abhs_cbcr_clk; ++ ++ /* Enable the LCCCSR CBC clock, Q6SSTOP_Q6SSTOP_LCC_CSR_CBCR clock */ ++ ret = clk_prepare_enable(wcss->lcc_csr_cbcr); ++ if (ret) ++ goto disable_ahbfabric_cbcr_clk; ++ ++ /* Enable the Q6AHBS CBC, Q6SSTOP_Q6SS_AHBS_CBCR clock */ ++ ret = clk_prepare_enable(wcss->ahbs_cbcr); ++ if (ret) ++ goto disable_csr_cbcr_clk; ++ ++ /* Enable the TCM slave CBC, Q6SSTOP_Q6SS_TCM_SLAVE_CBCR clock */ ++ ret = clk_prepare_enable(wcss->tcm_slave_cbcr); ++ if (ret) ++ goto disable_ahbs_cbcr_clk; ++ ++ /* Enable the Q6SS AHB master CBC, Q6SSTOP_Q6SS_AHBM_CBCR clock */ ++ ret = clk_prepare_enable(wcss->qdsp6ss_abhm_cbcr); ++ if (ret) ++ goto disable_tcm_slave_cbcr_clk; ++ ++ /* Enable the Q6SS AXI master CBC, Q6SSTOP_Q6SS_AXIM_CBCR clock */ ++ ret = clk_prepare_enable(wcss->qdsp6ss_axim_cbcr); ++ if (ret) ++ goto disable_abhm_cbcr_clk; ++ ++ /* Enable the Q6SS XO CBC */ ++ val = readl(wcss->reg_base + Q6SS_XO_CBCR); ++ val |= BIT(0); ++ writel(val, wcss->reg_base + Q6SS_XO_CBCR); ++ /* Read CLKOFF bit to go low indicating CLK is enabled */ ++ ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, ++ val, !(val & BIT(31)), 1, ++ HALT_CHECK_MAX_LOOPS); ++ if (ret) { ++ dev_err(wcss->dev, ++ "xo cbcr enabling timed out (rc:%d)\n", ret); ++ return ret; ++ } ++ ++ writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE); ++ ++ /* Enable QDSP6 sleep clock clock */ ++ val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); ++ val |= BIT(0); ++ writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); ++ ++ /* Enable the Enable the Q6 AXI clock, GCC_WDSP_Q6SS_AXIM_CBCR*/ ++ ret = clk_prepare_enable(wcss->gcc_axim_cbcr); ++ if (ret) ++ goto disable_sleep_cbcr_clk; ++ ++ /* Assert resets, stop core */ ++ val = readl(wcss->reg_base + Q6SS_RESET_REG); ++ val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; ++ writel(val, wcss->reg_base + Q6SS_RESET_REG); ++ ++ /* Program the QDSP6SS PWR_CTL register */ ++ writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG); ++ ++ writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG); ++ ++ writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG); ++ ++ writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); ++ ++ /* ++ * Enable memories by turning on the QDSP6 memory foot/head switch, one ++ * bank at a time to avoid in-rush current ++ */ ++ for (idx = 28; idx >= 0; idx--) { ++ writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) | ++ (1 << idx)), wcss->reg_base + Q6SS_MEM_PWR_CTL); ++ } ++ ++ writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); ++ writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); ++ ++ val = readl(wcss->reg_base + Q6SS_RESET_REG); ++ val &= ~Q6SS_CORE_ARES; ++ writel(val, wcss->reg_base + Q6SS_RESET_REG); ++ ++ /* Enable the Q6 core clock at the GFM, Q6SSTOP_QDSP6SS_GFMUX_CTL */ ++ val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); ++ val |= Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC; ++ writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); ++ ++ /* Enable sleep clock branch needed for BCR circuit */ ++ ret = clk_prepare_enable(wcss->lcc_bcr_sleep); ++ if (ret) ++ goto disable_core_gfmux_clk; ++ ++ return 0; ++ ++disable_core_gfmux_clk: ++ val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); ++ val &= ~(Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC); ++ writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); ++ clk_disable_unprepare(wcss->gcc_axim_cbcr); ++disable_sleep_cbcr_clk: ++ val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); ++ val &= ~Q6SS_CLK_ENABLE; ++ writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); ++ val = readl(wcss->reg_base + Q6SS_XO_CBCR); ++ val &= ~Q6SS_CLK_ENABLE; ++ writel(val, wcss->reg_base + Q6SS_XO_CBCR); ++ clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); ++disable_abhm_cbcr_clk: ++ clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); ++disable_tcm_slave_cbcr_clk: ++ clk_disable_unprepare(wcss->tcm_slave_cbcr); ++disable_ahbs_cbcr_clk: ++ clk_disable_unprepare(wcss->ahbs_cbcr); ++disable_csr_cbcr_clk: ++ clk_disable_unprepare(wcss->lcc_csr_cbcr); ++disable_ahbfabric_cbcr_clk: ++ clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); ++disable_gcc_abhs_cbcr_clk: ++ clk_disable_unprepare(wcss->gcc_abhs_cbcr); ++ ++ return ret; ++} ++ ++static inline int q6v5_wcss_qcs404_reset(struct q6v5_wcss *wcss) ++{ ++ unsigned long val; ++ ++ writel(0x80800000, wcss->reg_base + Q6SS_STRAP_ACC); ++ ++ /* Start core execution */ ++ val = readl(wcss->reg_base + Q6SS_RESET_REG); ++ val &= ~Q6SS_STOP_CORE; ++ writel(val, wcss->reg_base + Q6SS_RESET_REG); ++ ++ return 0; ++} ++ ++static int q6v5_qcs404_wcss_start(struct rproc *rproc) ++{ ++ struct q6v5_wcss *wcss = rproc->priv; ++ int ret; ++ ++ ret = clk_prepare_enable(wcss->xo); ++ if (ret) ++ return ret; ++ ++ ret = regulator_enable(wcss->cx_supply); ++ if (ret) ++ goto disable_xo_clk; ++ ++ qcom_q6v5_prepare(&wcss->q6v5); ++ ++ ret = q6v5_wcss_qcs404_power_on(wcss); ++ if (ret) { ++ dev_err(wcss->dev, "wcss clk_enable failed\n"); ++ goto disable_cx_supply; ++ } ++ ++ writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); ++ ++ q6v5_wcss_qcs404_reset(wcss); ++ ++ ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); ++ if (ret == -ETIMEDOUT) { ++ dev_err(wcss->dev, "start timed out\n"); ++ goto disable_cx_supply; ++ } ++ ++ return 0; ++ ++disable_cx_supply: ++ regulator_disable(wcss->cx_supply); ++disable_xo_clk: ++ clk_disable_unprepare(wcss->xo); ++ ++ return ret; ++} ++ + static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss, + struct regmap *halt_map, + u32 offset) +@@ -278,6 +526,70 @@ static void q6v5_wcss_halt_axi_port(stru + regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0); + } + ++static int q6v5_qcs404_wcss_shutdown(struct q6v5_wcss *wcss) ++{ ++ unsigned long val; ++ int ret; ++ ++ q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss); ++ ++ /* assert clamps to avoid MX current inrush */ ++ val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); ++ val |= (Q6SS_CLAMP_IO | Q6SS_CLAMP_WL | Q6SS_CLAMP_QMC_MEM); ++ writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); ++ ++ /* Disable memories by turning off memory foot/headswitch */ ++ writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) & ++ ~QDSS_Q6_MEMORIES), ++ wcss->reg_base + Q6SS_MEM_PWR_CTL); ++ ++ /* Clear the BHS_ON bit */ ++ val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); ++ val &= ~Q6SS_BHS_ON; ++ writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); ++ ++ clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); ++ clk_disable_unprepare(wcss->lcc_csr_cbcr); ++ clk_disable_unprepare(wcss->tcm_slave_cbcr); ++ clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); ++ clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); ++ ++ val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); ++ val &= ~BIT(0); ++ writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); ++ ++ val = readl(wcss->reg_base + Q6SS_XO_CBCR); ++ val &= ~BIT(0); ++ writel(val, wcss->reg_base + Q6SS_XO_CBCR); ++ ++ clk_disable_unprepare(wcss->ahbs_cbcr); ++ clk_disable_unprepare(wcss->lcc_bcr_sleep); ++ ++ val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); ++ val &= ~(Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC); ++ writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); ++ ++ clk_disable_unprepare(wcss->gcc_abhs_cbcr); ++ ++ ret = reset_control_assert(wcss->wcss_reset); ++ if (ret) { ++ dev_err(wcss->dev, "wcss_reset failed\n"); ++ return ret; ++ } ++ usleep_range(200, 300); ++ ++ ret = reset_control_deassert(wcss->wcss_reset); ++ if (ret) { ++ dev_err(wcss->dev, "wcss_reset failed\n"); ++ return ret; ++ } ++ usleep_range(200, 300); ++ ++ clk_disable_unprepare(wcss->gcc_axim_cbcr); ++ ++ return 0; ++} ++ + static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss) + { + int ret; +@@ -397,20 +709,28 @@ static int q6v5_wcss_stop(struct rproc * + int ret; + + /* WCSS powerdown */ +- ret = qcom_q6v5_request_stop(&wcss->q6v5); +- if (ret == -ETIMEDOUT) { +- dev_err(wcss->dev, "timed out on wait\n"); +- return ret; ++ if (wcss->requires_force_stop) { ++ ret = qcom_q6v5_request_stop(&wcss->q6v5); ++ if (ret == -ETIMEDOUT) { ++ dev_err(wcss->dev, "timed out on wait\n"); ++ return ret; ++ } + } + +- ret = q6v5_wcss_powerdown(wcss); +- if (ret) +- return ret; +- +- /* Q6 Power down */ +- ret = q6v5_q6_powerdown(wcss); +- if (ret) +- return ret; ++ if (wcss->version == WCSS_QCS404) { ++ ret = q6v5_qcs404_wcss_shutdown(wcss); ++ if (ret) ++ return ret; ++ } else { ++ ret = q6v5_wcss_powerdown(wcss); ++ if (ret) ++ return ret; ++ ++ /* Q6 Power down */ ++ ret = q6v5_q6_powerdown(wcss); ++ if (ret) ++ return ret; ++ } + + qcom_q6v5_unprepare(&wcss->q6v5); + +@@ -453,14 +773,26 @@ static const struct rproc_ops q6v5_wcss_ + .get_boot_addr = rproc_elf_get_boot_addr, + }; + +-static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss) ++static const struct rproc_ops q6v5_wcss_qcs404_ops = { ++ .start = q6v5_qcs404_wcss_start, ++ .stop = q6v5_wcss_stop, ++ .da_to_va = q6v5_wcss_da_to_va, ++ .load = q6v5_wcss_load, ++ .get_boot_addr = rproc_elf_get_boot_addr, ++ .parse_fw = qcom_register_dump_segments, ++}; ++ ++static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss, ++ const struct wcss_data *desc) + { + struct device *dev = wcss->dev; + +- wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset"); +- if (IS_ERR(wcss->wcss_aon_reset)) { +- dev_err(wcss->dev, "unable to acquire wcss_aon_reset\n"); +- return PTR_ERR(wcss->wcss_aon_reset); ++ if (desc->aon_reset_required) { ++ wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset"); ++ if (IS_ERR(wcss->wcss_aon_reset)) { ++ dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n"); ++ return PTR_ERR(wcss->wcss_aon_reset); ++ } + } + + wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset"); +@@ -469,10 +801,18 @@ static int q6v5_wcss_init_reset(struct q + return PTR_ERR(wcss->wcss_reset); + } + +- wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset"); +- if (IS_ERR(wcss->wcss_q6_reset)) { +- dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n"); +- return PTR_ERR(wcss->wcss_q6_reset); ++ if (desc->wcss_q6_reset_required) { ++ wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset"); ++ if (IS_ERR(wcss->wcss_q6_reset)) { ++ dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n"); ++ return PTR_ERR(wcss->wcss_q6_reset); ++ } ++ } ++ ++ wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset"); ++ if (IS_ERR(wcss->wcss_q6_bcr_reset)) { ++ dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); ++ return PTR_ERR(wcss->wcss_q6_bcr_reset); + } + + return 0; +@@ -481,35 +821,48 @@ static int q6v5_wcss_init_reset(struct q + static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss, + struct platform_device *pdev) + { +- struct of_phandle_args args; ++ unsigned int halt_reg[MAX_HALT_REG] = {0}; ++ struct device_node *syscon; + struct resource *res; + int ret; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6"); +- wcss->reg_base = devm_ioremap_resource(&pdev->dev, res); ++ wcss->reg_base = devm_ioremap(&pdev->dev, res->start, ++ resource_size(res)); + if (IS_ERR(wcss->reg_base)) + return PTR_ERR(wcss->reg_base); + +- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb"); +- wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res); +- if (IS_ERR(wcss->rmb_base)) +- return PTR_ERR(wcss->rmb_base); ++ if (wcss->version == WCSS_IPQ8074) { ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb"); ++ wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(wcss->rmb_base)) ++ return PTR_ERR(wcss->rmb_base); ++ } + +- ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, +- "qcom,halt-regs", 3, 0, &args); +- if (ret < 0) { ++ syscon = of_parse_phandle(pdev->dev.of_node, ++ "qcom,halt-regs", 0); ++ if (!syscon) { + dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); + return -EINVAL; + } + +- wcss->halt_map = syscon_node_to_regmap(args.np); +- of_node_put(args.np); ++ wcss->halt_map = syscon_node_to_regmap(syscon); ++ of_node_put(syscon); + if (IS_ERR(wcss->halt_map)) + return PTR_ERR(wcss->halt_map); + +- wcss->halt_q6 = args.args[0]; +- wcss->halt_wcss = args.args[1]; +- wcss->halt_nc = args.args[2]; ++ ret = of_property_read_variable_u32_array(pdev->dev.of_node, ++ "qcom,halt-regs", ++ halt_reg, 0, ++ MAX_HALT_REG); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); ++ return -EINVAL; ++ } ++ ++ wcss->halt_q6 = halt_reg[0]; ++ wcss->halt_wcss = halt_reg[1]; ++ wcss->halt_nc = halt_reg[2]; + + return 0; + } +@@ -543,6 +896,107 @@ static int q6v5_alloc_memory_region(stru + return 0; + } + ++static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) ++{ ++ int ret; ++ ++ wcss->xo = devm_clk_get(wcss->dev, "xo"); ++ if (IS_ERR(wcss->xo)) { ++ ret = PTR_ERR(wcss->xo); ++ if (ret != -EPROBE_DEFER) ++ dev_err(wcss->dev, "failed to get xo clock"); ++ return ret; ++ } ++ ++ wcss->gcc_abhs_cbcr = devm_clk_get(wcss->dev, "gcc_abhs_cbcr"); ++ if (IS_ERR(wcss->gcc_abhs_cbcr)) { ++ ret = PTR_ERR(wcss->gcc_abhs_cbcr); ++ if (ret != -EPROBE_DEFER) ++ dev_err(wcss->dev, "failed to get gcc abhs clock"); ++ return PTR_ERR(wcss->gcc_abhs_cbcr); ++ } ++ ++ wcss->gcc_axim_cbcr = devm_clk_get(wcss->dev, "gcc_axim_cbcr"); ++ if (IS_ERR(wcss->gcc_axim_cbcr)) { ++ ret = PTR_ERR(wcss->gcc_axim_cbcr); ++ if (ret != -EPROBE_DEFER) ++ dev_err(wcss->dev, "failed to get gcc axim clock\n"); ++ return PTR_ERR(wcss->gcc_axim_cbcr); ++ } ++ ++ wcss->ahbfabric_cbcr_clk = devm_clk_get(wcss->dev, ++ "lcc_ahbfabric_cbc"); ++ if (IS_ERR(wcss->ahbfabric_cbcr_clk)) { ++ ret = PTR_ERR(wcss->ahbfabric_cbcr_clk); ++ if (ret != -EPROBE_DEFER) ++ dev_err(wcss->dev, "failed to get ahbfabric clock\n"); ++ return PTR_ERR(wcss->ahbfabric_cbcr_clk); ++ } ++ ++ wcss->lcc_csr_cbcr = devm_clk_get(wcss->dev, "tcsr_lcc_cbc"); ++ if (IS_ERR(wcss->lcc_csr_cbcr)) { ++ ret = PTR_ERR(wcss->lcc_csr_cbcr); ++ if (ret != -EPROBE_DEFER) ++ dev_err(wcss->dev, "failed to get csr cbcr clk\n"); ++ return PTR_ERR(wcss->lcc_csr_cbcr); ++ } ++ ++ wcss->ahbs_cbcr = devm_clk_get(wcss->dev, ++ "lcc_abhs_cbc"); ++ if (IS_ERR(wcss->ahbs_cbcr)) { ++ ret = PTR_ERR(wcss->ahbs_cbcr); ++ if (ret != -EPROBE_DEFER) ++ dev_err(wcss->dev, "failed to get ahbs_cbcr clk\n"); ++ return PTR_ERR(wcss->ahbs_cbcr); ++ } ++ ++ wcss->tcm_slave_cbcr = devm_clk_get(wcss->dev, ++ "lcc_tcm_slave_cbc"); ++ if (IS_ERR(wcss->tcm_slave_cbcr)) { ++ ret = PTR_ERR(wcss->tcm_slave_cbcr); ++ if (ret != -EPROBE_DEFER) ++ dev_err(wcss->dev, "failed to get tcm cbcr clk\n"); ++ return PTR_ERR(wcss->tcm_slave_cbcr); ++ } ++ ++ wcss->qdsp6ss_abhm_cbcr = devm_clk_get(wcss->dev, "lcc_abhm_cbc"); ++ if (IS_ERR(wcss->qdsp6ss_abhm_cbcr)) { ++ ret = PTR_ERR(wcss->qdsp6ss_abhm_cbcr); ++ if (ret != -EPROBE_DEFER) ++ dev_err(wcss->dev, "failed to get abhm cbcr clk\n"); ++ return PTR_ERR(wcss->qdsp6ss_abhm_cbcr); ++ } ++ ++ wcss->qdsp6ss_axim_cbcr = devm_clk_get(wcss->dev, "lcc_axim_cbc"); ++ if (IS_ERR(wcss->qdsp6ss_axim_cbcr)) { ++ ret = PTR_ERR(wcss->qdsp6ss_axim_cbcr); ++ if (ret != -EPROBE_DEFER) ++ dev_err(wcss->dev, "failed to get axim cbcr clk\n"); ++ return PTR_ERR(wcss->qdsp6ss_abhm_cbcr); ++ } ++ ++ wcss->lcc_bcr_sleep = devm_clk_get(wcss->dev, "lcc_bcr_sleep"); ++ if (IS_ERR(wcss->lcc_bcr_sleep)) { ++ ret = PTR_ERR(wcss->lcc_bcr_sleep); ++ if (ret != -EPROBE_DEFER) ++ dev_err(wcss->dev, "failed to get bcr cbcr clk\n"); ++ return PTR_ERR(wcss->lcc_bcr_sleep); ++ } ++ ++ return 0; ++} ++ ++static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss) ++{ ++ wcss->cx_supply = devm_regulator_get(wcss->dev, "cx"); ++ if (IS_ERR(wcss->cx_supply)) ++ return PTR_ERR(wcss->cx_supply); ++ ++ regulator_set_load(wcss->cx_supply, 100000); ++ ++ return 0; ++} ++ + static int q6v5_wcss_probe(struct platform_device *pdev) + { + const struct wcss_data *desc; +@@ -554,7 +1008,7 @@ static int q6v5_wcss_probe(struct platfo + if (!desc) + return -EINVAL; + +- rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops, ++ rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops, + desc->firmware_name, sizeof(*wcss)); + if (!rproc) { + dev_err(&pdev->dev, "failed to allocate rproc\n"); +@@ -563,7 +1017,10 @@ static int q6v5_wcss_probe(struct platfo + + wcss = rproc->priv; + wcss->dev = &pdev->dev; +- wcss->crash_reason_smem = desc->crash_reason_smem; ++ wcss->version = desc->version; ++ ++ wcss->version = desc->version; ++ wcss->requires_force_stop = desc->requires_force_stop; + + ret = q6v5_wcss_init_mmio(wcss, pdev); + if (ret) +@@ -573,7 +1030,17 @@ static int q6v5_wcss_probe(struct platfo + if (ret) + goto free_rproc; + +- ret = q6v5_wcss_init_reset(wcss); ++ if (wcss->version == WCSS_QCS404) { ++ ret = q6v5_wcss_init_clock(wcss); ++ if (ret) ++ goto free_rproc; ++ ++ ret = q6v5_wcss_init_regulator(wcss); ++ if (ret) ++ goto free_rproc; ++ } ++ ++ ret = q6v5_wcss_init_reset(wcss, desc); + if (ret) + goto free_rproc; + +@@ -584,6 +1051,9 @@ static int q6v5_wcss_probe(struct platfo + + qcom_add_glink_subdev(rproc, &wcss->glink_subdev); + qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss"); ++ wcss->sysmon = qcom_add_sysmon_subdev(rproc, ++ desc->sysmon_name, ++ desc->ssctl_id); + + ret = rproc_add(rproc); + if (ret) +@@ -612,10 +1082,28 @@ static int q6v5_wcss_remove(struct platf + static const struct wcss_data wcss_ipq8074_res_init = { + .firmware_name = "IPQ8074/q6_fw.mdt", + .crash_reason_smem = WCSS_CRASH_REASON, ++ .aon_reset_required = true, ++ .wcss_q6_reset_required = true, ++ .ops = &q6v5_wcss_ipq8074_ops, ++ .requires_force_stop = true, ++}; ++ ++static const struct wcss_data wcss_qcs404_res_init = { ++ .crash_reason_smem = WCSS_CRASH_REASON, ++ .firmware_name = "wcnss.mdt", ++ .version = WCSS_QCS404, ++ .aon_reset_required = false, ++ .wcss_q6_reset_required = false, ++ .ssr_name = "mpss", ++ .sysmon_name = "wcnss", ++ .ssctl_id = 0x12, ++ .ops = &q6v5_wcss_qcs404_ops, ++ .requires_force_stop = false, + }; + + static const struct of_device_id q6v5_wcss_of_match[] = { + { .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init }, ++ { .compatible = "qcom,qcs404-wcss-pil", .data = &wcss_qcs404_res_init }, + { }, + }; + MODULE_DEVICE_TABLE(of, q6v5_wcss_of_match); diff --git a/target/linux/ipq807x/patches-5.4/106-03-remoteproc-qcom-wcss-explicitly-request-exclusive-reset-control.patch b/target/linux/ipq807x/patches-5.4/106-03-remoteproc-qcom-wcss-explicitly-request-exclusive-reset-control.patch new file mode 100644 index 00000000000000..e8859f130048f9 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/106-03-remoteproc-qcom-wcss-explicitly-request-exclusive-reset-control.patch @@ -0,0 +1,91 @@ +From patchwork Thu Jul 30 12:14:04 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Gokul Sriram Palanisamy +X-Patchwork-Id: 11692911 +Return-Path: +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22C5E13B1 + for ; + Thu, 30 Jul 2020 12:14:36 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 14CA4208A9 + for ; + Thu, 30 Jul 2020 12:14:36 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1727844AbgG3MOe (ORCPT + ); + Thu, 30 Jul 2020 08:14:34 -0400 +Received: from alexa-out.qualcomm.com ([129.46.98.28]:15938 "EHLO + alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1726967AbgG3MOe (ORCPT + ); + Thu, 30 Jul 2020 08:14:34 -0400 +Received: from ironmsg07-lv.qualcomm.com (HELO ironmsg07-lv.qulacomm.com) + ([10.47.202.151]) + by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:14:33 -0700 +Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) + by ironmsg07-lv.qulacomm.com with ESMTP/TLS/AES256-SHA; + 30 Jul 2020 05:14:31 -0700 +Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) + by ironmsg01-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:44:06 +0530 +Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) + id 40628218A1; Thu, 30 Jul 2020 17:44:05 +0530 (IST) +From: Gokul Sriram Palanisamy +To: bjorn.andersson@linaro.org, linux-remoteproc@vger.kernel.org, + sboyd@kernel.org, linux-clk@vger.kernel.org, + linux-arm-msm@vger.kernel.org +Cc: agross@kernel.org, linux-soc@vger.kernel.org, + devicetree@vger.kernel.org, govinds@codeaurora.org, + sricharan@codeaurora.org, gokulsri@codeaurora.org +Subject: [PATCH v8 4/4] remoteproc: qcom: wcss: explicitly request exclusive + reset control +Date: Thu, 30 Jul 2020 17:44:04 +0530 +Message-Id: <1596111244-28411-5-git-send-email-gokulsri@codeaurora.org> +X-Mailer: git-send-email 2.7.4 +In-Reply-To: <1596111244-28411-1-git-send-email-gokulsri@codeaurora.org> +References: <1596111244-28411-1-git-send-email-gokulsri@codeaurora.org> +Sender: linux-arm-msm-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-arm-msm@vger.kernel.org + +From: Govind Singh + +Use request exclusive reset control for wcss reset controls. + +Signed-off-by: Govind Singh +Signed-off-by: Gokul Sriram Palanisamy +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -788,21 +788,21 @@ static int q6v5_wcss_init_reset(struct q + struct device *dev = wcss->dev; + + if (desc->aon_reset_required) { +- wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset"); ++ wcss->wcss_aon_reset = devm_reset_control_get_exclusive(dev, "wcss_aon_reset"); + if (IS_ERR(wcss->wcss_aon_reset)) { + dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n"); + return PTR_ERR(wcss->wcss_aon_reset); + } + } + +- wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset"); ++ wcss->wcss_reset = devm_reset_control_get_exclusive(dev, "wcss_reset"); + if (IS_ERR(wcss->wcss_reset)) { + dev_err(wcss->dev, "unable to acquire wcss_reset\n"); + return PTR_ERR(wcss->wcss_reset); + } + + if (desc->wcss_q6_reset_required) { +- wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset"); ++ wcss->wcss_q6_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_reset"); + if (IS_ERR(wcss->wcss_q6_reset)) { + dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n"); + return PTR_ERR(wcss->wcss_q6_reset); diff --git a/target/linux/ipq807x/patches-5.4/106-04-remoteproc-qcom-Add-PRNG-proxy-clock.patch b/target/linux/ipq807x/patches-5.4/106-04-remoteproc-qcom-Add-PRNG-proxy-clock.patch new file mode 100644 index 00000000000000..f19d641be0f2ee --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/106-04-remoteproc-qcom-Add-PRNG-proxy-clock.patch @@ -0,0 +1,204 @@ +From patchwork Thu Jul 30 12:26:35 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Gokul Sriram Palanisamy +X-Patchwork-Id: 11692951 +Return-Path: +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A2A513B6 + for ; + Thu, 30 Jul 2020 12:29:02 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 0B7292082E + for ; + Thu, 30 Jul 2020 12:29:02 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1728690AbgG3M3B (ORCPT + ); + Thu, 30 Jul 2020 08:29:01 -0400 +Received: from alexa-out.qualcomm.com ([129.46.98.28]:43483 "EHLO + alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1728430AbgG3M2t (ORCPT + ); + Thu, 30 Jul 2020 08:28:49 -0400 +Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) + by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:48 -0700 +Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) + by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; + 30 Jul 2020 05:28:46 -0700 +Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) + by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:11 +0530 +Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) + id F3197218A1; Thu, 30 Jul 2020 17:58:09 +0530 (IST) +From: Gokul Sriram Palanisamy +To: gokulsri@codeaurora.org, agross@kernel.org, + bjorn.andersson@linaro.org, david.brown@linaro.org, + devicetree@vger.kernel.org, jassisinghbrar@gmail.com, + linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, + linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, + mark.rutland@arm.com, mturquette@baylibre.com, + nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, + sboyd@kernel.org, sricharan@codeaurora.org +Subject: [PATCH v7 1/9] remoteproc: qcom: Add PRNG proxy clock +Date: Thu, 30 Jul 2020 17:56:35 +0530 +Message-Id: <1596112003-31663-2-git-send-email-gokulsri@codeaurora.org> +X-Mailer: git-send-email 2.7.4 +In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +Sender: linux-arm-msm-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-arm-msm@vger.kernel.org + +PRNG clock is needed by the secure PIL, support for the same +is added in subsequent patches. + +Signed-off-by: Gokul Sriram Palanisamy +Signed-off-by: Sricharan R +Signed-off-by: Nikhil Prakash V +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++++++++---------- + 1 file changed, 47 insertions(+), 18 deletions(-) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -91,19 +91,6 @@ enum { + WCSS_QCS404, + }; + +-struct wcss_data { +- const char *firmware_name; +- unsigned int crash_reason_smem; +- u32 version; +- bool aon_reset_required; +- bool wcss_q6_reset_required; +- const char *ssr_name; +- const char *sysmon_name; +- int ssctl_id; +- const struct rproc_ops *ops; +- bool requires_force_stop; +-}; +- + struct q6v5_wcss { + struct device *dev; + +@@ -128,6 +115,7 @@ struct q6v5_wcss { + struct clk *qdsp6ss_xo_cbcr; + struct clk *qdsp6ss_core_gfmux; + struct clk *lcc_bcr_sleep; ++ struct clk *prng_clk; + struct regulator *cx_supply; + struct qcom_sysmon *sysmon; + +@@ -151,6 +139,21 @@ struct q6v5_wcss { + struct qcom_rproc_ssr ssr_subdev; + }; + ++struct wcss_data { ++ int (*init_clock)(struct q6v5_wcss *wcss); ++ int (*init_regulator)(struct q6v5_wcss *wcss); ++ const char *firmware_name; ++ unsigned int crash_reason_smem; ++ u32 version; ++ bool aon_reset_required; ++ bool wcss_q6_reset_required; ++ const char *ssr_name; ++ const char *sysmon_name; ++ int ssctl_id; ++ const struct rproc_ops *ops; ++ bool requires_force_stop; ++}; ++ + static int q6v5_wcss_reset(struct q6v5_wcss *wcss) + { + int ret; +@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc + struct q6v5_wcss *wcss = rproc->priv; + int ret; + ++ ret = clk_prepare_enable(wcss->prng_clk); ++ if (ret) { ++ dev_err(wcss->dev, "prng clock enable failed\n"); ++ return ret; ++ } ++ + qcom_q6v5_prepare(&wcss->q6v5); + + /* Release Q6 and WCSS reset */ +@@ -732,6 +741,7 @@ static int q6v5_wcss_stop(struct rproc * + return ret; + } + ++ clk_disable_unprepare(wcss->prng_clk); + qcom_q6v5_unprepare(&wcss->q6v5); + + return 0; +@@ -896,7 +906,21 @@ static int q6v5_alloc_memory_region(stru + return 0; + } + +-static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) ++static int ipq8074_init_clock(struct q6v5_wcss *wcss) ++{ ++ int ret; ++ ++ wcss->prng_clk = devm_clk_get(wcss->dev, "prng"); ++ if (IS_ERR(wcss->prng_clk)) { ++ ret = PTR_ERR(wcss->prng_clk); ++ if (ret != -EPROBE_DEFER) ++ dev_err(wcss->dev, "Failed to get prng clock\n"); ++ return ret; ++ } ++ return 0; ++} ++ ++static int qcs404_init_clock(struct q6v5_wcss *wcss) + { + int ret; + +@@ -986,7 +1010,7 @@ static int q6v5_wcss_init_clock(struct q + return 0; + } + +-static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss) ++static int qcs404_init_regulator(struct q6v5_wcss *wcss) + { + wcss->cx_supply = devm_regulator_get(wcss->dev, "cx"); + if (IS_ERR(wcss->cx_supply)) +@@ -1030,12 +1054,14 @@ static int q6v5_wcss_probe(struct platfo + if (ret) + goto free_rproc; + +- if (wcss->version == WCSS_QCS404) { +- ret = q6v5_wcss_init_clock(wcss); ++ if (desc->init_clock) { ++ ret = desc->init_clock(wcss); + if (ret) + goto free_rproc; ++ } + +- ret = q6v5_wcss_init_regulator(wcss); ++ if (desc->init_regulator) { ++ ret = desc->init_regulator(wcss); + if (ret) + goto free_rproc; + } +@@ -1080,6 +1106,7 @@ static int q6v5_wcss_remove(struct platf + } + + static const struct wcss_data wcss_ipq8074_res_init = { ++ .init_clock = ipq8074_init_clock, + .firmware_name = "IPQ8074/q6_fw.mdt", + .crash_reason_smem = WCSS_CRASH_REASON, + .aon_reset_required = true, +@@ -1089,6 +1116,8 @@ static const struct wcss_data wcss_ipq80 + }; + + static const struct wcss_data wcss_qcs404_res_init = { ++ .init_clock = qcs404_init_clock, ++ .init_regulator = qcs404_init_regulator, + .crash_reason_smem = WCSS_CRASH_REASON, + .firmware_name = "wcnss.mdt", + .version = WCSS_QCS404, diff --git a/target/linux/ipq807x/patches-5.4/106-05-remoteproc-qcom-Add-secure-PIL-support.patch b/target/linux/ipq807x/patches-5.4/106-05-remoteproc-qcom-Add-secure-PIL-support.patch new file mode 100644 index 00000000000000..1dc3dfd40ba413 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/106-05-remoteproc-qcom-Add-secure-PIL-support.patch @@ -0,0 +1,192 @@ +From patchwork Thu Jul 30 12:26:36 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Gokul Sriram Palanisamy +X-Patchwork-Id: 11692981 +Return-Path: +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 430041744 + for ; + Thu, 30 Jul 2020 12:29:20 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 346672082E + for ; + Thu, 30 Jul 2020 12:29:20 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1728528AbgG3M3S (ORCPT + ); + Thu, 30 Jul 2020 08:29:18 -0400 +Received: from alexa-out.qualcomm.com ([129.46.98.28]:43483 "EHLO + alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1728318AbgG3M2r (ORCPT + ); + Thu, 30 Jul 2020 08:28:47 -0400 +Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) + by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:46 -0700 +Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) + by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; + 30 Jul 2020 05:28:44 -0700 +Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) + by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:13 +0530 +Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) + id 072B2218A1; Thu, 30 Jul 2020 17:58:11 +0530 (IST) +From: Gokul Sriram Palanisamy +To: gokulsri@codeaurora.org, agross@kernel.org, + bjorn.andersson@linaro.org, david.brown@linaro.org, + devicetree@vger.kernel.org, jassisinghbrar@gmail.com, + linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, + linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, + mark.rutland@arm.com, mturquette@baylibre.com, + nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, + sboyd@kernel.org, sricharan@codeaurora.org +Subject: [PATCH v7 2/9] remoteproc: qcom: Add secure PIL support +Date: Thu, 30 Jul 2020 17:56:36 +0530 +Message-Id: <1596112003-31663-3-git-send-email-gokulsri@codeaurora.org> +X-Mailer: git-send-email 2.7.4 +In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +Sender: linux-arm-msm-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-arm-msm@vger.kernel.org + +IPQ8074 uses secure PIL. Hence, adding the support for the same. + +Signed-off-by: Gokul Sriram Palanisamy +Signed-off-by: Sricharan R +Signed-off-by: Nikhil Prakash V +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 43 ++++++++++++++++++++++++++++++++++--- + 1 file changed, 40 insertions(+), 3 deletions(-) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -18,6 +18,7 @@ + #include + #include + #include ++#include + #include "qcom_common.h" + #include "qcom_pil_info.h" + #include "qcom_q6v5.h" +@@ -86,6 +87,9 @@ + #define TCSR_WCSS_CLK_ENABLE 0x14 + + #define MAX_HALT_REG 3 ++ ++#define WCNSS_PAS_ID 6 ++ + enum { + WCSS_IPQ8074, + WCSS_QCS404, +@@ -134,6 +138,7 @@ struct q6v5_wcss { + unsigned int crash_reason_smem; + u32 version; + bool requires_force_stop; ++ bool need_mem_protection; + + struct qcom_rproc_glink glink_subdev; + struct qcom_rproc_ssr ssr_subdev; +@@ -152,6 +157,7 @@ struct wcss_data { + int ssctl_id; + const struct rproc_ops *ops; + bool requires_force_stop; ++ bool need_mem_protection; + }; + + static int q6v5_wcss_reset(struct q6v5_wcss *wcss) +@@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc + + qcom_q6v5_prepare(&wcss->q6v5); + ++ if (wcss->need_mem_protection) { ++ ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID); ++ if (ret) { ++ dev_err(wcss->dev, "wcss_reset failed\n"); ++ return ret; ++ } ++ goto wait_for_reset; ++ } ++ + /* Release Q6 and WCSS reset */ + ret = reset_control_deassert(wcss->wcss_reset); + if (ret) { +@@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc + if (ret) + goto wcss_q6_reset; + ++wait_for_reset: + ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); + if (ret == -ETIMEDOUT) + dev_err(wcss->dev, "start timed out\n"); +@@ -717,6 +733,15 @@ static int q6v5_wcss_stop(struct rproc * + struct q6v5_wcss *wcss = rproc->priv; + int ret; + ++ if (wcss->need_mem_protection) { ++ ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID); ++ if (ret) { ++ dev_err(wcss->dev, "not able to shutdown\n"); ++ return ret; ++ } ++ goto pas_done; ++ } ++ + /* WCSS powerdown */ + if (wcss->requires_force_stop) { + ret = qcom_q6v5_request_stop(&wcss->q6v5); +@@ -741,6 +766,7 @@ static int q6v5_wcss_stop(struct rproc * + return ret; + } + ++pas_done: + clk_disable_unprepare(wcss->prng_clk); + qcom_q6v5_unprepare(&wcss->q6v5); + +@@ -764,9 +790,15 @@ static int q6v5_wcss_load(struct rproc * + struct q6v5_wcss *wcss = rproc->priv; + int ret; + +- ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, +- 0, wcss->mem_region, wcss->mem_phys, +- wcss->mem_size, &wcss->mem_reloc); ++ if (wcss->need_mem_protection) ++ ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware, ++ WCNSS_PAS_ID, wcss->mem_region, ++ wcss->mem_phys, wcss->mem_size, ++ &wcss->mem_reloc); ++ else ++ ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, ++ 0, wcss->mem_region, wcss->mem_phys, ++ wcss->mem_size, &wcss->mem_reloc); + if (ret) + return ret; + +@@ -1032,6 +1064,9 @@ static int q6v5_wcss_probe(struct platfo + if (!desc) + return -EINVAL; + ++ if (desc->need_mem_protection && !qcom_scm_is_available()) ++ return -EPROBE_DEFER; ++ + rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops, + desc->firmware_name, sizeof(*wcss)); + if (!rproc) { +@@ -1045,6 +1080,7 @@ static int q6v5_wcss_probe(struct platfo + + wcss->version = desc->version; + wcss->requires_force_stop = desc->requires_force_stop; ++ wcss->need_mem_protection = desc->need_mem_protection; + + ret = q6v5_wcss_init_mmio(wcss, pdev); + if (ret) +@@ -1113,6 +1149,7 @@ static const struct wcss_data wcss_ipq80 + .wcss_q6_reset_required = true, + .ops = &q6v5_wcss_ipq8074_ops, + .requires_force_stop = true, ++ .need_mem_protection = true, + }; + + static const struct wcss_data wcss_qcs404_res_init = { diff --git a/target/linux/ipq807x/patches-5.4/106-06-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-firmware.patch b/target/linux/ipq807x/patches-5.4/106-06-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-firmware.patch new file mode 100644 index 00000000000000..3346b34609d475 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/106-06-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-firmware.patch @@ -0,0 +1,153 @@ +From patchwork Thu Jul 30 12:26:37 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Gokul Sriram Palanisamy +X-Patchwork-Id: 11692965 +Return-Path: +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BBE09722 + for ; + Thu, 30 Jul 2020 12:29:16 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id A87452082E + for ; + Thu, 30 Jul 2020 12:29:16 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1728400AbgG3M2s (ORCPT + ); + Thu, 30 Jul 2020 08:28:48 -0400 +Received: from alexa-out.qualcomm.com ([129.46.98.28]:26713 "EHLO + alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1728315AbgG3M2q (ORCPT + ); + Thu, 30 Jul 2020 08:28:46 -0400 +Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) + by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:46 -0700 +Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) + by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; + 30 Jul 2020 05:28:44 -0700 +Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) + by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:13 +0530 +Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) + id 1DA23213B6; Thu, 30 Jul 2020 17:58:12 +0530 (IST) +From: Gokul Sriram Palanisamy +To: gokulsri@codeaurora.org, agross@kernel.org, + bjorn.andersson@linaro.org, david.brown@linaro.org, + devicetree@vger.kernel.org, jassisinghbrar@gmail.com, + linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, + linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, + mark.rutland@arm.com, mturquette@baylibre.com, + nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, + sboyd@kernel.org, sricharan@codeaurora.org +Subject: [PATCH v7 3/9] remoteproc: qcom: Add support for split q6 + m3 wlan + firmware +Date: Thu, 30 Jul 2020 17:56:37 +0530 +Message-Id: <1596112003-31663-4-git-send-email-gokulsri@codeaurora.org> +X-Mailer: git-send-email 2.7.4 +In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +Sender: linux-arm-msm-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-arm-msm@vger.kernel.org + +IPQ8074 supports split firmware for q6 and m3 as well. +So add support for loading the m3 firmware before q6. +Now the drivers works fine for both split and unified +firmwares. + +Signed-off-by: Gokul Sriram Palanisamy +Signed-off-by: Sricharan R +Signed-off-by: Nikhil Prakash V +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 33 +++++++++++++++++++++++++++++---- + 1 file changed, 29 insertions(+), 4 deletions(-) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -139,6 +139,7 @@ struct q6v5_wcss { + u32 version; + bool requires_force_stop; + bool need_mem_protection; ++ const char *m3_firmware_name; + + struct qcom_rproc_glink glink_subdev; + struct qcom_rproc_ssr ssr_subdev; +@@ -147,7 +148,8 @@ struct q6v5_wcss { + struct wcss_data { + int (*init_clock)(struct q6v5_wcss *wcss); + int (*init_regulator)(struct q6v5_wcss *wcss); +- const char *firmware_name; ++ const char *q6_firmware_name; ++ const char *m3_firmware_name; + unsigned int crash_reason_smem; + u32 version; + bool aon_reset_required; +@@ -788,8 +790,29 @@ static void *q6v5_wcss_da_to_va(struct r + static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) + { + struct q6v5_wcss *wcss = rproc->priv; ++ const struct firmware *m3_fw; + int ret; + ++ if (wcss->m3_firmware_name) { ++ ret = request_firmware(&m3_fw, wcss->m3_firmware_name, ++ wcss->dev); ++ if (ret) ++ goto skip_m3; ++ ++ ret = qcom_mdt_load_no_init(wcss->dev, m3_fw, ++ wcss->m3_firmware_name, 0, ++ wcss->mem_region, wcss->mem_phys, ++ wcss->mem_size, &wcss->mem_reloc); ++ ++ release_firmware(m3_fw); ++ ++ if (ret) { ++ dev_err(wcss->dev, "can't load m3_fw.bXX\n"); ++ return ret; ++ } ++ } ++ ++skip_m3: + if (wcss->need_mem_protection) + ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware, + WCNSS_PAS_ID, wcss->mem_region, +@@ -1068,7 +1091,7 @@ static int q6v5_wcss_probe(struct platfo + return -EPROBE_DEFER; + + rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops, +- desc->firmware_name, sizeof(*wcss)); ++ desc->q6_firmware_name, sizeof(*wcss)); + if (!rproc) { + dev_err(&pdev->dev, "failed to allocate rproc\n"); + return -ENOMEM; +@@ -1081,6 +1104,7 @@ static int q6v5_wcss_probe(struct platfo + wcss->version = desc->version; + wcss->requires_force_stop = desc->requires_force_stop; + wcss->need_mem_protection = desc->need_mem_protection; ++ wcss->m3_firmware_name = desc->m3_firmware_name; + + ret = q6v5_wcss_init_mmio(wcss, pdev); + if (ret) +@@ -1143,7 +1167,8 @@ static int q6v5_wcss_remove(struct platf + + static const struct wcss_data wcss_ipq8074_res_init = { + .init_clock = ipq8074_init_clock, +- .firmware_name = "IPQ8074/q6_fw.mdt", ++ .q6_firmware_name = "IPQ8074/q6_fw.mdt", ++ .m3_firmware_name = "IPQ8074/m3_fw.mdt", + .crash_reason_smem = WCSS_CRASH_REASON, + .aon_reset_required = true, + .wcss_q6_reset_required = true, +@@ -1156,7 +1181,7 @@ static const struct wcss_data wcss_qcs40 + .init_clock = qcs404_init_clock, + .init_regulator = qcs404_init_regulator, + .crash_reason_smem = WCSS_CRASH_REASON, +- .firmware_name = "wcnss.mdt", ++ .q6_firmware_name = "wcnss.mdt", + .version = WCSS_QCS404, + .aon_reset_required = false, + .wcss_q6_reset_required = false, diff --git a/target/linux/ipq807x/patches-5.4/106-07-remoteproc-qcom-Add-ssr-subdevice-identifier.patch b/target/linux/ipq807x/patches-5.4/106-07-remoteproc-qcom-Add-ssr-subdevice-identifier.patch new file mode 100644 index 00000000000000..c4752054009761 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/106-07-remoteproc-qcom-Add-ssr-subdevice-identifier.patch @@ -0,0 +1,73 @@ +From patchwork Thu Jul 30 12:26:38 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Gokul Sriram Palanisamy +X-Patchwork-Id: 11692943 +Return-Path: +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A1B881744 + for ; + Thu, 30 Jul 2020 12:28:46 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 89AB422B3F + for ; + Thu, 30 Jul 2020 12:28:46 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1728303AbgG3M2q (ORCPT + ); + Thu, 30 Jul 2020 08:28:46 -0400 +Received: from alexa-out.qualcomm.com ([129.46.98.28]:43483 "EHLO + alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1728248AbgG3M2o (ORCPT + ); + Thu, 30 Jul 2020 08:28:44 -0400 +Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) + by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:44 -0700 +Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) + by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; + 30 Jul 2020 05:28:42 -0700 +Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) + by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:14 +0530 +Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) + id 2E02C218A2; Thu, 30 Jul 2020 17:58:12 +0530 (IST) +From: Gokul Sriram Palanisamy +To: gokulsri@codeaurora.org, agross@kernel.org, + bjorn.andersson@linaro.org, david.brown@linaro.org, + devicetree@vger.kernel.org, jassisinghbrar@gmail.com, + linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, + linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, + mark.rutland@arm.com, mturquette@baylibre.com, + nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, + sboyd@kernel.org, sricharan@codeaurora.org +Subject: [PATCH v7 4/9] remoteproc: qcom: Add ssr subdevice identifier +Date: Thu, 30 Jul 2020 17:56:38 +0530 +Message-Id: <1596112003-31663-5-git-send-email-gokulsri@codeaurora.org> +X-Mailer: git-send-email 2.7.4 +In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +Sender: linux-arm-msm-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-arm-msm@vger.kernel.org + +Add name for ssr subdevice on IPQ8074 SoC. + +Signed-off-by: Gokul Sriram Palanisamy +Signed-off-by: Sricharan R +Signed-off-by: Nikhil Prakash V +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -1172,6 +1172,7 @@ static const struct wcss_data wcss_ipq80 + .crash_reason_smem = WCSS_CRASH_REASON, + .aon_reset_required = true, + .wcss_q6_reset_required = true, ++ .ssr_name = "q6wcss", + .ops = &q6v5_wcss_ipq8074_ops, + .requires_force_stop = true, + .need_mem_protection = true, diff --git a/target/linux/ipq807x/patches-5.4/106-08-remoteproc-qcom-Update-regmap-offsets-for-halt-register.patch b/target/linux/ipq807x/patches-5.4/106-08-remoteproc-qcom-Update-regmap-offsets-for-halt-register.patch new file mode 100644 index 00000000000000..d703467b839d9a --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/106-08-remoteproc-qcom-Update-regmap-offsets-for-halt-register.patch @@ -0,0 +1,129 @@ +From patchwork Thu Jul 30 12:26:39 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Gokul Sriram Palanisamy +X-Patchwork-Id: 11692949 +Return-Path: +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 03EB21746 + for ; + Thu, 30 Jul 2020 12:29:01 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id E79E222CAD + for ; + Thu, 30 Jul 2020 12:29:00 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1728641AbgG3M24 (ORCPT + ); + Thu, 30 Jul 2020 08:28:56 -0400 +Received: from alexa-out.qualcomm.com ([129.46.98.28]:23866 "EHLO + alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1728529AbgG3M2t (ORCPT + ); + Thu, 30 Jul 2020 08:28:49 -0400 +Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) + by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:48 -0700 +Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) + by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; + 30 Jul 2020 05:28:46 -0700 +Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) + by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:14 +0530 +Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) + id 46F3A218A3; Thu, 30 Jul 2020 17:58:12 +0530 (IST) +From: Gokul Sriram Palanisamy +To: gokulsri@codeaurora.org, agross@kernel.org, + bjorn.andersson@linaro.org, david.brown@linaro.org, + devicetree@vger.kernel.org, jassisinghbrar@gmail.com, + linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, + linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, + mark.rutland@arm.com, mturquette@baylibre.com, + nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, + sboyd@kernel.org, sricharan@codeaurora.org +Subject: [PATCH v7 5/9] remoteproc: qcom: Update regmap offsets for halt + register +Date: Thu, 30 Jul 2020 17:56:39 +0530 +Message-Id: <1596112003-31663-6-git-send-email-gokulsri@codeaurora.org> +X-Mailer: git-send-email 2.7.4 +In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +Sender: linux-arm-msm-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-arm-msm@vger.kernel.org + +Fixed issue in reading halt-regs parameter from device-tree. + +Signed-off-by: Gokul Sriram Palanisamy +Signed-off-by: Sricharan R +--- + drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++-------- + 1 file changed, 14 insertions(+), 8 deletions(-) + +--- a/drivers/remoteproc/qcom_q6v5_wcss.c ++++ b/drivers/remoteproc/qcom_q6v5_wcss.c +@@ -86,7 +86,7 @@ + #define TCSR_WCSS_CLK_MASK 0x1F + #define TCSR_WCSS_CLK_ENABLE 0x14 + +-#define MAX_HALT_REG 3 ++#define MAX_HALT_REG 4 + + #define WCNSS_PAS_ID 6 + +@@ -154,6 +154,7 @@ struct wcss_data { + u32 version; + bool aon_reset_required; + bool wcss_q6_reset_required; ++ bool bcr_reset_required; + const char *ssr_name; + const char *sysmon_name; + int ssctl_id; +@@ -874,10 +875,13 @@ static int q6v5_wcss_init_reset(struct q + } + } + +- wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset"); +- if (IS_ERR(wcss->wcss_q6_bcr_reset)) { +- dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); +- return PTR_ERR(wcss->wcss_q6_bcr_reset); ++ if (desc->bcr_reset_required) { ++ wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, ++ "wcss_q6_bcr_reset"); ++ if (IS_ERR(wcss->wcss_q6_bcr_reset)) { ++ dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); ++ return PTR_ERR(wcss->wcss_q6_bcr_reset); ++ } + } + + return 0; +@@ -925,9 +929,9 @@ static int q6v5_wcss_init_mmio(struct q6 + return -EINVAL; + } + +- wcss->halt_q6 = halt_reg[0]; +- wcss->halt_wcss = halt_reg[1]; +- wcss->halt_nc = halt_reg[2]; ++ wcss->halt_q6 = halt_reg[1]; ++ wcss->halt_wcss = halt_reg[2]; ++ wcss->halt_nc = halt_reg[3]; + + return 0; + } +@@ -1172,6 +1176,7 @@ static const struct wcss_data wcss_ipq80 + .crash_reason_smem = WCSS_CRASH_REASON, + .aon_reset_required = true, + .wcss_q6_reset_required = true, ++ .bcr_reset_required = false, + .ssr_name = "q6wcss", + .ops = &q6v5_wcss_ipq8074_ops, + .requires_force_stop = true, +@@ -1186,6 +1191,7 @@ static const struct wcss_data wcss_qcs40 + .version = WCSS_QCS404, + .aon_reset_required = false, + .wcss_q6_reset_required = false, ++ .bcr_reset_required = true, + .ssr_name = "mpss", + .sysmon_name = "wcnss", + .ssctl_id = 0x12, diff --git a/target/linux/ipq807x/patches-5.4/106-09-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch b/target/linux/ipq807x/patches-5.4/106-09-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch new file mode 100644 index 00000000000000..7980b173ccf830 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/106-09-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch @@ -0,0 +1,74 @@ +From patchwork Thu Jul 30 12:26:40 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Gokul Sriram Palanisamy +X-Patchwork-Id: 11692973 +Return-Path: +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 82285722 + for ; + Thu, 30 Jul 2020 12:29:18 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 6A4A220842 + for ; + Thu, 30 Jul 2020 12:29:18 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1728355AbgG3M2s (ORCPT + ); + Thu, 30 Jul 2020 08:28:48 -0400 +Received: from alexa-out.qualcomm.com ([129.46.98.28]:23711 "EHLO + alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1728322AbgG3M2q (ORCPT + ); + Thu, 30 Jul 2020 08:28:46 -0400 +Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) + by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:46 -0700 +Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) + by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; + 30 Jul 2020 05:28:44 -0700 +Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) + by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:14 +0530 +Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) + id 7293D218A4; Thu, 30 Jul 2020 17:58:12 +0530 (IST) +From: Gokul Sriram Palanisamy +To: gokulsri@codeaurora.org, agross@kernel.org, + bjorn.andersson@linaro.org, david.brown@linaro.org, + devicetree@vger.kernel.org, jassisinghbrar@gmail.com, + linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, + linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, + mark.rutland@arm.com, mturquette@baylibre.com, + nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, + sboyd@kernel.org, sricharan@codeaurora.org +Subject: [PATCH v7 6/9] dt-bindings: clock: qcom: Add reset for WCSSAON +Date: Thu, 30 Jul 2020 17:56:40 +0530 +Message-Id: <1596112003-31663-7-git-send-email-gokulsri@codeaurora.org> +X-Mailer: git-send-email 2.7.4 +In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +Sender: linux-arm-msm-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-arm-msm@vger.kernel.org + +Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC. + +Signed-off-by: Gokul Sriram Palanisamy +Signed-off-by: Sricharan R +Signed-off-by: Nikhil Prakash V +Acked-by: Rob Herring +Acked-by: Stephen Boyd +--- + include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + + 1 file changed, 1 insertion(+) + +--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h ++++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h +@@ -362,5 +362,6 @@ + #define GCC_PCIE1_AXI_SLAVE_ARES 128 + #define GCC_PCIE1_AHB_ARES 129 + #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 ++#define GCC_WCSSAON_RESET 132 + + #endif diff --git a/target/linux/ipq807x/patches-5.4/106-10-clk-qcom-Add-WCSSAON-reset.patch b/target/linux/ipq807x/patches-5.4/106-10-clk-qcom-Add-WCSSAON-reset.patch new file mode 100644 index 00000000000000..116795979b3a1c --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/106-10-clk-qcom-Add-WCSSAON-reset.patch @@ -0,0 +1,74 @@ +From patchwork Thu Jul 30 12:26:41 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Gokul Sriram Palanisamy +X-Patchwork-Id: 11692991 +Return-Path: +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 04D351744 + for ; + Thu, 30 Jul 2020 12:29:28 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id E11AE2082E + for ; + Thu, 30 Jul 2020 12:29:27 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1728211AbgG3M2n (ORCPT + ); + Thu, 30 Jul 2020 08:28:43 -0400 +Received: from alexa-out.qualcomm.com ([129.46.98.28]:26713 "EHLO + alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1726774AbgG3M2m (ORCPT + ); + Thu, 30 Jul 2020 08:28:42 -0400 +Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) + by alexa-out.qualcomm.com with ESMTP; 30 Jul 2020 05:28:42 -0700 +Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) + by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; + 30 Jul 2020 05:28:40 -0700 +Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) + by ironmsg02-blr.qualcomm.com with ESMTP; 30 Jul 2020 17:58:15 +0530 +Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) + id 902C6218A5; Thu, 30 Jul 2020 17:58:12 +0530 (IST) +From: Gokul Sriram Palanisamy +To: gokulsri@codeaurora.org, agross@kernel.org, + bjorn.andersson@linaro.org, david.brown@linaro.org, + devicetree@vger.kernel.org, jassisinghbrar@gmail.com, + linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, + linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, + mark.rutland@arm.com, mturquette@baylibre.com, + nprakash@codeaurora.org, ohad@wizery.com, robh+dt@kernel.org, + sboyd@kernel.org, sricharan@codeaurora.org +Subject: [PATCH v7 7/9] clk: qcom: Add WCSSAON reset +Date: Thu, 30 Jul 2020 17:56:41 +0530 +Message-Id: <1596112003-31663-8-git-send-email-gokulsri@codeaurora.org> +X-Mailer: git-send-email 2.7.4 +In-Reply-To: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +References: <1596112003-31663-1-git-send-email-gokulsri@codeaurora.org> +Sender: linux-arm-msm-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-arm-msm@vger.kernel.org + +Add WCSSAON reset required for Q6v5 on IPQ8074 SoC. + +Signed-off-by: Gokul Sriram Palanisamy +Signed-off-by: Sricharan R +Signed-off-by: Nikhil Prakash V +Acked-by: Stephen Boyd +--- + drivers/clk/qcom/gcc-ipq8074.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -4685,6 +4685,7 @@ static const struct qcom_reset_map gcc_i + [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, + [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, + [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, ++ [GCC_WCSSAON_RESET] = { 0x59010, 0 }, + }; + + static const struct of_device_id gcc_ipq8074_match_table[] = { diff --git a/target/linux/ipq807x/patches-5.4/106-11-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch b/target/linux/ipq807x/patches-5.4/106-11-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch new file mode 100644 index 00000000000000..dcd8e6a4d95fa7 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/106-11-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch @@ -0,0 +1,144 @@ +From cc3bb635a139e9967c43a5e4ba36ec6ff929cb8f Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Sun, 23 Aug 2020 00:00:44 +0200 +Subject: [PATCH] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC + +Enable remoteproc WCSS PIL driver with glink +and ssr subdevices. Also configures shared memory +and enables smp2p and mailboxes required for IPC. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 93 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -107,6 +107,11 @@ + reg = <0x0 0x4ab00000 0x0 0x100000>; + no-map; + }; ++ ++ q6_region: memory@4b000000 { ++ no-map; ++ reg = <0x0 0x4b000000 0x0 0x05f00000>; ++ }; + }; + + smem { +@@ -115,6 +120,32 @@ + hwlocks = <&tcsr_mutex 0>; + }; + ++ wcss: smp2p-wcss { ++ compatible = "qcom,smp2p"; ++ qcom,smem = <435>, <428>; ++ ++ interrupt-parent = <&intc>; ++ interrupts = <0 322 1>; ++ ++ mboxes = <&apcs_glb 9>; ++ ++ qcom,local-pid = <0>; ++ qcom,remote-pid = <1>; ++ ++ wcss_smp2p_out: master-kernel { ++ qcom,entry-name = "master-kernel"; ++ qcom,smp2p-feature-ssr-ack; ++ #qcom,smem-state-cells = <1>; ++ }; ++ ++ wcss_smp2p_in: slave-kernel { ++ qcom,entry-name = "slave-kernel"; ++ ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ }; ++ + soc: soc { + #address-cells = <0x1>; + #size-cells = <0x1>; +@@ -220,6 +251,11 @@ + reg = <0x1905000 0x8000>; + }; + ++ tcsr_q6: syscon@1945000 { ++ compatible = "syscon"; ++ reg = <0x01945000 0xe000>; ++ }; ++ + sdhc_1: sdhci@7824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x7824900 0x500>, <0x7824000 0x800>; +@@ -390,6 +426,13 @@ + ; + }; + ++ apcs_glb: mailbox@b111000 { ++ compatible = "qcom,ipq8074-apcs-apps-global"; ++ reg = <0x0b111000 0x1000>; ++ ++ #mbox-cells = <1>; ++ }; ++ + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; +@@ -449,6 +492,56 @@ + }; + }; + ++ q6v5_wcss: q6v5_wcss@cd00000 { ++ compatible = "qcom,ipq8074-wcss-pil"; ++ reg = <0x0cd00000 0x4040>, ++ <0x004ab000 0x20>; ++ reg-names = "qdsp6", ++ "rmb"; ++ qca,auto-restart; ++ qca,extended-intc; ++ interrupts-extended = <&intc 0 325 1>, ++ <&wcss_smp2p_in 0 0>, ++ <&wcss_smp2p_in 1 0>, ++ <&wcss_smp2p_in 2 0>, ++ <&wcss_smp2p_in 3 0>; ++ interrupt-names = "wdog", ++ "fatal", ++ "ready", ++ "handover", ++ "stop-ack"; ++ ++ resets = <&gcc GCC_WCSSAON_RESET>, ++ <&gcc GCC_WCSS_BCR>, ++ <&gcc GCC_WCSS_Q6_BCR>; ++ ++ reset-names = "wcss_aon_reset", ++ "wcss_reset", ++ "wcss_q6_reset"; ++ ++ clocks = <&gcc GCC_PRNG_AHB_CLK>; ++ clock-names = "prng"; ++ ++ qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>; ++ ++ qcom,smem-states = <&wcss_smp2p_out 0>, ++ <&wcss_smp2p_out 1>; ++ qcom,smem-state-names = "shutdown", ++ "stop"; ++ ++ memory-region = <&q6_region>; ++ ++ glink-edge { ++ interrupts = ; ++ qcom,remote-pid = <1>; ++ mboxes = <&apcs_glb 8>; ++ ++ rpm_requests { ++ qcom,glink-channels = "IPCRTR"; ++ }; ++ }; ++ }; ++ + pcie1: pci@10000000 { + compatible = "qcom,pcie-ipq8074"; + reg = <0x10000000 0xf1d diff --git a/target/linux/ipq807x/patches-5.4/107-arm64-dts-ipq8074-Add-WLAN-node.patch b/target/linux/ipq807x/patches-5.4/107-arm64-dts-ipq8074-Add-WLAN-node.patch new file mode 100644 index 00000000000000..772cccc4c775bb --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/107-arm64-dts-ipq8074-Add-WLAN-node.patch @@ -0,0 +1,138 @@ +From 9e4b14257e1b4dd418fe42badc637852c69f1e6b Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 24 Aug 2020 12:33:19 +0200 +Subject: [PATCH] arm64: dts: ipq8074: Add WLAN node + +IPQ8074 has 2 802.11ax radios supported by ath11k. +So lets add the node for ath11k. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 116 +++++++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 116 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -542,6 +542,122 @@ + }; + }; + ++ wifi0: wifi@c0000000 { ++ compatible = "qcom,ipq8074-wifi"; ++ reg = <0xc000000 0x2000000>; ++ interrupts = <0 320 1>, /* o_wcss_apps_intr[0] = */ ++ <0 319 1>, ++ <0 318 1>, ++ <0 317 1>, ++ <0 316 1>, ++ <0 315 1>, ++ <0 314 1>, ++ <0 311 1>, ++ <0 310 1>, ++ <0 411 1>, ++ <0 410 1>, ++ <0 40 1>, ++ <0 39 1>, ++ <0 302 1>, ++ <0 301 1>, ++ <0 37 1>, ++ <0 36 1>, ++ <0 296 1>, ++ <0 295 1>, ++ <0 294 1>, ++ <0 293 1>, ++ <0 292 1>, ++ <0 291 1>, ++ <0 290 1>, ++ <0 289 1>, ++ <0 288 1>, /* o_wcss_apps_intr[25] */ ++ ++ <0 239 1>, ++ <0 236 1>, ++ <0 235 1>, ++ <0 234 1>, ++ <0 233 1>, ++ <0 232 1>, ++ <0 231 1>, ++ <0 230 1>, ++ <0 229 1>, ++ <0 228 1>, ++ <0 224 1>, ++ <0 223 1>, ++ ++ <0 203 1>, ++ ++ <0 183 1>, ++ <0 180 1>, ++ <0 179 1>, ++ <0 178 1>, ++ <0 177 1>, ++ <0 176 1>, ++ ++ <0 163 1>, ++ <0 162 1>, ++ <0 160 1>, ++ <0 159 1>, ++ <0 158 1>, ++ <0 157 1>, ++ <0 156 1>; /* o_wcss_apps_intr[51] */ ++ ++ interrupt-names = "misc-pulse1", ++ "misc-latch", ++ "sw-exception", ++ "watchdog", ++ "ce0", ++ "ce1", ++ "ce2", ++ "ce3", ++ "ce4", ++ "ce5", ++ "ce6", ++ "ce7", ++ "ce8", ++ "ce9", ++ "ce10", ++ "ce11", ++ "host2wbm-desc-feed", ++ "host2reo-re-injection", ++ "host2reo-command", ++ "host2rxdma-monitor-ring3", ++ "host2rxdma-monitor-ring2", ++ "host2rxdma-monitor-ring1", ++ "reo2ost-exception", ++ "wbm2host-rx-release", ++ "reo2host-status", ++ "reo2host-destination-ring4", ++ "reo2host-destination-ring3", ++ "reo2host-destination-ring2", ++ "reo2host-destination-ring1", ++ "rxdma2host-monitor-destination-mac3", ++ "rxdma2host-monitor-destination-mac2", ++ "rxdma2host-monitor-destination-mac1", ++ "ppdu-end-interrupts-mac3", ++ "ppdu-end-interrupts-mac2", ++ "ppdu-end-interrupts-mac1", ++ "rxdma2host-monitor-status-ring-mac3", ++ "rxdma2host-monitor-status-ring-mac2", ++ "rxdma2host-monitor-status-ring-mac1", ++ "host2rxdma-host-buf-ring-mac3", ++ "host2rxdma-host-buf-ring-mac2", ++ "host2rxdma-host-buf-ring-mac1", ++ "rxdma2host-destination-ring-mac3", ++ "rxdma2host-destination-ring-mac2", ++ "rxdma2host-destination-ring-mac1", ++ "host2tcl-input-ring4", ++ "host2tcl-input-ring3", ++ "host2tcl-input-ring2", ++ "host2tcl-input-ring1", ++ "wbm2host-tx-completions-ring3", ++ "wbm2host-tx-completions-ring2", ++ "wbm2host-tx-completions-ring1", ++ "tcl2host-status-ring"; ++ qcom,rproc = <&q6v5_wcss>; ++ status = "disabled"; ++ }; ++ + pcie1: pci@10000000 { + compatible = "qcom,pcie-ipq8074"; + reg = <0x10000000 0xf1d diff --git a/target/linux/ipq807x/patches-5.4/901-arm64-qcom-dts-add-IPQ8074-dts.patch b/target/linux/ipq807x/patches-5.4/901-arm64-qcom-dts-add-IPQ8074-dts.patch new file mode 100644 index 00000000000000..0236ec00546810 --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/901-arm64-qcom-dts-add-IPQ8074-dts.patch @@ -0,0 +1,22 @@ +From 7dd07fff04e9333ccc660adea4cd51f7f322deb3 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 15 Jun 2020 23:28:00 +0200 +Subject: [PATCH] arm64: qcom: dts: add IPQ8074 dts + +Enable IPQ8074 dts to be built. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/Makefile | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/qcom/Makefile ++++ b/arch/arm64/boot/dts/qcom/Makefile +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb + dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq8071-ax3600.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb diff --git a/target/linux/ipq807x/patches-5.4/997-device_tree_cmdline.patch b/target/linux/ipq807x/patches-5.4/997-device_tree_cmdline.patch new file mode 100644 index 00000000000000..3cc032fdd24bdb --- /dev/null +++ b/target/linux/ipq807x/patches-5.4/997-device_tree_cmdline.patch @@ -0,0 +1,12 @@ +--- a/drivers/of/fdt.c ++++ b/drivers/of/fdt.c +@@ -1059,6 +1059,9 @@ int __init early_init_dt_scan_chosen(uns + p = of_get_flat_dt_prop(node, "bootargs", &l); + if (p != NULL && l > 0) + strlcpy(data, p, min(l, COMMAND_LINE_SIZE)); ++ p = of_get_flat_dt_prop(node, "bootargs-append", &l); ++ if (p != NULL && l > 0) ++ strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); + + /* + * CONFIG_CMDLINE is meant to be a default in case nothing else