From 82597c377c8a276cb03691b6eb7cb912d8436642 Mon Sep 17 00:00:00 2001
From: Daniel K Osawa <daniel.k.osawa@intel.com>
Date: Wed, 18 Oct 2017 01:36:31 +0200
Subject: [PATCH] Update diagnostic quick test to use correct AIT DRAM trained
 bits in BSR

Signed-off-by: Daniel K Osawa <daniel.k.osawa@intel.com>
---
 src/lib/diagnostic_quick.c | 36 +++++++++++++++++++++++++++---------
 src/lib/fis_types.h        |  4 ++++
 2 files changed, 31 insertions(+), 9 deletions(-)

diff --git a/src/lib/diagnostic_quick.c b/src/lib/diagnostic_quick.c
index d408266..88f5204 100644
--- a/src/lib/diagnostic_quick.c
+++ b/src/lib/diagnostic_quick.c
@@ -603,18 +603,36 @@ void check_ait_dram_not_ready(const unsigned long long bsr,
 		NVM_UINT32 *p_results)
 {
 	COMMON_LOG_ENTRY();
+	struct device_discovery discovery;
+	NVM_BOOL ait_dram_ready = 0;
+	NVM_UINT16 event_code = EVENT_CODE_DIAG_QUICK_AIT_DRAM_NOT_READY;
 
-	if (!BSR_H_AIT_DRAM_READY(bsr))
+	if (NVM_SUCCESS != nvm_get_device_discovery(device_uid, &discovery))
+	{
+		event_code = EVENT_CODE_DIAG_QUICK_UNKNOWN;
+	}
+	else
+	{
+		if (atof(discovery.fw_api_version) >= FIS_1_5)
+		{
+			ait_dram_ready = (BSR_H_AIT_DRAM_READY_1_5(bsr) == DEV_FW_BSR_AIT_DRAM_TRAINED_READY) ? 1 : 0;
+		}
+		else
+		{
+			ait_dram_ready = (BSR_H_AIT_DRAM_READY(bsr)) ? 1 : 0;
+		}
+	}
+	if (!ait_dram_ready)
 	{
 		store_event_by_parts(EVENT_TYPE_DIAG_QUICK,
-				EVENT_SEVERITY_CRITICAL,
-				EVENT_CODE_DIAG_QUICK_AIT_DRAM_NOT_READY,
-				device_uid,
-				1,
-				device_uid,
-				NULL,
-				NULL,
-				DIAGNOSTIC_RESULT_FAILED);
+			EVENT_SEVERITY_CRITICAL,
+			event_code,
+			device_uid,
+			1,
+			device_uid,
+			NULL,
+			NULL,
+			DIAGNOSTIC_RESULT_FAILED);
 		(*p_results)++;
 	}
 
diff --git a/src/lib/fis_types.h b/src/lib/fis_types.h
index 2c05ba9..5ab9a91 100644
--- a/src/lib/fis_types.h
+++ b/src/lib/fis_types.h
@@ -39,6 +39,7 @@
  * DEFINES
  * ****************************************************************************
  */
+#define FIS_1_5	1.5
 #define	DEV_SN_LEN		4  /* DIMM Serial Number buffer length */
 #define	DEV_PASSPHRASE_LEN	32  /* Length of a passphrase buffer */
 #define	DEV_BCD_DATE_LEN		4   /* Length of a BDC Formatted Date */
@@ -118,6 +119,8 @@
 #define DEV_FW_BSR_STALLED ((long long) 0x01 << 33)
 
 #define DEV_FW_BSR_AIT_DRAM_READY ((long long) 0x01 << 34)
+#define DEV_FW_BSR_AIT_DRAM_TRAINED_READY	0x3
+#define DEV_FW_BSR_AIT_DRAM_TRAINED_READY_OFFSET 27
 
 // firmware checkpoint codes and boot status register
 #define	BSR_IS_INVALID(bits) ((bits == ULLONG_MAX) || (bits == 0))
@@ -140,6 +143,7 @@
 #define	BSR_H_ASSERTION(bits)	(bits & DEV_FW_BSR_ASSERTION)
 #define	BSR_H_MI_STALLED(bits)	(bits & DEV_FW_BSR_STALLED)
 #define	BSR_H_AIT_DRAM_READY(bits)	(bits & DEV_FW_BSR_AIT_DRAM_READY)
+#define BSR_H_AIT_DRAM_READY_1_5(bits)	((bits >> DEV_FW_BSR_AIT_DRAM_TRAINED_READY_OFFSET) & 0x3)
 
 #define DSM_VENDOR_ERROR_SHIFT (0)
 #define DSM_MAILBOX_ERROR_SHIFT (16)