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max32625.svd
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max32625.svd
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<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
<vendor>Maxim Integrated</vendor> <!-- device vendor name -->
<vendorID>Maxim</vendorID> <!-- device vendor short name -->
<name>max32625</name> <!-- name of part-->
<series>ARMCM4</series> <!-- device series the device belongs to -->
<version>1.1</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
<description>The MAX32625/6 device family is designed for wearable and portable medical and
fitness applications. The devices contain an ARM Cortex-M4 processor with FPU, execute up to
96MHz and include a 10-bit ADC and a versatile set of on-chip peripherals. </description>
<licenseText> <!-- this license text will appear in header file. \n force line breaks --> Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.\n \n
Permission is hereby granted, free of charge, to any person obtaining a\n copy of this
software and associated documentation files (the "Software"),\n to deal in the Software
without restriction, including without limitation\n the rights to use, copy, modify, merge,
publish, distribute, sublicense,\n and/or sell copies of the Software, and to permit persons
to whom the\n Software is furnished to do so, subject to the following conditions:\n \n The
above copyright notice and this permission notice shall be included\n in all copies or
substantial portions of the Software.\n \n THE SOFTWARE IS PROVIDED "AS IS", WITHOUT
WARRANTY OF ANY KIND, EXPRESS\n OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.\n IN NO EVENT SHALL
MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES\n \n OR OTHER LIABILITY, WHETHER IN AN
ACTION OF CONTRACT, TORT OR OTHERWISE,\n ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR\n OTHER DEALINGS IN THE SOFTWARE.\n \n Except as contained in this
notice, the name of Maxim Integrated\n Products, Inc. shall not be used except as stated in
the Maxim Integrated\n Products, Inc. Branding Policy.\n \n The mere transfer of this
software does not imply any licenses\n of trade secrets, proprietary technology, copyrights,
patents,\n trademarks, maskwork rights, or any other form of intellectual\n property
whatsoever. Maxim Integrated Products, Inc. retains all\n ownership rights. </licenseText>
<cpu> <!-- details about the cpu embedded in the device -->
<name>CM4</name>
<revision>r1p0</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>true</fpuPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
and register that do not define "size" themselves -->
<access>read-write</access> <!-- default access permission for all subsequent registers -->
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to
0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
<peripherals>
<!-- SYSMAN:CLKMAN -->
<peripheral>
<name>CLKMAN</name>
<version>1.0</version>
<description>System Clock Manager</description>
<groupName>System Clock Manager</groupName>
<baseAddress>0x40000400</baseAddress>
<size>32</size>
<access>read-write</access>
<addressBlock>
<offset>0</offset>
<size>0x0400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CLKMAN</name>
<value>0</value>
<description>Clock Management IRQ</description>
</interrupt>
<registers>
<!-- CLK_CONFIG: System Clock Configuration -->
<register>
<name>CLK_CONFIG</name>
<description>System Clock Configuration</description>
<addressOffset>0x0000</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>crypto_enable</name>
<description>Cryptographic (TPU) Relaxation Oscillator Enable</description>
<enumeratedValues></enumeratedValues>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>crypto_stability_count</name>
<description>Crypto Oscillator Stability Select</description>
<enumeratedValues></enumeratedValues>
<bitRange>[7:4]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- CLK_CTRL: System Clock Controls -->
<register>
<name>CLK_CTRL</name>
<description>System Clock Controls</description>
<addressOffset>0x0004</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>system_source_select</name>
<description>System Clock Source Select</description>
<enumeratedValues></enumeratedValues>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>usb_clock_enable</name>
<description>USB Clock Enable</description>
<enumeratedValues></enumeratedValues>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>usb_clock_select</name>
<description>USB Clock Select</description>
<enumeratedValues></enumeratedValues>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
</field>
<field>
<name>crypto_clock_enable</name>
<description>Crypto Clock Enable</description>
<enumeratedValues></enumeratedValues>
<bitRange>[8:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>rtos_mode</name>
<description>Enable RTOS Mode for SysTick Timers</description>
<enumeratedValues></enumeratedValues>
<bitRange>[12:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>cpu_dynamic_clock</name>
<description>Enable CPU Dynamic Clock Gating</description>
<enumeratedValues></enumeratedValues>
<bitRange>[13:13]</bitRange>
<access>read-write</access>
</field>
<field>
<name>wdt0_clock_enable</name>
<description>Watchdog 0 Clock Enable</description>
<enumeratedValues></enumeratedValues>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>wdt0_clock_select</name>
<description>Watchdog 0 Clock Source Select</description>
<enumeratedValues></enumeratedValues>
<bitRange>[18:17]</bitRange>
<access>read-write</access>
</field>
<field>
<name>wdt1_clock_enable</name>
<description>Watchdog 1 Clock Enable</description>
<enumeratedValues></enumeratedValues>
<bitRange>[20:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>wdt1_clock_select</name>
<description>Watchdog 1 Clock Source Select</description>
<enumeratedValues></enumeratedValues>
<bitRange>[22:21]</bitRange>
<access>read-write</access>
</field>
<field>
<name>adc_clock_enable</name>
<description>ADC Clock Enable</description>
<enumeratedValues></enumeratedValues>
<bitRange>[24:24]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- INTFL: Interrupt Flags -->
<register>
<name>INTFL</name>
<description>Interrupt Flags</description>
<addressOffset>0x0008</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>crypto_stable</name>
<description>Crypto Oscillator Stable Interrupt Flag</description>
<enumeratedValues></enumeratedValues>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
<field>
<name>sys_ro_stable</name>
<description>System Oscillator Stable Interrupt Flag</description>
<enumeratedValues></enumeratedValues>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
</fields>
</register>
<!-- INTEN: Interrupt Enable/Disable Controls -->
<register>
<name>INTEN</name>
<description>Interrupt Enable/Disable Controls</description>
<addressOffset>0x000C</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>crypto_stable</name>
<description>Crypto Oscillator Stable Interrupt Enable</description>
<enumeratedValues></enumeratedValues>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>sys_ro_stable</name>
<description>System Oscillator Stable Interrupt Enable</description>
<enumeratedValues></enumeratedValues>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- TRIM_CALC: Trim Calculation Controls -->
<register>
<name>TRIM_CALC</name>
<description>Trim Calculation Controls</description>
<addressOffset>0x0010</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>trim_clk_sel</name>
<description>Trim Clock Select</description>
<enumeratedValues></enumeratedValues>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>trim_calc_start</name>
<description>Start Trim Calculation</description>
<enumeratedValues></enumeratedValues>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
</field>
<field>
<name>trim_calc_completed</name>
<description>Trim Calculation Completed</description>
<enumeratedValues></enumeratedValues>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
</field>
<field>
<name>trim_enable</name>
<description>Trim Logic Enable</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
</field>
<field>
<name>trim_calc_results</name>
<description>Trim Calculation Results</description>
<enumeratedValues></enumeratedValues>
<bitRange>[25:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<!-- I2C_TIMER_CTRL: I2C Timer Control -->
<register>
<name>I2C_TIMER_CTRL</name>
<description>I2C Timer Control</description>
<addressOffset>0x0014</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>i2c_1ms_timer_en</name>
<description>I2C 1ms Timer Enable</description>
<enumeratedValues></enumeratedValues>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- CM4_START_CLK_EN0: CM4 Start Clock on Interrupt Enable 0 -->
<register>
<name>CM4_START_CLK_EN0</name>
<description>CM4 Start Clock on Interrupt Enable 0</description>
<addressOffset>0x0018</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>ints</name>
<description>Interrupt Sources 0-31</description>
<enumeratedValues></enumeratedValues>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- CM4_START_CLK_EN1: CM4 Start Clock on Interrupt Enable 1 -->
<register>
<name>CM4_START_CLK_EN1</name>
<description>CM4 Start Clock on Interrupt Enable 1</description>
<addressOffset>0x001C</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>ints</name>
<description>Interrupt Sources 32-63</description>
<enumeratedValues></enumeratedValues>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- CM4_START_CLK_EN2: CM4 Start Clock on Interrupt Enable 2 -->
<register>
<name>CM4_START_CLK_EN2</name>
<description>CM4 Start Clock on Interrupt Enable 2</description>
<addressOffset>0x0020</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>ints</name>
<description>Interrupt Sources 95-64</description>
<enumeratedValues></enumeratedValues>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_0_CM4: Control Settings for CLK0 - Cortex M4 Clock -->
<register>
<name>SYS_CLK_CTRL_0_CM4</name>
<description>Control Settings for CLK0 - Cortex M4 Clock</description>
<addressOffset>0x0040</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>cm4_clk_scale</name>
<description>Control Settings for CLK0 - Cortex M4 Clock</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_1_SYNC: Control Settings for CLK1 - Synchronizer Clock -->
<register>
<name>SYS_CLK_CTRL_1_SYNC</name>
<description>Control Settings for CLK1 - Synchronizer Clock</description>
<addressOffset>0x0044</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>sync_clk_scale</name>
<description>Control Settings for CLK1 - Synchronizer Clock</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_2_SPIX: Control Settings for CLK2 - SPI XIP Clock -->
<register>
<name>SYS_CLK_CTRL_2_SPIX</name>
<description>Control Settings for CLK2 - SPI XIP Clock</description>
<addressOffset>0x0048</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>spix_clk_scale</name>
<description>Control Settings for CLK2 - SPI XIP Clock</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_3_PRNG: Control Settings for CLK3 - PRNG Clock -->
<register>
<name>SYS_CLK_CTRL_3_PRNG</name>
<description>Control Settings for CLK3 - PRNG Clock</description>
<addressOffset>0x004C</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>prng_clk_scale</name>
<description>Control Settings for CLK3 - PRNG Clock</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_4_WDT0: Control Settings for CLK4 - Watchdog Timer 0 -->
<register>
<name>SYS_CLK_CTRL_4_WDT0</name>
<description>Control Settings for CLK4 - Watchdog Timer 0</description>
<addressOffset>0x0050</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>watchdog0_clk_scale</name>
<description>Control Settings for CLK4 - Watchdog Timer 0</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_5_WDT1: Control Settings for CLK5 - Watchdog Timer 1 -->
<register>
<name>SYS_CLK_CTRL_5_WDT1</name>
<description>Control Settings for CLK5 - Watchdog Timer 1</description>
<addressOffset>0x0054</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>watchdog1_clk_scale</name>
<description>Control Settings for CLK5 - Watchdog Timer 1</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_6_GPIO: Control Settings for CLK6 - Clock for GPIO Ports -->
<register>
<name>SYS_CLK_CTRL_6_GPIO</name>
<description>Control Settings for CLK6 - Clock for GPIO Ports</description>
<addressOffset>0x0058</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>gpio_clk_scale</name>
<description>Control Settings for CLK6 - Clock for GPIO Ports</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_7_PT: Control Settings for CLK7 - Source Clock for All Pulse
Trains -->
<register>
<name>SYS_CLK_CTRL_7_PT</name>
<description>Control Settings for CLK7 - Source Clock for All Pulse Trains</description>
<addressOffset>0x005C</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>pulse_train_clk_scale</name>
<description>Control Settings for CLK7 - Source Clock for All Pulse
Trains</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_8_UART: Control Settings for CLK8 - Source Clock for All UARTs -->
<register>
<name>SYS_CLK_CTRL_8_UART</name>
<description>Control Settings for CLK8 - Source Clock for All UARTs</description>
<addressOffset>0x0060</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>uart_clk_scale</name>
<description>Control Settings for CLK8 - Source Clock for All UARTs</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_9_I2CM: Control Settings for CLK9 - Source Clock for All I2C
Masters -->
<register>
<name>SYS_CLK_CTRL_9_I2CM</name>
<description>Control Settings for CLK9 - Source Clock for All I2C Masters</description>
<addressOffset>0x0064</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>i2cm_clk_scale</name>
<description>Control Settings for CLK9 - Source Clock for All I2C
Masters</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_10_I2CS: Control Settings for CLK10 - Source Clock for I2C Slave -->
<register>
<name>SYS_CLK_CTRL_10_I2CS</name>
<description>Control Settings for CLK10 - Source Clock for I2C Slave</description>
<addressOffset>0x0068</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>i2cs_clk_scale</name>
<description>Control Settings for CLK10 - Source Clock for I2C Slave</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_11_SPI0: Control Settings for CLK11 - SPI Master 0 -->
<register>
<name>SYS_CLK_CTRL_11_SPI0</name>
<description>Control Settings for CLK11 - SPI Master 0</description>
<addressOffset>0x006C</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>spi0_clk_scale</name>
<description>Control Settings for CLK11 - SPI Master 0</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_12_SPI1: Control Settings for CLK12 - SPI Master 1 -->
<register>
<name>SYS_CLK_CTRL_12_SPI1</name>
<description>Control Settings for CLK12 - SPI Master 1</description>
<addressOffset>0x0070</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>spi1_clk_scale</name>
<description>Control Settings for CLK12 - SPI Master 1</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_13_SPI2: Control Settings for CLK13 - SPI Master 2 -->
<register>
<name>SYS_CLK_CTRL_13_SPI2</name>
<description>Control Settings for CLK13 - SPI Master 2</description>
<addressOffset>0x0074</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>spi2_clk_scale</name>
<description>Control Settings for CLK13 - SPI Master 2</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_14_SPIB: Control Settings for CLK14 - SPI Bridge Clock -->
<register>
<name>SYS_CLK_CTRL_14_SPIB</name>
<description>Control Settings for CLK14 - SPI Bridge Clock</description>
<addressOffset>0x0078</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>spib_clk_scale</name>
<description>Control Settings for CLK14 - SPI Bridge Clock</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_15_OWM: Control Settings for CLK15 - 1-Wire Master Clock -->
<register>
<name>SYS_CLK_CTRL_15_OWM</name>
<description>Control Settings for CLK15 - 1-Wire Master Clock</description>
<addressOffset>0x007C</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>owm_clk_scale</name>
<description>Control Settings for CLK15 - 1-Wire Master Clock</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- SYS_CLK_CTRL_16_SPIS: Control Settings for CLK16 - SPI Slave Clock -->
<register>
<name>SYS_CLK_CTRL_16_SPIS</name>
<description>Control Settings for CLK16 - SPI Slave Clock</description>
<addressOffset>0x0080</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>spis_clk_scale</name>
<description>Control Settings for CLK16 - SPI Slave Clock</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- CRYPT_CLK_CTRL_0_AES: Control Settings for Crypto Clock 0 - AES -->
<register>
<name>CRYPT_CLK_CTRL_0_AES</name>
<description>Control Settings for Crypto Clock 0 - AES</description>
<addressOffset>0x0100</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>aes_clk_scale</name>
<description>Control Settings for Crypto Clock 0 - AES</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- CRYPT_CLK_CTRL_1_MAA: Control Settings for Crypto Clock 1 - MAA -->
<register>
<name>CRYPT_CLK_CTRL_1_MAA</name>
<description>Control Settings for Crypto Clock 1 - MAA</description>
<addressOffset>0x0104</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>maa_clk_scale</name>
<description>Control Settings for Crypto Clock 1 - MAA</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- CRYPT_CLK_CTRL_2_PRNG: Control Settings for Crypto Clock 2 - PRNG -->
<register>
<name>CRYPT_CLK_CTRL_2_PRNG</name>
<description>Control Settings for Crypto Clock 2 - PRNG</description>
<addressOffset>0x0108</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>prng_clk_scale</name>
<description>Control Settings for Crypto Clock 2 - PRNG</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- CLK_GATE_CTRL0: Dynamic Clock Gating Control Register 0 -->
<register>
<name>CLK_GATE_CTRL0</name>
<description>Dynamic Clock Gating Control Register 0</description>
<addressOffset>0x0140</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>cm4_clk_gater</name>
<description>Clock Gating Control for CM4 CPU</description>
<enumeratedValues></enumeratedValues>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ahb32_clk_gater</name>
<description>Clock Gating Control for AHB32</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>icache_clk_gater</name>
<description>Clock Gating Control for Instruction Cache</description>
<enumeratedValues></enumeratedValues>
<bitRange>[5:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>flash_clk_gater</name>
<description>Clock Gating Control for Flash Memory</description>
<enumeratedValues></enumeratedValues>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>sram_clk_gater</name>
<description>Clock Gating Control for SRAM</description>
<enumeratedValues></enumeratedValues>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>apb_bridge_clk_gater</name>
<description>Clock Gating Control for AHB-to-APB Bridge</description>
<enumeratedValues></enumeratedValues>
<bitRange>[11:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>sysman_clk_gater</name>
<description>Clock Gating Control for CLKMAN, PWRMAN, and IOMAN</description>
<enumeratedValues></enumeratedValues>
<bitRange>[13:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ptp_clk_gater</name>
<description>Clock Gating Control for PTP Logic</description>
<enumeratedValues></enumeratedValues>
<bitRange>[15:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>ssb_mux_clk_gater</name>
<description>Clock Gating Control for SSB Mux</description>
<enumeratedValues></enumeratedValues>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>pad_clk_gater</name>
<description>Clock Gating Control for Pad Mode Filter</description>
<enumeratedValues></enumeratedValues>
<bitRange>[19:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>spix_clk_gater</name>
<description>Clock Gating Control for SPI XIP</description>
<enumeratedValues></enumeratedValues>
<bitRange>[21:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>pmu_clk_gater</name>
<description>Clock Gating Control for PMU</description>
<enumeratedValues></enumeratedValues>
<bitRange>[23:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>usb_clk_gater</name>
<description>Clock Gating Control for USB</description>
<enumeratedValues></enumeratedValues>
<bitRange>[25:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>crc_clk_gater</name>
<description>Clock Gating Control for CRC</description>
<enumeratedValues></enumeratedValues>
<bitRange>[27:26]</bitRange>
<access>read-write</access>
</field>
<field>
<name>tpu_clk_gater</name>
<description>Clock Gating Control for TPU</description>
<enumeratedValues></enumeratedValues>
<bitRange>[29:28]</bitRange>
<access>read-write</access>
</field>
<field>
<name>watchdog0_clk_gater</name>
<description>Clock Gating Control for Watchdog Timer 0</description>
<enumeratedValues></enumeratedValues>
<bitRange>[31:30]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- CLK_GATE_CTRL1: Dynamic Clock Gating Control Register 1 -->
<register>
<name>CLK_GATE_CTRL1</name>
<description>Dynamic Clock Gating Control Register 1</description>
<addressOffset>0x0144</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>watchdog1_clk_gater</name>
<description>Clock Gating Control for Watchdog Timer 1</description>
<enumeratedValues></enumeratedValues>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>gpio_clk_gater</name>
<description>Clock Gating Control for GPIO Ports</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>timer0_clk_gater</name>
<description>Clock Gating Control for Timer/Counter Module 0</description>
<enumeratedValues></enumeratedValues>
<bitRange>[5:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>timer1_clk_gater</name>
<description>Clock Gating Control for Timer/Counter Module 1</description>
<enumeratedValues></enumeratedValues>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>timer2_clk_gater</name>
<description>Clock Gating Control for Timer/Counter Module 2</description>
<enumeratedValues></enumeratedValues>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>timer3_clk_gater</name>
<description>Clock Gating Control for Timer/Counter Module 3</description>
<enumeratedValues></enumeratedValues>
<bitRange>[11:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>timer4_clk_gater</name>
<description>Clock Gating Control for Timer/Counter Module 4</description>
<enumeratedValues></enumeratedValues>
<bitRange>[13:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>timer5_clk_gater</name>
<description>Clock Gating Control for Timer/Counter Module 5</description>
<enumeratedValues></enumeratedValues>
<bitRange>[15:14]</bitRange>
<access>read-write</access>
</field>
<field>
<name>pulsetrain_clk_gater</name>
<description>Clock Gating Control for Pulse Train Generators</description>
<enumeratedValues></enumeratedValues>
<bitRange>[17:16]</bitRange>
<access>read-write</access>
</field>
<field>
<name>uart0_clk_gater</name>
<description>Clock Gating Control for UART 0</description>
<enumeratedValues></enumeratedValues>
<bitRange>[19:18]</bitRange>
<access>read-write</access>
</field>
<field>
<name>uart1_clk_gater</name>
<description>Clock Gating Control for UART 1</description>
<enumeratedValues></enumeratedValues>
<bitRange>[21:20]</bitRange>
<access>read-write</access>
</field>
<field>
<name>uart2_clk_gater</name>
<description>Clock Gating Control for UART 2</description>
<enumeratedValues></enumeratedValues>
<bitRange>[23:22]</bitRange>
<access>read-write</access>
</field>
<field>
<name>uart3_clk_gater</name>
<description>Clock Gating Control for UART 3</description>
<enumeratedValues></enumeratedValues>
<bitRange>[25:24]</bitRange>
<access>read-write</access>
</field>
<field>
<name>i2cm0_clk_gater</name>
<description>Clock Gating Control for I2C Master 0</description>
<enumeratedValues></enumeratedValues>
<bitRange>[27:26]</bitRange>
<access>read-write</access>
</field>
<field>
<name>i2cm1_clk_gater</name>
<description>Clock Gating Control for I2C Master 1</description>
<enumeratedValues></enumeratedValues>
<bitRange>[29:28]</bitRange>
<access>read-write</access>
</field>
<field>
<name>i2cm2_clk_gater</name>
<description>Clock Gating Control for I2C Master 2</description>
<enumeratedValues></enumeratedValues>
<bitRange>[31:30]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<!-- CLK_GATE_CTRL2: Dynamic Clock Gating Control Register 2 -->
<register>
<name>CLK_GATE_CTRL2</name>
<description>Dynamic Clock Gating Control Register 2</description>
<addressOffset>0x0148</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>i2cs_clk_gater</name>
<description>Clock Gating Control for I2C Slave</description>
<enumeratedValues></enumeratedValues>
<bitRange>[1:0]</bitRange>
<access>read-write</access>
</field>
<field>
<name>spi0_clk_gater</name>
<description>Clock Gating Control for SPI Master 0</description>
<enumeratedValues></enumeratedValues>
<bitRange>[3:2]</bitRange>
<access>read-write</access>
</field>
<field>
<name>spi1_clk_gater</name>
<description>Clock Gating Control for SPI Master 1</description>
<enumeratedValues></enumeratedValues>
<bitRange>[5:4]</bitRange>
<access>read-write</access>
</field>
<field>
<name>spi2_clk_gater</name>
<description>Clock Gating Control for SPI Master 2</description>
<enumeratedValues></enumeratedValues>
<bitRange>[7:6]</bitRange>
<access>read-write</access>
</field>
<field>
<name>spi_bridge_clk_gater</name>
<description>Clock Gating Control for SPI Bridge</description>
<enumeratedValues></enumeratedValues>
<bitRange>[9:8]</bitRange>
<access>read-write</access>
</field>
<field>
<name>owm_clk_gater</name>
<description>Clock Gating Control for 1-Wire Master (OWM)</description>
<enumeratedValues></enumeratedValues>
<bitRange>[11:10]</bitRange>
<access>read-write</access>
</field>
<field>
<name>adc_clk_gater</name>
<description>Clock Gating Control for ADC</description>
<enumeratedValues></enumeratedValues>
<bitRange>[13:12]</bitRange>
<access>read-write</access>
</field>
<field>
<name>spis_clk_gater</name>
<description>Clock Gating Control for SPI Slave</description>
<enumeratedValues></enumeratedValues>
<bitRange>[15:14]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>