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max32660.svd
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max32660.svd
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<?xml version='1.0' encoding='utf-8'?>
<device xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1"
xsi:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
<vendor>Maxim Integrated</vendor>
<vendorID>Maxim</vendorID>
<name>max32660</name>
<series>ARMCM4</series>
<version>1.0</version>
<description>MAX32660 32-bit ARM Cortex-M4 microcontroller with 96KB of system RAM and 256KB of
flash memory.</description>
<cpu>
<name>CM4</name>
<revision>r2p1</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>true</fpuPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>BBFC</name>
<description>Battery-Backed Function Control.</description>
<baseAddress>0x40005800</baseAddress>
<addressBlock>
<offset>0x00</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>BBFCR0</name>
<description>Function Control Register 0.</description>
<addressOffset>0x00</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>CKPDRV</name>
<description>Hyperbus CK Pad Driver Control.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CKNPDRV</name>
<description>Hyperbus CKN Pad Driver Control.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RDSDLLEN</name>
<description>Hyperbus RDS DLL Power Up Control.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>dis</name>
<description>Disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>en</name>
<description>Enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<!--BBFC
Battery-Backed Function Control.-->
<peripheral>
<name>BBSIR</name>
<description>Battery-Backed Registers.</description>
<baseAddress>0x40005400</baseAddress>
<addressBlock>
<offset>0x00</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>rsv0</name>
<description>RFU</description>
<addressOffset>0x00</addressOffset>
</register>
<register>
<name>BB_SIR2</name>
<description>System Init. Configuration Register 2.</description>
<addressOffset>0x08</addressOffset>
<access>read-only</access>
</register>
<register>
<name>BB_SIR3</name>
<description>System Init. Configuration Register 3.</description>
<addressOffset>0x0C</addressOffset>
<access>read-only</access>
</register>
</registers>
</peripheral>
<!--BBSIR
Battery-Backed Registers.-->
<peripheral>
<name>GPDMA</name>
<description>DMA Controller Fully programmable, chaining capable DMA channels.</description>
<baseAddress>0x40028000</baseAddress>
<size>32</size>
<addressBlock>
<offset>0x00</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA0</name>
<value>28</value>
</interrupt>
<interrupt>
<name>DMA1</name>
<value>29</value>
</interrupt>
<interrupt>
<name>DMA2</name>
<value>30</value>
</interrupt>
<interrupt>
<name>DMA3</name>
<value>31</value>
</interrupt>
<interrupt>
<name>DMA4</name>
<value>68</value>
</interrupt>
<interrupt>
<name>DMA5</name>
<value>69</value>
</interrupt>
<interrupt>
<name>DMA6</name>
<value>70</value>
</interrupt>
<interrupt>
<name>DMA7</name>
<value>71</value>
</interrupt>
<interrupt>
<name>DMA8</name>
<value>72</value>
</interrupt>
<interrupt>
<name>DMA9</name>
<value>73</value>
</interrupt>
<interrupt>
<name>DMA10</name>
<value>74</value>
</interrupt>
<interrupt>
<name>DMA11</name>
<value>75</value>
</interrupt>
<interrupt>
<name>DMA12</name>
<value>76</value>
</interrupt>
<interrupt>
<name>DMA13</name>
<value>77</value>
</interrupt>
<interrupt>
<name>DMA14</name>
<value>78</value>
</interrupt>
<interrupt>
<name>DMA15</name>
<value>79</value>
</interrupt>
<registers>
<register>
<name>CN</name>
<description>DMA Control Register.</description>
<addressOffset>0x000</addressOffset>
<fields>
<field>
<name>CH0_IEN</name>
<description>Channel 0 Interrupt Enable.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>dis</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>en</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field derivedFrom="CH0_IEN">
<name>CH1_IEN</name>
<description>Channel 1 Interrupt Enable.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="CH0_IEN">
<name>CH2_IEN</name>
<description>Channel 2 Interrupt Enable.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="CH0_IEN">
<name>CH3_IEN</name>
<description>Channel 3 Interrupt Enable.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INTR</name>
<description>DMA Interrupt Register.</description>
<addressOffset>0x004</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>CH0_IPEND</name>
<description>Channel Interrupt. To clear an interrupt, all active
interrupt bits of the DMA_ST must be cleared. The interrupt bits are
set only if their corresponding interrupt enable bits are set in
DMA_CN.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>ch_ipend_enum</name>
<enumeratedValue>
<name>inactive</name>
<description>No interrupt is pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>pending</name>
<description>An interrupt is pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field derivedFrom="CH0_IPEND">
<name>CH1_IPEND</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="CH0_IPEND">
<name>CH2_IPEND</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="CH0_IPEND">
<name>CH3_IPEND</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<cluster>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
<name>CH[%s]</name>
<description>DMA Channel registers.</description>
<headerStructName>dma_ch</headerStructName>
<addressOffset>0x100</addressOffset>
<access>read-write</access>
<register>
<name>CFG</name>
<description>DMA Channel Configuration Register.</description>
<addressOffset>0x100</addressOffset>
<fields>
<field>
<name>CHEN</name>
<description>Channel Enable. This bit is automatically cleared when
DMA_ST.CH_ST changes from 1 to 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>dis</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>en</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RLDEN</name>
<description>Reload Enable. Setting this bit to 1 enables DMA_SRC,
DMA_DST and DMA_CNT to be reloaded with their corresponding
reload registers upon count-to-zero. This bit is also writeable
in the Count Reload Register. Refer to the description on Buffer
Chaining for use of this bit. If buffer chaining is not used
this bit must be written with a 0. This bit should be set after
the reload registers have been programmed.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>dis</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>en</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PRI</name>
<description>DMA Priority.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>high</name>
<description>Highest Priority.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>medHigh</name>
<description>Medium High Priority.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>medLow</name>
<description>Medium Low Priority.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>low</name>
<description>Lowest Priority.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REQSEL</name>
<description>Request Select. Select DMA request line for this
channel. If memory-to-memory is selected, the channel operates
as if the request is always active.</description>
<bitOffset>4</bitOffset>
<bitWidth>6</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>MEMTOMEM</name>
<description>Memory To Memory</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI0RX</name>
<description>SPI0 RX</description>
<value>0x01</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI1RX</name>
<description>SPI1 RX</description>
<value>0x02</value>
</enumeratedValue>
<enumeratedValue>
<name>UART0RX</name>
<description>UART0 RX</description>
<value>0x04</value>
</enumeratedValue>
<enumeratedValue>
<name>UART1RX</name>
<description>UART1 RX</description>
<value>0x05</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C0RX</name>
<description>I2C0 RX</description>
<value>0x07</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C1RX</name>
<description>I2C1 RX</description>
<value>0x08</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI0TX</name>
<description>SPI0 TX</description>
<value>0x21</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI1TX</name>
<description>SPI1 TX</description>
<value>0x22</value>
</enumeratedValue>
<enumeratedValue>
<name>UART0TX</name>
<description>UART0 TX</description>
<value>0x24</value>
</enumeratedValue>
<enumeratedValue>
<name>UART1TX</name>
<description>UART1 TX</description>
<value>0x25</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C0TX</name>
<description>I2C0 TX</description>
<value>0x27</value>
</enumeratedValue>
<enumeratedValue>
<name>I2C1TX</name>
<description>I2C1 TX</description>
<value>0x28</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>REQWAIT</name>
<description>Request Wait Enable. When enabled, delay timer start
until DMA request transitions from active to inactive.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>dis</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>en</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TOSEL</name>
<description>Time-Out Select. Selects the number of prescale clocks
seen by the channel timer before a time-out conditions is
generated for this channel. Important note: since the prescaler
runs independent of the individual channel timers, the actual
number of Pre-Scale clock edges seen has a margin of error equal
to a single Pre-Scale clock.</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>to4</name>
<description>Timeout of 3 to 4 prescale clocks.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>to8</name>
<description>Timeout of 7 to 8 prescale clocks.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>to16</name>
<description>Timeout of 15 to 16 prescale clocks.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>to32</name>
<description>Timeout of 31 to 32 prescale clocks.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>to64</name>
<description>Timeout of 63 to 64 prescale clocks.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>to128</name>
<description>Timeout of 127 to 128 prescale clocks.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>to256</name>
<description>Timeout of 255 to 256 prescale clocks.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>to512</name>
<description>Timeout of 511 to 512 prescale clocks.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PSSEL</name>
<description>Pre-Scale Select. Selects the Pre-Scale divider for
timer clock input.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>dis</name>
<description>Disable timer.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>div256</name>
<description>hclk / 256.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>div64k</name>
<description>hclk / 64k.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>div16M</name>
<description>hclk / 16M.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRCWD</name>
<description>Source Width. In most cases, this will be the data
width of each AHB transactions. However, the width will be
reduced in the cases where DMA_CNT indicates a smaller value.</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>byte</name>
<description>Byte.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>halfWord</name>
<description>Halfword.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>word</name>
<description>Word.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SRCINC</name>
<description>Source Increment Enable. This bit enables DMA_SRC
increment upon every AHB transaction. This bit is forced to 0
for DMA receive from peripherals.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>dis</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>en</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSTWD</name>
<description>Destination Width. Indicates the width of the each AHB
transactions to the destination peripheral or memory. (The
actual width may be less than this if there are insufficient
bytes in the DMA FIFO for the full width).</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>byte</name>
<description>Byte.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>halfWord</name>
<description>Halfword.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>word</name>
<description>Word.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DSTINC</name>
<description>Destination Increment Enable. This bit enables DMA_DST
increment upon every AHB transaction. This bit is forced to 0
for DMA transmit to peripherals.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>dis</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>en</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BRST</name>
<description>Burst Size. The number of bytes to be transferred into
and out of the DMA FIFO in a single burst. Burst size equals 1 +
value stored in this field.</description>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>CHDIEN</name>
<description>Channel Disable Interrupt Enable. When enabled, the
IPEND will be set to 1 whenever CH_ST changes from 1 to 0.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>dis</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>en</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTZIEN</name>
<description>Count-to-zero Interrupts Enable. When enabled, the
IPEND will be set to 1 whenever a count-to-zero event occurs.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>dis</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>en</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ST</name>
<description>DMA Channel Status Register.</description>
<addressOffset>0x104</addressOffset>
<fields>
<field>
<name>CH_ST</name>
<description>Channel Status. This bit is used to indicate to the
programmer when it is safe to change the configuration, address,
and count registers for the channel. Whenever this bit is
cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if
not cleared already).</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>dis</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>en</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>IPEND</name>
<description>Channel Interrupt.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>inactive</name>
<description>No interrupt is pending.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>pending</name>
<description>An interrupt is pending.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CTZ_ST</name>
<description>Count-to-Zero (CTZ) Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<enumeratedValues>
<name>ctz_st_enum_rd</name>
<usage>read</usage>
<enumeratedValue>
<name>noEvent</name>
<description>The event has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>occurred</name>
<description>The event has occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<enumeratedValues>
<name>ctz_st_enum_wr</name>
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
<description>Clears the interrupt flag</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RLD_ST</name>
<description>Reload Status.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<enumeratedValues>
<usage>read</usage>
<enumeratedValue>
<name>noEvent</name>
<description>The event has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>occurred</name>
<description>The event has occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<enumeratedValues>
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
<description>Clears the interrupt flag</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BUS_ERR</name>
<description>Bus Error. Indicates that an AHB abort was received and
the channel has been disabled.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<enumeratedValues>
<usage>read</usage>
<enumeratedValue>
<name>noEvent</name>
<description>The event has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>occurred</name>
<description>The event has occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<enumeratedValues>
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
<description>Clears the interrupt flag</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TO_ST</name>
<description>Time-Out Status.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
<enumeratedValues>
<usage>read</usage>
<enumeratedValue>
<name>noEvent</name>
<description>The event has not occurred.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>occurred</name>
<description>The event has occurred.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<enumeratedValues>
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
<description>Clears the interrupt flag</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SRC</name>
<description>Source Device Address. If SRCINC=1, the counter bits are
incremented by 1,2, or 4, depending on the data width of each AHB cycle.
For peripheral transfers, some or all of the actual address bits are
fixed. If SRCINC=0, this register remains constant. In the case where a
count-to-zero condition occurs while RLDEN=1, the register is reloaded
with the contents of DMA_SRC_RLD.</description>
<addressOffset>0x108</addressOffset>
<fields>
<field>
<name>ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DST</name>
<description>Destination Device Address. For peripheral transfers, some or
all of the actual address bits are fixed. If DSTINC=1, this register is
incremented on every AHB write out of the DMA FIFO. They are incremented
by 1, 2, or 4, depending on the data width of each AHB cycle. In the
case where a count-to-zero condition occurs while RLDEN=1, the register
is reloaded with DMA_DST_RLD.</description>
<addressOffset>0x10C</addressOffset>
<fields>
<field>
<name>ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<description>DMA Counter. The user loads this register with the number of
bytes to transfer. This counter decreases on every AHB cycle into the
DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width
of each AHB cycle. When the counter reaches 0, a count-to-zero condition
is triggered.</description>
<addressOffset>0x110</addressOffset>
<fields>
<field>
<name>CNT</name>
<description>DMA Counter.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>SRC_RLD</name>
<description>Source Address Reload Value. The value of this register is
loaded into DMA0_SRC upon a count-to-zero condition.</description>
<addressOffset>0x114</addressOffset>
<fields>
<field>
<name>SRC_RLD</name>
<description>Source Address Reload Value.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
</field>
</fields>
</register>
<register>
<name>DST_RLD</name>
<description>Destination Address Reload Value. The value of this register is
loaded into DMA0_DST upon a count-to-zero condition.</description>
<addressOffset>0x118</addressOffset>
<fields>
<field>
<name>DST_RLD</name>
<description>Destination Address Reload Value.</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT_RLD</name>
<description>DMA Channel Count Reload Register.</description>
<addressOffset>0x11C</addressOffset>
<fields>
<field>
<name>CNT_RLD</name>
<description>Count Reload Value. The value of this register is
loaded into DMA0_CNT upon a count-to-zero condition.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
<field>
<name>RLDEN</name>
<description>Reload Enable. This bit should be set after the address
reload registers have been programmed. This bit is automatically
cleared to 0 when reload occurs.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>dis</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>en</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</cluster>
</registers>
</peripheral>
<!--DMA
DMA Controller Fully programmable, chaining capable DMA channels.-->
<peripheral>
<name>FLC</name>
<description>Flash Memory Control.</description>
<prependToName>FLSH_</prependToName>
<baseAddress>0x40029000</baseAddress>
<addressBlock>
<offset>0x00</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>Flash_Controller</name>
<description>Flash Controller interrupt.</description>
<value>23</value>
</interrupt>
<registers>
<register>
<name>ADDR</name>
<description>Flash Write Address.</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>ADDR</name>
<description>Address for next operation.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLKDIV</name>
<description>Flash Clock Divide. The clock (PLL0) is divided by this value to
generate a 1 MHz clock for Flash controller.</description>
<addressOffset>0x04</addressOffset>
<resetValue>0x00000064</resetValue>
<fields>
<field>
<name>CLKDIV</name>
<description>Flash Clock Divide. The clock is divided by this value to
generate a 1MHz clock for flash controller.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CN</name>