-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathvivado_batch.tcl
executable file
·86 lines (59 loc) · 2.64 KB
/
vivado_batch.tcl
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
# Simple TCL script for Vivado builds
# Jamieson Olsen <[email protected]>
#
# vivado -mode tcl -source vivado_batch.tcl
# general setup stuff...
set_param general.maxThreads 4
set outputDir ./output
file mkdir $outputDir
set_part xc7k325t-ffg900-2
# load the sources...
read_vhdl ./top_level.vhd
# Load IP core container file should be *.XCIX container
# which includes the output products. XCIX does not
# require synth_ip and generate_target commands
#read_ip ../src/ip/gig_ethernet_pcs_pma_0.xcix
# Load IP module as *.xci
#read_ip ../src/ip/gig_ethernet_pcs_pma_0.xci
#set_property target_language VHDL [current_project]
#generate_target all [get_files ../src/ip/gig_ethernet_pcs_pma_0.xci]
# Load general constraints...
read_xdc -verbose ./constraints.xdc
# get the git SHA hash (commit id) and pass it to the top level source
# keep it simple just use the short form of the long SHA-1 number.
# Note this is a 7 character HEX string, e.g. 28 bits, but Vivado requires
# this number to be in Verilog notation, even if the top level source is VHDL.
set git_sha [exec git rev-parse --short=7 HEAD]
set v_git_sha "28'h$git_sha"
puts "INFO: passing git commit number $v_git_sha to top level generic"
# synth design...
synth_design -top top_level -generic version=$v_git_sha
report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
report_power -file $outputDir/post_synth_power.rpt
report_utilization -file $outputDir/post_synth_util.rpt
# place design...
opt_design
place_design
phys_opt_design -directive AggressiveFanoutOpt
write_checkpoint -force $outputDir/post_place
report_timing_summary -file $outputDir/post_place_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_place_timing.rpt
# route...
route_design
write_checkpoint -force $outputDir/post_route
# generate reports...
report_timing_summary -file $outputDir/post_route_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt
report_clock_utilization -file $outputDir/clock_util.rpt
report_utilization -file $outputDir/post_route_util.rpt
report_power -file $outputDir/post_route_power.rpt
report_drc -file $outputDir/post_imp_drc.rpt
report_io -file $outputDir/io.rpt
# write out VHDL and constraints for timing sim...
#write_vhdl -force $outputDir/vivpram_impl_netlist.v
#write_xdc -no_fixed_only -force $outputDir/bft_impl.xdc
# generate bitstream...
write_bitstream -force $outputDir/vivado_test.bit
# write out ILA debug probes file
# write_debug_probes -force $outputDir/probes.ltx
exit