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Initial support for RISCV vector extension #1716

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Initial support for RISCV vector extension #1716

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b17e2b3
[riscv] Add support for RISC-V vector extension in arch
ita-sc Aug 16, 2024
d4092f5
[riscv] Add support for unit.internals testing
ita-sc Aug 16, 2024
666cbfe
[riscv] Add support unit.core testing
ita-sc Aug 16, 2024
dc3687e
[riscv] Fix test unit.memory.load.tuple for RISC-V
ita-sc Aug 17, 2024
6b38369
[riscv] Impelement right variant of first_true
ita-sc Aug 16, 2024
707f5f3
[riscv] Add support for unit.api tests for RISC-V
ita-sc Aug 17, 2024
979fa91
[riscv] Add support for testing RISC-V for unit.algo testsuite
ita-sc Aug 17, 2024
af4327d
[riscv] Optimizations for RISC-V
ita-sc Aug 17, 2024
db76657
Merge branch 'jfalcou:main' into ita-sc/riscv-backend
ita-sc Aug 22, 2024
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19 changes: 19 additions & 0 deletions cmake/toolchain/clang.rvv128.cmake
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Original file line number Diff line number Diff line change
@@ -0,0 +1,19 @@
##==================================================================================================
## EVE - Expressive Vector Engine
## Copyright : EVE Project Contributors
## SPDX-License-Identifier: BSL-1.0
##==================================================================================================
set(CMAKE_SYSTEM_NAME Generic)
set(CMAKE_SYSTEM_PROCESSOR riscv64)

set(CMAKE_C_COMPILER clang )
set(CMAKE_CXX_COMPILER clang++ )


if(NOT DEFINED ENV{RISCV_GCC})
message(FATAL_ERROR "expected to have RISCV_GCC in environment")
endif()

set(CMAKE_CXX_FLAGS "-O3 -march=rv64gcv -std=c++20 -mrvv-vector-bits=128 --sysroot=$ENV{RISCV_GCC}/sysroot --gcc-toolchain=$ENV{RISCV_GCC} --static --target=riscv64-unknown-linux-gnu ${EVE_OPTIONS}" )

set(CMAKE_CROSSCOMPILING_CMD ${PROJECT_SOURCE_DIR}/cmake/toolchain/run_rvv128.sh )
8 changes: 8 additions & 0 deletions cmake/toolchain/run_rvv128.sh
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Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
##==================================================================================================
## EVE - Expressive Vector Engine
## Copyright : EVE Project Contributors
## SPDX-License-Identifier: BSL-1.0
##==================================================================================================
#!/bin/sh

qemu-riscv64 --cpu rv64,v=true,vlen=128 $@
1 change: 1 addition & 0 deletions include/eve/arch/abi_of.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,7 @@ namespace eve
else return emulated_{};
}
}
else if constexpr( spy::simd_instruction_set == spy::rvv_ ) { return riscv_rvv_dyn_ {}; }
else
{
return emulated_{};
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9 changes: 5 additions & 4 deletions include/eve/arch/as_register.hpp
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Expand Up @@ -10,9 +10,10 @@
#include <eve/arch/cpu/as_register.hpp>

#if !defined(EVE_NO_SIMD)
#include <eve/arch/x86/as_register.hpp>
#include <eve/arch/ppc/as_register.hpp>
#include <eve/arch/arm/sve/as_register.hpp>
#include <eve/arch/arm/neon/as_register.hpp>
# include <eve/arch/arm/neon/as_register.hpp>
# include <eve/arch/arm/sve/as_register.hpp>
# include <eve/arch/ppc/as_register.hpp>
# include <eve/arch/riscv/as_register.hpp>
# include <eve/arch/x86/as_register.hpp>
#endif

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