-
Notifications
You must be signed in to change notification settings - Fork 0
/
emconfig.json
153 lines (153 loc) · 7.79 KB
/
emconfig.json
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
{
"Comment": "This file is auto-generated by the tool. Do not modify",
"Version": {
"FileVersion": "2.0",
"ToolVersion": "2020.2"
},
"Platform": {
"Boards": [
{
"Devices": [
{
"Name": "xilinx_u280_xdma_201920_3",
"DdrBanks": [
{
"Name": "dynamic_region_memory_subsystem_memory_ddr4_mem00",
"Type": "ddr4",
"Size": "16GB",
"AXI_ARBITRATION_SCHEME": "RD_PRI_REG",
"BURST_LENGTH": "8",
"C0": {
"APP_ADDR_WIDTH": "31",
"APP_DATA_WIDTH": "512",
"ControllerType": "DDR4_SDRAM",
"DDR4_ADDR_WIDTH": "17",
"DDR4_AXI_ADDR_WIDTH": "34",
"DDR4_AXI_DATA_WIDTH": "512",
"DDR4_AXI_ID_WIDTH": "1",
"DDR4_AutoPrecharge": "false",
"DDR4_AxiNarrowBurst": "false",
"DDR4_BANK_GROUP_WIDTH": "2",
"DDR4_BANK_WIDTH": "2",
"DDR4_CL": "0",
"DDR4_COLUMN_WIDTH": "10",
"DDR4_CWL": "0",
"DDR4_Mem_Add_Map": "ROW_COLUMN_BANK_INTLV",
"DDR4_Ordering": "Normal",
"DDR4_RANK_WIDTH": "1",
"DDR4_ROW_WIDTH": "17",
"DDR4_tCK": "833",
"DDR4_tCKE": "0",
"DDR4_tFAW": "16",
"DDR4_tMRD": "2",
"DDR4_tRAS": "39",
"DDR4_tRCD": "17",
"DDR4_tREFI": "9363",
"DDR4_tRFC": "421",
"DDR4_tRP": "17",
"DDR4_tRRD_L": "6",
"DDR4_tRRD_S": "4",
"DDR4_tRTP": "10",
"DDR4_tWR": "19",
"DDR4_tWTR_L": "10",
"DDR4_tWTR_S": "4",
"DDR4_tXPR": "109",
"DDR4_tZQCS": "128",
"DDR4_tZQI": "0",
"DDR4_tZQINIT": "256"
},
"CAS_LATENCY": "17",
"CAS_WRITE_LATENCY": "12",
"DATA_WIDTH": "72",
"MEMORY_PART": "MTA18ASF2G72PZ-2G3",
"MEM_ADDR_MAP": "ROW_COLUMN_BANK_INTLV",
"TIMEPERIOD_PS": "833"
},
{
"Name": "dynamic_region_memory_subsystem_memory_ddr4_mem01",
"Type": "ddr4",
"Size": "16GB",
"AXI_ARBITRATION_SCHEME": "RD_PRI_REG",
"BURST_LENGTH": "8",
"C0": {
"APP_ADDR_WIDTH": "31",
"APP_DATA_WIDTH": "512",
"ControllerType": "DDR4_SDRAM",
"DDR4_ADDR_WIDTH": "17",
"DDR4_AXI_ADDR_WIDTH": "34",
"DDR4_AXI_DATA_WIDTH": "512",
"DDR4_AXI_ID_WIDTH": "1",
"DDR4_AutoPrecharge": "false",
"DDR4_AxiNarrowBurst": "false",
"DDR4_BANK_GROUP_WIDTH": "2",
"DDR4_BANK_WIDTH": "2",
"DDR4_CL": "0",
"DDR4_COLUMN_WIDTH": "10",
"DDR4_CWL": "0",
"DDR4_Mem_Add_Map": "ROW_COLUMN_BANK_INTLV",
"DDR4_Ordering": "Normal",
"DDR4_RANK_WIDTH": "1",
"DDR4_ROW_WIDTH": "17",
"DDR4_tCK": "833",
"DDR4_tCKE": "0",
"DDR4_tFAW": "16",
"DDR4_tMRD": "2",
"DDR4_tRAS": "39",
"DDR4_tRCD": "17",
"DDR4_tREFI": "9363",
"DDR4_tRFC": "421",
"DDR4_tRP": "17",
"DDR4_tRRD_L": "6",
"DDR4_tRRD_S": "4",
"DDR4_tRTP": "10",
"DDR4_tWR": "19",
"DDR4_tWTR_L": "10",
"DDR4_tWTR_S": "4",
"DDR4_tXPR": "109",
"DDR4_tZQCS": "128",
"DDR4_tZQI": "0",
"DDR4_tZQINIT": "256"
},
"CAS_LATENCY": "17",
"CAS_WRITE_LATENCY": "12",
"DATA_WIDTH": "72",
"MEMORY_PART": "MTA18ASF2G72PZ-2G3",
"MEM_ADDR_MAP": "ROW_COLUMN_BANK_INTLV",
"TIMEPERIOD_PS": "833"
}
],
"FeatureRom": {
"Major_Version": "10",
"Minor_Version": "1",
"Vivado_Build_Id": "2742762",
"Ip_Build_Id": "2719198",
"Time_Since_Epoch": "1579649056",
"Fpga_Part_Name": "xcu280-fsvh2892-2L-e",
"Vbnv_Name": "xilinx_u280_xdma_201920_3",
"Ddr_Channel_Count": "2",
"Ddr_Channel_Size": "16",
"Dr_Base_Address": "0",
"Feature_Bitmap": "197133",
"Uuid": "f2b82d53-372f-45a4-bbe9-3d1c980216da",
"Unified_Platform": "enabled",
"Aurora_Link": "disabled",
"Board_Mgmt": "enabled",
"Board_Scheduler": "enabled",
"Prom_Type": "0x0",
"Debug_Type": "0x2",
"Peer_To_Peer": "enabled",
"Cdma_Size": "4",
"Cdma_Base_Address0": "0",
"Cdma_Base_Address1": "0",
"Cdma_Base_Address2": "0",
"Cdma_Base_Address3": "0"
}
}
],
"NumBoards": "1"
}
],
"UnifiedPlatform": "true",
"ExpandedPR": "false"
}
}