Sparcv8Monocicle.syr

Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
 
--> Reading design: Sparcv8Monocicle.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "Sparcv8Monocicle.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "Sparcv8Monocicle"
Output Format                      : NGC
Target Device                      : xc3s100e-4-vq100

---- Source Options
Top Module Name                    : Sparcv8Monocicle
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/SEUDisp30.vhd" in Library work.
Architecture behavioral of Entity seudisp30 is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/SEUDisp22.vhd" in Library work.
Architecture behavioral of Entity seudisp22 is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/MuxPC.vhd" in Library work.
Architecture behavioral of Entity muxpc is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/MuxNextRD.vhd" in Library work.
Architecture behavioral of Entity muxnextrd is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/MuxDWR.vhd" in Library work.
Architecture behavioral of Entity muxdwr is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/DM.vhd" in Library work.
Architecture arqdatamemory of Entity datamemory is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/windows_manager.vhd" in Library work.
Architecture behavioral of Entity windows_manager is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/psr.vhd" in Library work.
Architecture psrarq of Entity psr is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/psr_modifier.vhd" in Library work.
Architecture psr_modarq of Entity psr_modifier is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/sum32b.vhd" in Library work.
Architecture arqsum32 of Entity sum32b is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/alu.vhd" in Library work.
Architecture arqalu of Entity alu is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/control_unit.vhd" in Library work.
Architecture arq_unidadcontrol of Entity control_unit is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/instruction_memory.vhd" in Library work.
Architecture arqinstructionmemory of Entity instructionmemory is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/mux32b.vhd" in Library work.
Architecture arqmux32b of Entity mux32b is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/pc.vhd" in Library work.
Architecture arqpc of Entity pc is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/register_file.vhd" in Library work.
Architecture arqregfile of Entity register_file is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/sign_ext_unit.vhd" in Library work.
Architecture arqsignext of Entity sign_ext_unit is up to date.
Compiling vhdl file "C:/Users/Personal/Downloads/sparcv8-monocicle-master/Sparcv8Monocicle.vhd" in Library work.
Architecture behavioral of Entity sparcv8monocicle is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <Sparcv8Monocicle> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <SEUDisp30> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <SEUDisp22> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <MuxPC> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <MuxNextRD> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <MuxDWR> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <DataMemory> in library <work> (architecture <arqdatamemory>).

Analyzing hierarchy for entity <windows_manager> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <psr> in library <work> (architecture <psrarq>).

Analyzing hierarchy for entity <psr_modifier> in library <work> (architecture <psr_modarq>).

Analyzing hierarchy for entity <sum32b> in library <work> (architecture <arqsum32>).

Analyzing hierarchy for entity <alu> in library <work> (architecture <arqalu>).

Analyzing hierarchy for entity <control_unit> in library <work> (architecture <arq_unidadcontrol>).

Analyzing hierarchy for entity <instructionMemory> in library <work> (architecture <arqinstructionmemory>).

Analyzing hierarchy for entity <mux32b> in library <work> (architecture <arqmux32b>).

Analyzing hierarchy for entity <pc> in library <work> (architecture <arqpc>).

Analyzing hierarchy for entity <register_file> in library <work> (architecture <arqregfile>).

Analyzing hierarchy for entity <sign_ext_unit> in library <work> (architecture <arqsignext>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <Sparcv8Monocicle> in library <work> (Architecture <behavioral>).
Entity <Sparcv8Monocicle> analyzed. Unit <Sparcv8Monocicle> generated.

Analyzing Entity <SEUDisp30> in library <work> (Architecture <behavioral>).
Entity <SEUDisp30> analyzed. Unit <SEUDisp30> generated.

Analyzing Entity <SEUDisp22> in library <work> (Architecture <behavioral>).
Entity <SEUDisp22> analyzed. Unit <SEUDisp22> generated.

Analyzing Entity <MuxPC> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/Users/Personal/Downloads/sparcv8-monocicle-master/MuxPC.vhd" line 18: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <PCplus1>
Entity <MuxPC> analyzed. Unit <MuxPC> generated.

Analyzing Entity <MuxNextRD> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/Users/Personal/Downloads/sparcv8-monocicle-master/MuxNextRD.vhd" line 17: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <O7>
Entity <MuxNextRD> analyzed. Unit <MuxNextRD> generated.

Analyzing Entity <MuxDWR> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/Users/Personal/Downloads/sparcv8-monocicle-master/MuxDWR.vhd" line 17: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <PC>
Entity <MuxDWR> analyzed. Unit <MuxDWR> generated.

Analyzing Entity <DataMemory> in library <work> (Architecture <arqdatamemory>).
WARNING:Xst:819 - "C:/Users/Personal/Downloads/sparcv8-monocicle-master/DM.vhd" line 22: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <ramMemory>
Entity <DataMemory> analyzed. Unit <DataMemory> generated.

Analyzing Entity <windows_manager> in library <work> (Architecture <behavioral>).
Entity <windows_manager> analyzed. Unit <windows_manager> generated.

Analyzing Entity <psr> in library <work> (Architecture <psrarq>).
Entity <psr> analyzed. Unit <psr> generated.

Analyzing Entity <psr_modifier> in library <work> (Architecture <psr_modarq>).
WARNING:Xst:795 - "C:/Users/Personal/Downloads/sparcv8-monocicle-master/psr_modifier.vhd" line 22: Size of operands are different : result is <false>.
Entity <psr_modifier> analyzed. Unit <psr_modifier> generated.

Analyzing Entity <sum32b> in library <work> (Architecture <arqsum32>).
Entity <sum32b> analyzed. Unit <sum32b> generated.

Analyzing Entity <alu> in library <work> (Architecture <arqalu>).
Entity <alu> analyzed. Unit <alu> generated.

Analyzing Entity <control_unit> in library <work> (Architecture <arq_unidadcontrol>).
Entity <control_unit> analyzed. Unit <control_unit> generated.

Analyzing Entity <instructionMemory> in library <work> (Architecture <arqinstructionmemory>).
Entity <instructionMemory> analyzed. Unit <instructionMemory> generated.

Analyzing Entity <mux32b> in library <work> (Architecture <arqmux32b>).
Entity <mux32b> analyzed. Unit <mux32b> generated.

Analyzing Entity <pc> in library <work> (Architecture <arqpc>).
Entity <pc> analyzed. Unit <pc> generated.

Analyzing Entity <register_file> in library <work> (Architecture <arqregfile>).
WARNING:Xst:790 - "C:/Users/Personal/Downloads/sparcv8-monocicle-master/register_file.vhd" line 29: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Users/Personal/Downloads/sparcv8-monocicle-master/register_file.vhd" line 30: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Users/Personal/Downloads/sparcv8-monocicle-master/register_file.vhd" line 31: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Users/Personal/Downloads/sparcv8-monocicle-master/register_file.vhd" line 33: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:819 - "C:/Users/Personal/Downloads/sparcv8-monocicle-master/register_file.vhd" line 26: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <reg>, <Wren>
Entity <register_file> analyzed. Unit <register_file> generated.

Analyzing Entity <sign_ext_unit> in library <work> (Architecture <arqsignext>).
Entity <sign_ext_unit> analyzed. Unit <sign_ext_unit> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <SEUDisp30>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/SEUDisp30.vhd".
Unit <SEUDisp30> synthesized.


Synthesizing Unit <SEUDisp22>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/SEUDisp22.vhd".
Unit <SEUDisp22> synthesized.


Synthesizing Unit <MuxPC>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/MuxPC.vhd".
    Found 32-bit 4-to-1 multiplexer for signal <nPC>.
    Summary:
	inferred  32 Multiplexer(s).
Unit <MuxPC> synthesized.


Synthesizing Unit <MuxNextRD>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/MuxNextRD.vhd".
Unit <MuxNextRD> synthesized.


Synthesizing Unit <MuxDWR>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/MuxDWR.vhd".
    Found 32-bit 4-to-1 multiplexer for signal <DTRF>.
    Summary:
	inferred  32 Multiplexer(s).
Unit <MuxDWR> synthesized.


Synthesizing Unit <DataMemory>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/DM.vhd".
WARNING:Xst:647 - Input <address<31:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_9>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_20>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_16>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_21>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_17>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_22>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_18>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_23>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_19>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_24>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_25>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_30>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_26>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_31>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_27>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_32>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_28>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_33>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_29>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_34>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_35>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_40>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_36>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_41>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_37>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_42>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_38>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_43>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_39>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_44>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_45>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_50>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_46>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_51>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_47>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_52>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_48>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_53>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_49>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_54>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <datoToWr>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_55>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_60>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_56>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_61>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_57>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_62>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_58>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_63>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_59>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <ramMemory_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 32-bit 64-to-1 multiplexer for signal <$varindex0000> created at line 30.
    Summary:
	inferred  32 Multiplexer(s).
Unit <DataMemory> synthesized.


Synthesizing Unit <windows_manager>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/windows_manager.vhd".
WARNING:Xst:737 - Found 6-bit latch for signal <rs1int>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 6-bit latch for signal <rs2int>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ncwp_signal>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 6-bit latch for signal <rdint>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 6-bit subtractor for signal <mux0000$addsub0000> created at line 41.
    Found 5-bit adder carry out for signal <mux0000$addsub0002> created at line 43.
    Found 5-bit comparator greatequal for signal <mux0000$cmp_ge0000> created at line 40.
    Found 6-bit subtractor for signal <mux0001$addsub0000> created at line 51.
    Found 5-bit adder carry out for signal <mux0001$addsub0002> created at line 53.
    Found 5-bit comparator greatequal for signal <mux0001$cmp_ge0000> created at line 50.
    Found 6-bit subtractor for signal <mux0002$addsub0000> created at line 61.
    Found 5-bit adder carry out for signal <mux0002$addsub0002> created at line 63.
    Found 5-bit comparator greatequal for signal <mux0002$cmp_ge0000> created at line 60.
    Found 5-bit comparator greatequal for signal <rdint$cmp_ge0000> created at line 61.
    Found 5-bit comparator greatequal for signal <rdint$cmp_ge0001> created at line 63.
    Found 5-bit comparator lessequal for signal <rdint$cmp_le0000> created at line 65.
    Found 5-bit comparator lessequal for signal <rdint$cmp_le0001> created at line 61.
    Found 5-bit comparator lessequal for signal <rdint$cmp_le0002> created at line 63.
    Found 5-bit comparator greatequal for signal <rs1int$cmp_ge0000> created at line 41.
    Found 5-bit comparator greatequal for signal <rs1int$cmp_ge0001> created at line 43.
    Found 5-bit comparator lessequal for signal <rs1int$cmp_le0000> created at line 45.
    Found 5-bit comparator lessequal for signal <rs1int$cmp_le0001> created at line 41.
    Found 5-bit comparator lessequal for signal <rs1int$cmp_le0002> created at line 43.
    Found 5-bit comparator greatequal for signal <rs2int$cmp_ge0000> created at line 51.
    Found 5-bit comparator greatequal for signal <rs2int$cmp_ge0001> created at line 53.
    Found 5-bit comparator lessequal for signal <rs2int$cmp_le0000> created at line 55.
    Found 5-bit comparator lessequal for signal <rs2int$cmp_le0001> created at line 51.
    Found 5-bit comparator lessequal for signal <rs2int$cmp_le0002> created at line 53.
    Summary:
	inferred   6 Adder/Subtractor(s).
	inferred  18 Comparator(s).
Unit <windows_manager> synthesized.


Synthesizing Unit <psr>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/psr.vhd".
WARNING:Xst:646 - Signal <PSRDATA<3:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <carry>.
    Found 1-bit register for signal <cwp>.
    Found 4-bit register for signal <PSRDATA>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <psr> synthesized.


Synthesizing Unit <psr_modifier>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/psr_modifier.vhd".
WARNING:Xst:737 - Found 1-bit latch for signal <nzvc_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <nzvc_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <nzvc_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <nzvc_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
Unit <psr_modifier> synthesized.


Synthesizing Unit <sum32b>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/sum32b.vhd".
    Found 32-bit adder for signal <R>.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <sum32b> synthesized.


Synthesizing Unit <alu>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/alu.vhd".
    Found 32-bit adder for signal <r$addsub0000> created at line 21.
    Found 32-bit adder carry in for signal <r$addsub0001> created at line 23.
    Found 32-bit subtractor for signal <r$addsub0002> created at line 25.
    Found 32-bit subtractor for signal <r$addsub0003> created at line 27.
    Found 32-bit xor2 for signal <r$xor0000> created at line 35.
    Summary:
	inferred   4 Adder/Subtractor(s).
Unit <alu> synthesized.


Synthesizing Unit <control_unit>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/control_unit.vhd".
WARNING:Xst:647 - Input <icc<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 6-bit latch for signal <Aluop>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 2-bit latch for signal <RFSource>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 2-bit latch for signal <PCSource>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <wrenDM>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <RFdest>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <write_enable>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
    Found 6-bit 4-to-1 multiplexer for signal <Aluop$mux0006>.
    Found 2-bit 4-to-1 multiplexer for signal <PCSource$mux0007>.
    Found 2-bit 8-to-1 multiplexer for signal <PCSource$mux0008> created at line 35.
    Found 1-bit xor2 for signal <PCSource$xor0000> created at line 108.
    Found 1-bit 4-to-1 multiplexer for signal <RFdest$mux0006>.
    Found 2-bit 4-to-1 multiplexer for signal <RFSource$mux0007>.
    Found 1-bit 4-to-1 multiplexer for signal <wrenDM$mux0006>.
    Found 1-bit 4-to-1 multiplexer for signal <write_enable$mux0007>.
    Summary:
	inferred  15 Multiplexer(s).
Unit <control_unit> synthesized.


Synthesizing Unit <instructionMemory>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/instruction_memory.vhd".
WARNING:Xst:647 - Input <address<31:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1781 - Signal <instructions> is used but never assigned. Tied to default value.
    Found 64x32-bit ROM for signal <$varindex0000> created at line 61.
    Summary:
	inferred   1 ROM(s).
Unit <instructionMemory> synthesized.


Synthesizing Unit <mux32b>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/mux32b.vhd".
Unit <mux32b> synthesized.


Synthesizing Unit <pc>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/pc.vhd".
    Found 32-bit register for signal <sig>.
    Summary:
	inferred  32 D-type flip-flop(s).
Unit <pc> synthesized.


Synthesizing Unit <register_file>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/register_file.vhd".
WARNING:Xst:737 - Found 32-bit latch for signal <reg_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_20>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_16>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_21>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_17>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_22>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_18>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_23>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_19>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_24>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_9>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_25>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_30>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_26>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_31>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_27>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_32>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <crd>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_33>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_28>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_29>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_34>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_35>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_36>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_37>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_38>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_39>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 32-bit latch for signal <reg_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 32-bit 40-to-1 multiplexer for signal <$varindex0000> created at line 29.
    Found 32-bit 40-to-1 multiplexer for signal <$varindex0001> created at line 30.
    Found 32-bit 40-to-1 multiplexer for signal <$varindex0002> created at line 31.
    Summary:
	inferred  96 Multiplexer(s).
Unit <register_file> synthesized.


Synthesizing Unit <sign_ext_unit>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/sign_ext_unit.vhd".
Unit <sign_ext_unit> synthesized.


Synthesizing Unit <Sparcv8Monocicle>.
    Related source file is "C:/Users/Personal/Downloads/sparcv8-monocicle-master/Sparcv8Monocicle.vhd".
WARNING:Xst:1780 - Signal <aux34> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <Sparcv8Monocicle> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 64x32-bit ROM                                         : 1
# Adders/Subtractors                                   : 13
 32-bit adder                                          : 4
 32-bit adder carry in                                 : 1
 32-bit subtractor                                     : 2
 5-bit adder carry out                                 : 3
 6-bit subtractor                                      : 3
# Registers                                            : 5
 1-bit register                                        : 2
 32-bit register                                       : 2
 4-bit register                                        : 1
# Latches                                              : 120
 1-bit latch                                           : 8
 2-bit latch                                           : 2
 32-bit latch                                          : 106
 6-bit latch                                           : 4
# Comparators                                          : 18
 5-bit comparator greatequal                           : 9
 5-bit comparator lessequal                            : 9
# Multiplexers                                         : 13
 1-bit 4-to-1 multiplexer                              : 3
 2-bit 4-to-1 multiplexer                              : 2
 2-bit 8-to-1 multiplexer                              : 1
 32-bit 4-to-1 multiplexer                             : 2
 32-bit 40-to-1 multiplexer                            : 3
 32-bit 64-to-1 multiplexer                            : 1
 6-bit 4-to-1 multiplexer                              : 1
# Xors                                                 : 2
 1-bit xor2                                            : 1
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <31>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <30>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <29>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <28>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <27>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <26>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <25>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <24>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <23>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <22>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <21>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <20>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <19>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <18>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <17>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <16>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <15>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <14>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <13>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <12>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <11>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <10>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <9>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <8>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <PSRDATA_1> of sequential type is unconnected in block <Inst_psr>.
WARNING:Xst:2677 - Node <PSRDATA_2> of sequential type is unconnected in block <Inst_psr>.
WARNING:Xst:2677 - Node <PSRDATA_3> of sequential type is unconnected in block <Inst_psr>.
WARNING:Xst:2677 - Node <PSRDATA_1> of sequential type is unconnected in block <psr>.
WARNING:Xst:2677 - Node <PSRDATA_2> of sequential type is unconnected in block <psr>.
WARNING:Xst:2677 - Node <PSRDATA_3> of sequential type is unconnected in block <psr>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 64x32-bit ROM                                         : 1
# Adders/Subtractors                                   : 13
 32-bit adder                                          : 4
 32-bit adder carry in                                 : 1
 32-bit subtractor                                     : 2
 5-bit adder carry out                                 : 3
 6-bit subtractor                                      : 3
# Registers                                            : 67
 Flip-Flops                                            : 67
# Latches                                              : 120
 1-bit latch                                           : 8
 2-bit latch                                           : 2
 32-bit latch                                          : 106
 6-bit latch                                           : 4
# Comparators                                          : 18
 5-bit comparator greatequal                           : 9
 5-bit comparator lessequal                            : 9
# Multiplexers                                         : 13
 1-bit 4-to-1 multiplexer                              : 3
 2-bit 4-to-1 multiplexer                              : 2
 2-bit 8-to-1 multiplexer                              : 1
 32-bit 4-to-1 multiplexer                             : 2
 32-bit 40-to-1 multiplexer                            : 3
 32-bit 64-to-1 multiplexer                            : 1
 6-bit 4-to-1 multiplexer                              : 1
# Xors                                                 : 2
 1-bit xor2                                            : 1
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:2261 - The FF/Latch <31> in Unit <LPM_LATCH_3395> is equivalent to the following 31 FFs/Latches, which will be removed : <30> <29> <28> <27> <26> <25> <24> <23> <22> <21> <20> <19> <18> <17> <16> <15> <14> <13> <12> <11> <10> <9> <8> <7> <6> <5> <4> <3> <2> <1> <0> 
WARNING:Xst:1293 - FF/Latch <31> has a constant value of 0 in block <LPM_LATCH_3395>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <Sparcv8Monocicle> ...

Optimizing unit <psr_modifier> ...

Optimizing unit <alu> ...

Optimizing unit <instructionMemory> ...

Optimizing unit <pc> ...

Optimizing unit <DataMemory> ...

Optimizing unit <windows_manager> ...

Optimizing unit <control_unit> ...

Optimizing unit <register_file> ...

Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <Inst_windows_manager/rs1int_2> in Unit <Sparcv8Monocicle> is equivalent to the following 2 FFs/Latches, which will be removed : <Inst_windows_manager/rs1int_1> <Inst_windows_manager/rs1int_0> 
Found area constraint ratio of 100 (+ 5) on block Sparcv8Monocicle, actual ratio is 432.
Optimizing block <Sparcv8Monocicle> to meet ratio 100 (+ 5) of 960 slices :
WARNING:Xst:2254 - Area constraint could not be met for block <Sparcv8Monocicle>, final ratio is 432.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 67
 Flip-Flops                                            : 67

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : Sparcv8Monocicle.ngr
Top Level Output File Name         : Sparcv8Monocicle
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 34

Cell Usage :
# BELS                             : 8580
#      GND                         : 1
#      INV                         : 32
#      LUT1                        : 31
#      LUT2                        : 146
#      LUT2_D                      : 7
#      LUT2_L                      : 22
#      LUT3                        : 2557
#      LUT3_D                      : 42
#      LUT3_L                      : 6
#      LUT4                        : 2064
#      LUT4_D                      : 74
#      LUT4_L                      : 290
#      MUXCY                       : 229
#      MUXF5                       : 1637
#      MUXF6                       : 737
#      MUXF7                       : 320
#      MUXF8                       : 160
#      VCC                         : 1
#      XORCY                       : 224
# FlipFlops/Latches                : 3461
#      FDC                         : 67
#      LD                          : 18
#      LD_1                        : 32
#      LDC_1                       : 32
#      LDCE                        : 3264
#      LDCE_1                      : 32
#      LDCP                        : 16
# Clock Buffers                    : 24
#      BUFG                        : 23
#      BUFGP                       : 1
# IO Buffers                       : 33
#      IBUF                        : 1
#      OBUF                        : 32
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s100evq100-4 

 Number of Slices:                     4193  out of    960   436% (*) 
 Number of Slice Flip Flops:           3461  out of   1920   180% (*) 
 Number of 4 input LUTs:               5271  out of   1920   274% (*) 
 Number of IOs:                          34
 Number of bonded IOBs:                  34  out of     66    51%  
 Number of GCLKs:                        24  out of     24   100%  

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
------------------------------------------------------------------------------------------+------------------------------------------+-------+
Clock Signal                                                                              | Clock buffer(FF name)                    | Load  |
------------------------------------------------------------------------------------------+------------------------------------------+-------+
CLK                                                                                       | BUFGP                                    | 67    |
Inst_psr_modifier/nzvc_0_not0001(Inst_psr_modifier/nzvc_0_not0001:O)                      | NONE(*)(Inst_psr_modifier/nzvc_0)        | 4     |
Inst_DataMemory/ramMemory_8_cmp_eq00001(Inst_DataMemory/ramMemory_8_cmp_eq00001:O)        | BUFG(*)(Inst_DataMemory/ramMemory_8_31)  | 32    |
Inst_DataMemory/ramMemory_13_cmp_eq00001(Inst_DataMemory/ramMemory_13_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_13_31) | 32    |
Inst_DataMemory/ramMemory_9_cmp_eq00001(Inst_DataMemory/ramMemory_9_cmp_eq00001:O)        | BUFG(*)(Inst_DataMemory/ramMemory_9_31)  | 32    |
Inst_DataMemory/ramMemory_14_cmp_eq00001(Inst_DataMemory/ramMemory_14_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_14_31) | 32    |
Inst_DataMemory/ramMemory_15_cmp_eq00001(Inst_DataMemory/ramMemory_15_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_15_31) | 32    |
Inst_DataMemory/ramMemory_20_cmp_eq00001(Inst_DataMemory/ramMemory_20_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_20_31) | 32    |
Inst_DataMemory/ramMemory_16_cmp_eq00001(Inst_DataMemory/ramMemory_16_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_16_31) | 32    |
Inst_DataMemory/ramMemory_21_cmp_eq00001(Inst_DataMemory/ramMemory_21_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_21_31) | 32    |
Inst_DataMemory/ramMemory_17_cmp_eq00001(Inst_DataMemory/ramMemory_17_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_17_31) | 32    |
Inst_DataMemory/ramMemory_22_cmp_eq00001(Inst_DataMemory/ramMemory_22_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_22_31) | 32    |
Inst_DataMemory/ramMemory_18_cmp_eq00001(Inst_DataMemory/ramMemory_18_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_18_31) | 32    |
Inst_DataMemory/ramMemory_23_cmp_eq00001(Inst_DataMemory/ramMemory_23_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_23_31) | 32    |
Inst_DataMemory/ramMemory_19_cmp_eq00001(Inst_DataMemory/ramMemory_19_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_19_31) | 32    |
Inst_DataMemory/ramMemory_24_cmp_eq00001(Inst_DataMemory/ramMemory_24_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_24_31) | 32    |
Inst_DataMemory/ramMemory_25_cmp_eq00001(Inst_DataMemory/ramMemory_25_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_25_31) | 32    |
Inst_DataMemory/ramMemory_30_cmp_eq00001(Inst_DataMemory/ramMemory_30_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_30_31) | 32    |
Inst_DataMemory/ramMemory_26_cmp_eq00001(Inst_DataMemory/ramMemory_26_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_26_31) | 32    |
Inst_DataMemory/ramMemory_31_cmp_eq00001(Inst_DataMemory/ramMemory_31_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_31_31) | 32    |
Inst_DataMemory/ramMemory_27_cmp_eq00001(Inst_DataMemory/ramMemory_27_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_27_31) | 32    |
Inst_DataMemory/ramMemory_32_cmp_eq00001(Inst_DataMemory/ramMemory_32_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_32_31) | 32    |
Inst_DataMemory/ramMemory_28_cmp_eq00001(Inst_DataMemory/ramMemory_28_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_28_31) | 32    |
Inst_DataMemory/ramMemory_33_cmp_eq00001(Inst_DataMemory/ramMemory_33_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_33_31) | 32    |
Inst_DataMemory/ramMemory_29_cmp_eq00001(Inst_DataMemory/ramMemory_29_cmp_eq00001:O)      | BUFG(*)(Inst_DataMemory/ramMemory_29_31) | 32    |
Inst_DataMemory/ramMemory_34_cmp_eq0000(Inst_DataMemory/ramMemory_34_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_34_31) | 32    |
Inst_DataMemory/ramMemory_35_cmp_eq0000(Inst_DataMemory/ramMemory_35_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_35_31) | 32    |
Inst_DataMemory/ramMemory_40_cmp_eq0000(Inst_DataMemory/ramMemory_40_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_40_31) | 32    |
Inst_DataMemory/ramMemory_36_cmp_eq0000(Inst_DataMemory/ramMemory_36_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_36_31) | 32    |
Inst_DataMemory/ramMemory_41_cmp_eq0000(Inst_DataMemory/ramMemory_41_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_41_31) | 32    |
Inst_DataMemory/ramMemory_37_cmp_eq0000(Inst_DataMemory/ramMemory_37_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_37_31) | 32    |
Inst_DataMemory/ramMemory_42_cmp_eq0000(Inst_DataMemory/ramMemory_42_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_42_31) | 32    |
Inst_DataMemory/ramMemory_38_cmp_eq0000(Inst_DataMemory/ramMemory_38_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_38_31) | 32    |
Inst_DataMemory/ramMemory_43_cmp_eq0000(Inst_DataMemory/ramMemory_43_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_43_31) | 32    |
Inst_DataMemory/ramMemory_39_cmp_eq0000(Inst_DataMemory/ramMemory_39_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_39_31) | 32    |
Inst_DataMemory/ramMemory_44_cmp_eq0000(Inst_DataMemory/ramMemory_44_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_44_31) | 32    |
Inst_DataMemory/ramMemory_45_cmp_eq0000(Inst_DataMemory/ramMemory_45_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_45_31) | 32    |
Inst_DataMemory/ramMemory_50_cmp_eq0000(Inst_DataMemory/ramMemory_50_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_50_31) | 32    |
Inst_DataMemory/ramMemory_46_cmp_eq0000(Inst_DataMemory/ramMemory_46_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_46_31) | 32    |
Inst_DataMemory/ramMemory_51_cmp_eq0000(Inst_DataMemory/ramMemory_51_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_51_31) | 32    |
Inst_DataMemory/ramMemory_47_cmp_eq0000(Inst_DataMemory/ramMemory_47_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_47_31) | 32    |
Inst_DataMemory/ramMemory_52_cmp_eq0000(Inst_DataMemory/ramMemory_52_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_52_31) | 32    |
Inst_DataMemory/ramMemory_48_cmp_eq0000(Inst_DataMemory/ramMemory_48_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_48_31) | 32    |
Inst_DataMemory/ramMemory_53_cmp_eq0000(Inst_DataMemory/ramMemory_53_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_53_31) | 32    |
Inst_DataMemory/ramMemory_49_cmp_eq0000(Inst_DataMemory/ramMemory_49_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_49_31) | 32    |
Inst_DataMemory/ramMemory_54_cmp_eq0000(Inst_DataMemory/ramMemory_54_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_54_31) | 32    |
Inst_control_unit/wrenDM                                                                  | NONE(Inst_DataMemory/datoToWr_31)        | 32    |
Inst_DataMemory/ramMemory_55_cmp_eq0000(Inst_DataMemory/ramMemory_55_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_55_31) | 32    |
Inst_DataMemory/ramMemory_60_cmp_eq0000(Inst_DataMemory/ramMemory_60_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_60_31) | 32    |
Inst_DataMemory/ramMemory_56_cmp_eq0000(Inst_DataMemory/ramMemory_56_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_56_31) | 32    |
Inst_DataMemory/ramMemory_61_cmp_eq0000(Inst_DataMemory/ramMemory_61_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_61_31) | 32    |
Inst_DataMemory/ramMemory_57_cmp_eq0000(Inst_DataMemory/ramMemory_57_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_57_31) | 32    |
Inst_DataMemory/ramMemory_62_cmp_eq0000(Inst_DataMemory/ramMemory_62_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_62_31) | 32    |
Inst_DataMemory/ramMemory_58_cmp_eq0000(Inst_DataMemory/ramMemory_58_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_58_31) | 32    |
Inst_DataMemory/ramMemory_63_cmp_eq0000(Inst_DataMemory/ramMemory_63_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_63_31) | 32    |
Inst_DataMemory/ramMemory_59_cmp_eq0000(Inst_DataMemory/ramMemory_59_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_59_31) | 32    |
Inst_DataMemory/ramMemory_0_not0001(Inst_DataMemory/ramMemory_0_not0001:O)                | NONE(*)(Inst_DataMemory/ramMemory_0_31)  | 32    |
Inst_DataMemory/ramMemory_1_cmp_eq0000(Inst_DataMemory/ramMemory_1_cmp_eq0000:O)          | NONE(*)(Inst_DataMemory/ramMemory_1_31)  | 32    |
Inst_DataMemory/ramMemory_2_cmp_eq0000(Inst_DataMemory/ramMemory_2_cmp_eq0000:O)          | NONE(*)(Inst_DataMemory/ramMemory_2_31)  | 32    |
Inst_DataMemory/ramMemory_3_cmp_eq0000(Inst_DataMemory/ramMemory_3_cmp_eq0000:O)          | NONE(*)(Inst_DataMemory/ramMemory_3_31)  | 32    |
Inst_DataMemory/ramMemory_4_cmp_eq0000(Inst_DataMemory/ramMemory_4_cmp_eq0000:O)          | NONE(*)(Inst_DataMemory/ramMemory_4_31)  | 32    |
Inst_DataMemory/ramMemory_5_cmp_eq0000(Inst_DataMemory/ramMemory_5_cmp_eq0000:O)          | NONE(*)(Inst_DataMemory/ramMemory_5_31)  | 32    |
Inst_DataMemory/ramMemory_10_cmp_eq0000(Inst_DataMemory/ramMemory_10_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_10_31) | 32    |
Inst_DataMemory/ramMemory_6_cmp_eq0000(Inst_DataMemory/ramMemory_6_cmp_eq0000:O)          | NONE(*)(Inst_DataMemory/ramMemory_6_31)  | 32    |
Inst_DataMemory/ramMemory_11_cmp_eq0000(Inst_DataMemory/ramMemory_11_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_11_31) | 32    |
Inst_DataMemory/ramMemory_7_cmp_eq0000(Inst_DataMemory/ramMemory_7_cmp_eq0000:O)          | NONE(*)(Inst_DataMemory/ramMemory_7_31)  | 32    |
Inst_DataMemory/ramMemory_12_cmp_eq0000(Inst_DataMemory/ramMemory_12_cmp_eq00001:O)       | NONE(*)(Inst_DataMemory/ramMemory_12_31) | 32    |
Inst_windows_manager/rs1int_cmp_le0000(Inst_windows_manager/rs1int_cmp_le00001:O)         | NONE(*)(Inst_windows_manager/rs1int_5)   | 4     |
Inst_windows_manager/rs2int_cmp_le0000(Inst_windows_manager/rs2int_cmp_le00001:O)         | NONE(*)(Inst_windows_manager/rs2int_5)   | 6     |
Inst_windows_manager/rdint_cmp_le0000(Inst_windows_manager/rdint_cmp_le00001:O)           | NONE(*)(Inst_windows_manager/rdint_5)    | 6     |
Inst_control_unit/Mmux_RFSource_mux0007270(Inst_windows_manager/ncwp_signal_cmp_eq00001:O)| NONE(*)(Inst_windows_manager/ncwp_signal)| 1     |
Inst_control_unit/Aluop_not0001(Inst_control_unit/Aluop_not00011:O)                       | NONE(*)(Inst_control_unit/Aluop_5)       | 12    |
Inst_control_unit/RFdest_not0001(Inst_control_unit/RFdest_not0001:O)                      | NONE(*)(Inst_control_unit/RFdest)        | 1     |
Inst_register_file/reg_1_cmp_eq0000(Inst_register_file/reg_1_cmp_eq000011:O)              | NONE(*)(Inst_register_file/reg_1_31)     | 32    |
Inst_register_file/reg_12_cmp_eq0000(Inst_register_file/reg_12_cmp_eq000021:O)            | NONE(*)(Inst_register_file/reg_12_31)    | 32    |
Inst_register_file/reg_2_cmp_eq0000(Inst_register_file/reg_2_cmp_eq000011:O)              | NONE(*)(Inst_register_file/reg_2_31)     | 32    |
Inst_register_file/reg_13_cmp_eq0000(Inst_register_file/reg_13_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_13_31)    | 32    |
Inst_register_file/reg_3_cmp_eq0000(Inst_register_file/reg_3_cmp_eq000011:O)              | NONE(*)(Inst_register_file/reg_3_31)     | 32    |
Inst_register_file/reg_14_cmp_eq0000(Inst_register_file/reg_14_cmp_eq000021:O)            | NONE(*)(Inst_register_file/reg_14_31)    | 32    |
Inst_register_file/reg_4_cmp_eq0000(Inst_register_file/reg_4_cmp_eq000011:O)              | NONE(*)(Inst_register_file/reg_4_31)     | 32    |
Inst_register_file/reg_15_cmp_eq0000(Inst_register_file/reg_15_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_15_31)    | 32    |
Inst_register_file/reg_20_cmp_eq0000(Inst_register_file/reg_20_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_20_31)    | 32    |
Inst_register_file/reg_5_cmp_eq0000(Inst_register_file/reg_5_cmp_eq000011:O)              | NONE(*)(Inst_register_file/reg_5_31)     | 32    |
Inst_register_file/reg_16_cmp_eq0000(Inst_register_file/reg_16_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_16_31)    | 32    |
Inst_register_file/reg_21_cmp_eq0000(Inst_register_file/reg_21_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_21_31)    | 32    |
Inst_register_file/reg_6_cmp_eq0000(Inst_register_file/reg_6_cmp_eq000011:O)              | NONE(*)(Inst_register_file/reg_6_31)     | 32    |
Inst_register_file/reg_17_cmp_eq0000(Inst_register_file/reg_17_cmp_eq000021:O)            | NONE(*)(Inst_register_file/reg_17_31)    | 32    |
Inst_register_file/reg_22_cmp_eq0000(Inst_register_file/reg_22_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_22_31)    | 32    |
Inst_register_file/reg_7_cmp_eq0000(Inst_register_file/reg_7_cmp_eq000011:O)              | NONE(*)(Inst_register_file/reg_7_31)     | 32    |
Inst_register_file/reg_18_cmp_eq0000(Inst_register_file/reg_18_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_18_31)    | 32    |
Inst_register_file/reg_23_cmp_eq0000(Inst_register_file/reg_23_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_23_31)    | 32    |
Inst_register_file/reg_8_cmp_eq0000(Inst_register_file/reg_8_cmp_eq000011:O)              | NONE(*)(Inst_register_file/reg_8_31)     | 32    |
Inst_register_file/reg_19_cmp_eq0000(Inst_register_file/reg_19_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_19_31)    | 32    |
Inst_register_file/reg_24_cmp_eq0000(Inst_register_file/reg_24_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_24_31)    | 32    |
Inst_register_file/reg_9_cmp_eq0000(Inst_register_file/reg_9_cmp_eq000011:O)              | NONE(*)(Inst_register_file/reg_9_31)     | 32    |
Inst_register_file/reg_25_cmp_eq0000(Inst_register_file/reg_25_cmp_eq000021:O)            | NONE(*)(Inst_register_file/reg_25_31)    | 32    |
Inst_register_file/reg_30_cmp_eq0000(Inst_register_file/reg_30_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_30_31)    | 32    |
Inst_register_file/reg_26_cmp_eq0000(Inst_register_file/reg_26_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_26_31)    | 32    |
Inst_register_file/reg_31_cmp_eq0000(Inst_register_file/reg_31_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_31_31)    | 32    |
Inst_register_file/reg_27_cmp_eq0000(Inst_register_file/reg_27_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_27_31)    | 32    |
Inst_register_file/reg_32_cmp_eq0000(Inst_register_file/reg_32_cmp_eq000021:O)            | NONE(*)(Inst_register_file/reg_32_31)    | 32    |
RST                                                                                       | IBUF                                     | 32    |
Inst_register_file/reg_33_cmp_eq0000(Inst_register_file/reg_33_cmp_eq000021:O)            | NONE(*)(Inst_register_file/reg_33_31)    | 32    |
Inst_register_file/reg_28_cmp_eq0000(Inst_register_file/reg_28_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_28_31)    | 32    |
Inst_register_file/reg_29_cmp_eq0000(Inst_register_file/reg_29_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_29_31)    | 32    |
Inst_register_file/reg_34_cmp_eq0000(Inst_register_file/reg_34_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_34_31)    | 32    |
Inst_register_file/reg_35_cmp_eq0000(Inst_register_file/reg_35_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_35_31)    | 32    |
Inst_register_file/reg_36_cmp_eq0000(Inst_register_file/reg_36_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_36_31)    | 32    |
Inst_register_file/reg_37_cmp_eq0000(Inst_register_file/reg_37_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_37_31)    | 32    |
Inst_register_file/reg_38_cmp_eq0000(Inst_register_file/reg_38_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_38_31)    | 32    |
Inst_register_file/reg_39_cmp_eq0000(Inst_register_file/reg_39_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_39_31)    | 32    |
Inst_register_file/reg_10_cmp_eq0000(Inst_register_file/reg_10_cmp_eq000011:O)            | NONE(*)(Inst_register_file/reg_10_31)    | 32    |
Inst_register_file/reg_11_cmp_eq0000(Inst_register_file/reg_11_cmp_eq000021:O)            | NONE(*)(Inst_register_file/reg_11_31)    | 32    |
------------------------------------------------------------------------------------------+------------------------------------------+-------+
(*) These 110 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------------------------------------------------------+------------------------------------+-------+
Control Signal                                                                     | Buffer(FF name)                    | Load  |
-----------------------------------------------------------------------------------+------------------------------------+-------+
RST                                                                                | IBUF                               | 3395  |
Inst_windows_manager/rdint_0__and0000(Inst_windows_manager/rdint_0__and00001:O)    | NONE(Inst_windows_manager/rdint_0) | 1     |
Inst_windows_manager/rdint_0__and0001(Inst_instructionMemory/outInstruction<25>1:O)| NONE(Inst_windows_manager/rdint_0) | 1     |
Inst_windows_manager/rdint_1__and0000(Inst_windows_manager/rdint_1__and00001:O)    | NONE(Inst_windows_manager/rdint_1) | 1     |
Inst_windows_manager/rdint_1__and0001(Inst_windows_manager/rdint_1__and00011:O)    | NONE(Inst_windows_manager/rdint_1) | 1     |
Inst_windows_manager/rdint_2__and0000(Inst_windows_manager/rdint_2__and00001:O)    | NONE(Inst_windows_manager/rdint_2) | 1     |
Inst_windows_manager/rdint_2__and0001(Inst_windows_manager/rdint_2__and00011:O)    | NONE(Inst_windows_manager/rdint_2) | 1     |
Inst_windows_manager/rdint_3__and0000(Inst_windows_manager/rdint_3__and00001:O)    | NONE(Inst_windows_manager/rdint_3) | 1     |
Inst_windows_manager/rdint_4__and0000(Inst_windows_manager/rdint_4__and000021:O)   | NONE(Inst_windows_manager/rdint_4) | 1     |
Inst_windows_manager/rdint_4__and0001(Inst_windows_manager/rdint_4__and000111:O)   | NONE(Inst_windows_manager/rdint_4) | 1     |
Inst_windows_manager/rdint_5__and0000(Inst_windows_manager/rdint_5__and000011:O)   | NONE(Inst_windows_manager/rdint_5) | 1     |
Inst_windows_manager/rdint_5__and0001(Inst_windows_manager/rdint_5__and00011:O)    | NONE(Inst_windows_manager/rdint_5) | 1     |
Inst_windows_manager/rs1int_0__and0000(Inst_windows_manager/rs1int_2__and00001:O)  | NONE(Inst_windows_manager/rs1int_2)| 1     |
Inst_windows_manager/rs1int_0__and0001(Inst_windows_manager/rs1int_2__and00011:O)  | NONE(Inst_windows_manager/rs1int_2)| 1     |
Inst_windows_manager/rs1int_3__and0000(Inst_windows_manager/rs1int_3__and00001:O)  | NONE(Inst_windows_manager/rs1int_3)| 1     |
Inst_windows_manager/rs1int_4__and0000(Inst_windows_manager/rs1int_4__and000021:O) | NONE(Inst_windows_manager/rs1int_4)| 1     |
Inst_windows_manager/rs1int_4__and0001(Inst_windows_manager/rs1int_4__and000111:O) | NONE(Inst_windows_manager/rs1int_4)| 1     |
Inst_windows_manager/rs1int_5__and0000(Inst_windows_manager/rs1int_5__and000011:O) | NONE(Inst_windows_manager/rs1int_5)| 1     |
Inst_windows_manager/rs1int_5__and0001(Inst_windows_manager/rs1int_5__and00011:O)  | NONE(Inst_windows_manager/rs1int_5)| 1     |
Inst_windows_manager/rs2int_0__and0000(Inst_windows_manager/rs2int_0__and00001:O)  | NONE(Inst_windows_manager/rs2int_0)| 1     |
Inst_windows_manager/rs2int_0__and0001(Inst_windows_manager/rs2int_0__and00011:O)  | NONE(Inst_windows_manager/rs2int_0)| 1     |
Inst_windows_manager/rs2int_1__and0000(Inst_windows_manager/rs2int_1__and00001:O)  | NONE(Inst_windows_manager/rs2int_1)| 1     |
Inst_windows_manager/rs2int_1__and0001(Inst_windows_manager/rs2int_1__and00011:O)  | NONE(Inst_windows_manager/rs2int_1)| 1     |
Inst_windows_manager/rs2int_2__and0000(Inst_windows_manager/rs2int_2__and00001:O)  | NONE(Inst_windows_manager/rs2int_2)| 1     |
Inst_windows_manager/rs2int_2__and0001(Inst_windows_manager/rs2int_2__and00011:O)  | NONE(Inst_windows_manager/rs2int_2)| 1     |
Inst_windows_manager/rs2int_3__and0000(Inst_windows_manager/rs2int_3__and00001:O)  | NONE(Inst_windows_manager/rs2int_3)| 1     |
Inst_windows_manager/rs2int_4__and0000(Inst_windows_manager/rs2int_4__and000021:O) | NONE(Inst_windows_manager/rs2int_4)| 1     |
Inst_windows_manager/rs2int_4__and0001(Inst_windows_manager/rs2int_4__and000111:O) | NONE(Inst_windows_manager/rs2int_4)| 1     |
Inst_windows_manager/rs2int_5__and0000(Inst_windows_manager/rs2int_5__and000011:O) | NONE(Inst_windows_manager/rs2int_5)| 1     |
Inst_windows_manager/rs2int_5__and0001(Inst_windows_manager/rs2int_5__and00011:O)  | NONE(Inst_windows_manager/rs2int_5)| 1     |
aux4<17>(Inst_instructionMemory/outInstruction<17>:O)                              | NONE(Inst_windows_manager/rs1int_3)| 1     |
aux4<28>(Inst_instructionMemory/outInstruction<28>:O)                              | NONE(Inst_windows_manager/rdint_3) | 1     |
aux4<3>(Inst_instructionMemory/outInstruction<3>:O)                                | NONE(Inst_windows_manager/rs2int_3)| 1     |
-----------------------------------------------------------------------------------+------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 20.132ns (Maximum Frequency: 49.671MHz)
   Minimum input arrival time before clock: 25.033ns
   Maximum output required time after clock: 24.147ns
   Maximum combinational path delay: 24.600ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 10.780ns (frequency: 92.764MHz)
  Total number of paths / destination ports: 13806 / 65
-------------------------------------------------------------------------
Delay:               10.780ns (Levels of Logic = 32)
  Source:            Inst_pc/sig_5 (FF)
  Destination:       Inst_npc/sig_31 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: Inst_pc/sig_5 to Inst_npc/sig_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             24   0.591   1.427  Inst_pc/sig_5 (Inst_pc/sig_5)
     LUT4:I0->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.465  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT2:I0->O            1   0.704   0.000  Inst_sumDisp22/Madd_R_lut<5> (Inst_sumDisp22/Madd_R_lut<5>)
     MUXCY:S->O            1   0.464   0.000  Inst_sumDisp22/Madd_R_cy<5> (Inst_sumDisp22/Madd_R_cy<5>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<6> (Inst_sumDisp22/Madd_R_cy<6>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<7> (Inst_sumDisp22/Madd_R_cy<7>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<8> (Inst_sumDisp22/Madd_R_cy<8>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<9> (Inst_sumDisp22/Madd_R_cy<9>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<10> (Inst_sumDisp22/Madd_R_cy<10>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<11> (Inst_sumDisp22/Madd_R_cy<11>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<12> (Inst_sumDisp22/Madd_R_cy<12>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<13> (Inst_sumDisp22/Madd_R_cy<13>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<14> (Inst_sumDisp22/Madd_R_cy<14>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<15> (Inst_sumDisp22/Madd_R_cy<15>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<16> (Inst_sumDisp22/Madd_R_cy<16>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<17> (Inst_sumDisp22/Madd_R_cy<17>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<18> (Inst_sumDisp22/Madd_R_cy<18>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<19> (Inst_sumDisp22/Madd_R_cy<19>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<20> (Inst_sumDisp22/Madd_R_cy<20>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<21> (Inst_sumDisp22/Madd_R_cy<21>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<22> (Inst_sumDisp22/Madd_R_cy<22>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<23> (Inst_sumDisp22/Madd_R_cy<23>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<24> (Inst_sumDisp22/Madd_R_cy<24>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<25> (Inst_sumDisp22/Madd_R_cy<25>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<26> (Inst_sumDisp22/Madd_R_cy<26>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<27> (Inst_sumDisp22/Madd_R_cy<27>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<28> (Inst_sumDisp22/Madd_R_cy<28>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<29> (Inst_sumDisp22/Madd_R_cy<29>)
     MUXCY:CI->O           0   0.059   0.000  Inst_sumDisp22/Madd_R_cy<30> (Inst_sumDisp22/Madd_R_cy<30>)
     XORCY:CI->O           1   0.804   0.499  Inst_sumDisp22/Madd_R_xor<31> (aux22<31>)
     LUT3:I1->O            1   0.704   0.000  Inst_MuxPC/Mmux_nPC_324 (Inst_MuxPC/Mmux_nPC_324)
     MUXF5:I1->O           1   0.321   0.000  Inst_MuxPC/Mmux_nPC_2_f5_23 (aux25<31>)
     FDC:D                     0.308          Inst_npc/sig_31
    ----------------------------------------
    Total                     10.780ns (6.779ns logic, 4.001ns route)
                                       (62.9% logic, 37.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_1_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_1_21 (LATCH)
  Destination:       Inst_register_file/reg_1_7 (LATCH)
  Source Clock:      Inst_register_file/reg_1_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_1_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_1_21 to Inst_register_file/reg_1_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_1_21 (Inst_register_file/reg_1_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1254 (Inst_register_file/Mmux__varindex0001_1254)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_40 (Inst_register_file/Mmux__varindex0001_10_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_1_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_12_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_12_21 (LATCH)
  Destination:       Inst_register_file/reg_12_7 (LATCH)
  Source Clock:      Inst_register_file/reg_12_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_12_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_12_21 to Inst_register_file/reg_12_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_12_21 (Inst_register_file/reg_12_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1252 (Inst_register_file/Mmux__varindex0001_1252)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_38 (Inst_register_file/Mmux__varindex0001_10_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_12_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_2_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_2_21 (LATCH)
  Destination:       Inst_register_file/reg_2_7 (LATCH)
  Source Clock:      Inst_register_file/reg_2_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_2_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_2_21 to Inst_register_file/reg_2_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_2_21 (Inst_register_file/reg_2_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1253 (Inst_register_file/Mmux__varindex0001_1253)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_39 (Inst_register_file/Mmux__varindex0001_10_f540)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_2_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_13_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_13_21 (LATCH)
  Destination:       Inst_register_file/reg_13_7 (LATCH)
  Source Clock:      Inst_register_file/reg_13_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_13_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_13_21 to Inst_register_file/reg_13_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_13_21 (Inst_register_file/reg_13_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1179 (Inst_register_file/Mmux__varindex0001_1179)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_39 (Inst_register_file/Mmux__varindex0001_9_f540)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_13_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_3_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_3_21 (LATCH)
  Destination:       Inst_register_file/reg_3_7 (LATCH)
  Source Clock:      Inst_register_file/reg_3_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_3_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_3_21 to Inst_register_file/reg_3_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_3_21 (Inst_register_file/reg_3_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1181 (Inst_register_file/Mmux__varindex0001_1181)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_40 (Inst_register_file/Mmux__varindex0001_9_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_3_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_14_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_14_21 (LATCH)
  Destination:       Inst_register_file/reg_14_7 (LATCH)
  Source Clock:      Inst_register_file/reg_14_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_14_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_14_21 to Inst_register_file/reg_14_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_14_21 (Inst_register_file/reg_14_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1178 (Inst_register_file/Mmux__varindex0001_1178)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_38 (Inst_register_file/Mmux__varindex0001_9_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_14_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_4_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_4_21 (LATCH)
  Destination:       Inst_register_file/reg_4_7 (LATCH)
  Source Clock:      Inst_register_file/reg_4_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_4_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_4_21 to Inst_register_file/reg_4_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_4_21 (Inst_register_file/reg_4_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1252 (Inst_register_file/Mmux__varindex0001_1252)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_38 (Inst_register_file/Mmux__varindex0001_10_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_4_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_15_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_15_21 (LATCH)
  Destination:       Inst_register_file/reg_15_7 (LATCH)
  Source Clock:      Inst_register_file/reg_15_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_15_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_15_21 to Inst_register_file/reg_15_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_15_21 (Inst_register_file/reg_15_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1065 (Inst_register_file/Mmux__varindex0001_1065)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_25 (Inst_register_file/Mmux__varindex0001_8_f526)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_15_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_20_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_20_21 (LATCH)
  Destination:       Inst_register_file/reg_20_7 (LATCH)
  Source Clock:      Inst_register_file/reg_20_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_20_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_20_21 to Inst_register_file/reg_20_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_20_21 (Inst_register_file/reg_20_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1180 (Inst_register_file/Mmux__varindex0001_1180)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_38 (Inst_register_file/Mmux__varindex0001_10_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_20_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_5_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_5_21 (LATCH)
  Destination:       Inst_register_file/reg_5_7 (LATCH)
  Source Clock:      Inst_register_file/reg_5_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_5_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_5_21 to Inst_register_file/reg_5_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_5_21 (Inst_register_file/reg_5_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1179 (Inst_register_file/Mmux__varindex0001_1179)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_39 (Inst_register_file/Mmux__varindex0001_9_f540)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_5_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_16_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_16_21 (LATCH)
  Destination:       Inst_register_file/reg_16_7 (LATCH)
  Source Clock:      Inst_register_file/reg_16_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_16_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_16_21 to Inst_register_file/reg_16_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_16_21 (Inst_register_file/reg_16_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1255 (Inst_register_file/Mmux__varindex0001_1255)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_11_f5_12 (Inst_register_file/Mmux__varindex0001_11_f513)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_16_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_21_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_21_21 (LATCH)
  Destination:       Inst_register_file/reg_21_7 (LATCH)
  Source Clock:      Inst_register_file/reg_21_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_21_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_21_21 to Inst_register_file/reg_21_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_21_21 (Inst_register_file/reg_21_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1067 (Inst_register_file/Mmux__varindex0001_1067)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_39 (Inst_register_file/Mmux__varindex0001_9_f540)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_21_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_6_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_6_21 (LATCH)
  Destination:       Inst_register_file/reg_6_7 (LATCH)
  Source Clock:      Inst_register_file/reg_6_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_6_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_6_21 to Inst_register_file/reg_6_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_6_21 (Inst_register_file/reg_6_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1178 (Inst_register_file/Mmux__varindex0001_1178)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_38 (Inst_register_file/Mmux__varindex0001_9_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_6_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_17_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_17_21 (LATCH)
  Destination:       Inst_register_file/reg_17_7 (LATCH)
  Source Clock:      Inst_register_file/reg_17_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_17_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_17_21 to Inst_register_file/reg_17_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_17_21 (Inst_register_file/reg_17_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1183 (Inst_register_file/Mmux__varindex0001_1183)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_40 (Inst_register_file/Mmux__varindex0001_10_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_17_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_22_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_22_21 (LATCH)
  Destination:       Inst_register_file/reg_22_7 (LATCH)
  Source Clock:      Inst_register_file/reg_22_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_22_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_22_21 to Inst_register_file/reg_22_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_22_21 (Inst_register_file/reg_22_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1066 (Inst_register_file/Mmux__varindex0001_1066)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_38 (Inst_register_file/Mmux__varindex0001_9_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_22_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_7_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_7_21 (LATCH)
  Destination:       Inst_register_file/reg_7_7 (LATCH)
  Source Clock:      Inst_register_file/reg_7_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_7_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_7_21 to Inst_register_file/reg_7_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_7_21 (Inst_register_file/reg_7_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1065 (Inst_register_file/Mmux__varindex0001_1065)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_25 (Inst_register_file/Mmux__varindex0001_8_f526)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_7_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_18_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_18_21 (LATCH)
  Destination:       Inst_register_file/reg_18_7 (LATCH)
  Source Clock:      Inst_register_file/reg_18_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_18_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_18_21 to Inst_register_file/reg_18_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_18_21 (Inst_register_file/reg_18_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1182 (Inst_register_file/Mmux__varindex0001_1182)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_39 (Inst_register_file/Mmux__varindex0001_10_f540)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_18_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_23_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_23_21 (LATCH)
  Destination:       Inst_register_file/reg_23_7 (LATCH)
  Source Clock:      Inst_register_file/reg_23_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_23_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_23_21 to Inst_register_file/reg_23_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_23_21 (Inst_register_file/reg_23_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_939 (Inst_register_file/Mmux__varindex0001_939)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_25 (Inst_register_file/Mmux__varindex0001_8_f526)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_23_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_8_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_8_21 (LATCH)
  Destination:       Inst_register_file/reg_8_7 (LATCH)
  Source Clock:      Inst_register_file/reg_8_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_8_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_8_21 to Inst_register_file/reg_8_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_8_21 (Inst_register_file/reg_8_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1313 (Inst_register_file/Mmux__varindex0001_1313)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_11_f5_12 (Inst_register_file/Mmux__varindex0001_11_f513)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_8_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_19_cmp_eq0000'
  Clock period: 20.132ns (frequency: 49.671MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.132ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_19_21 (LATCH)
  Destination:       Inst_register_file/reg_19_7 (LATCH)
  Source Clock:      Inst_register_file/reg_19_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_19_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_19_21 to Inst_register_file/reg_19_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_19_21 (Inst_register_file/reg_19_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1068 (Inst_register_file/Mmux__varindex0001_1068)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_40 (Inst_register_file/Mmux__varindex0001_9_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_19_7
    ----------------------------------------
    Total                     20.132ns (13.131ns logic, 7.001ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_24_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_24_21 (LATCH)
  Destination:       Inst_register_file/reg_24_7 (LATCH)
  Source Clock:      Inst_register_file/reg_24_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_24_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_24_21 to Inst_register_file/reg_24_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_24_21 (Inst_register_file/reg_24_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1255 (Inst_register_file/Mmux__varindex0001_1255)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_11_f5_12 (Inst_register_file/Mmux__varindex0001_11_f513)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_24_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_9_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_9_21 (LATCH)
  Destination:       Inst_register_file/reg_9_7 (LATCH)
  Source Clock:      Inst_register_file/reg_9_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_9_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_9_21 to Inst_register_file/reg_9_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_9_21 (Inst_register_file/reg_9_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1254 (Inst_register_file/Mmux__varindex0001_1254)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_40 (Inst_register_file/Mmux__varindex0001_10_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_9_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_25_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_25_21 (LATCH)
  Destination:       Inst_register_file/reg_25_7 (LATCH)
  Source Clock:      Inst_register_file/reg_25_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_25_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_25_21 to Inst_register_file/reg_25_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_25_21 (Inst_register_file/reg_25_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1183 (Inst_register_file/Mmux__varindex0001_1183)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_40 (Inst_register_file/Mmux__varindex0001_10_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_25_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_30_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_30_21 (LATCH)
  Destination:       Inst_register_file/reg_30_7 (LATCH)
  Source Clock:      Inst_register_file/reg_30_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_30_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_30_21 to Inst_register_file/reg_30_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_30_21 (Inst_register_file/reg_30_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1066 (Inst_register_file/Mmux__varindex0001_1066)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_38 (Inst_register_file/Mmux__varindex0001_9_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_30_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_26_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_26_21 (LATCH)
  Destination:       Inst_register_file/reg_26_7 (LATCH)
  Source Clock:      Inst_register_file/reg_26_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_26_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_26_21 to Inst_register_file/reg_26_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_26_21 (Inst_register_file/reg_26_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1182 (Inst_register_file/Mmux__varindex0001_1182)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_39 (Inst_register_file/Mmux__varindex0001_10_f540)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_26_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_31_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_31_21 (LATCH)
  Destination:       Inst_register_file/reg_31_7 (LATCH)
  Source Clock:      Inst_register_file/reg_31_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_31_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_31_21 to Inst_register_file/reg_31_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_31_21 (Inst_register_file/reg_31_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_939 (Inst_register_file/Mmux__varindex0001_939)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_25 (Inst_register_file/Mmux__varindex0001_8_f526)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_31_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_27_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_27_21 (LATCH)
  Destination:       Inst_register_file/reg_27_7 (LATCH)
  Source Clock:      Inst_register_file/reg_27_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_27_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_27_21 to Inst_register_file/reg_27_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_27_21 (Inst_register_file/reg_27_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1068 (Inst_register_file/Mmux__varindex0001_1068)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_40 (Inst_register_file/Mmux__varindex0001_9_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_27_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_32_cmp_eq0000'
  Clock period: 19.121ns (frequency: 52.297MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               19.121ns (Levels of Logic = 19)
  Source:            Inst_register_file/reg_32_21 (LATCH)
  Destination:       Inst_register_file/reg_32_7 (LATCH)
  Source Clock:      Inst_register_file/reg_32_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_32_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_32_21 to Inst_register_file/reg_32_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_32_21 (Inst_register_file/reg_32_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1069 (Inst_register_file/Mmux__varindex0001_1069)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_26 (Inst_register_file/Mmux__varindex0001_8_f527)
     MUXF6:I0->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_32_7
    ----------------------------------------
    Total                     19.121ns (12.089ns logic, 7.032ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_33_cmp_eq0000'
  Clock period: 19.077ns (frequency: 52.418MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               19.077ns (Levels of Logic = 19)
  Source:            Inst_register_file/reg_33_21 (LATCH)
  Destination:       Inst_register_file/reg_33_7 (LATCH)
  Source Clock:      Inst_register_file/reg_33_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_33_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_33_21 to Inst_register_file/reg_33_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_33_21 (Inst_register_file/reg_33_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1069 (Inst_register_file/Mmux__varindex0001_1069)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_26 (Inst_register_file/Mmux__varindex0001_8_f527)
     MUXF6:I0->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_33_7
    ----------------------------------------
    Total                     19.077ns (12.089ns logic, 6.988ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_28_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_28_21 (LATCH)
  Destination:       Inst_register_file/reg_28_7 (LATCH)
  Source Clock:      Inst_register_file/reg_28_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_28_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_28_21 to Inst_register_file/reg_28_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_28_21 (Inst_register_file/reg_28_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1180 (Inst_register_file/Mmux__varindex0001_1180)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_38 (Inst_register_file/Mmux__varindex0001_10_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_28_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_29_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_29_21 (LATCH)
  Destination:       Inst_register_file/reg_29_7 (LATCH)
  Source Clock:      Inst_register_file/reg_29_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_29_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_29_21 to Inst_register_file/reg_29_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_29_21 (Inst_register_file/reg_29_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1067 (Inst_register_file/Mmux__varindex0001_1067)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_39 (Inst_register_file/Mmux__varindex0001_9_f540)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_29_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_34_cmp_eq0000'
  Clock period: 19.121ns (frequency: 52.297MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               19.121ns (Levels of Logic = 19)
  Source:            Inst_register_file/reg_34_21 (LATCH)
  Destination:       Inst_register_file/reg_34_7 (LATCH)
  Source Clock:      Inst_register_file/reg_34_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_34_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_34_21 to Inst_register_file/reg_34_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_34_21 (Inst_register_file/reg_34_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_941 (Inst_register_file/Mmux__varindex0001_941)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_26 (Inst_register_file/Mmux__varindex0001_8_f527)
     MUXF6:I0->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_34_7
    ----------------------------------------
    Total                     19.121ns (12.089ns logic, 7.032ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_35_cmp_eq0000'
  Clock period: 19.077ns (frequency: 52.418MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               19.077ns (Levels of Logic = 19)
  Source:            Inst_register_file/reg_35_21 (LATCH)
  Destination:       Inst_register_file/reg_35_7 (LATCH)
  Source Clock:      Inst_register_file/reg_35_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_35_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_35_21 to Inst_register_file/reg_35_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_35_21 (Inst_register_file/reg_35_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_941 (Inst_register_file/Mmux__varindex0001_941)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_26 (Inst_register_file/Mmux__varindex0001_8_f527)
     MUXF6:I0->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_35_7
    ----------------------------------------
    Total                     19.077ns (12.089ns logic, 6.988ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_36_cmp_eq0000'
  Clock period: 19.121ns (frequency: 52.297MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               19.121ns (Levels of Logic = 19)
  Source:            Inst_register_file/reg_36_21 (LATCH)
  Destination:       Inst_register_file/reg_36_7 (LATCH)
  Source Clock:      Inst_register_file/reg_36_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_36_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_36_21 to Inst_register_file/reg_36_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_36_21 (Inst_register_file/reg_36_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_940 (Inst_register_file/Mmux__varindex0001_940)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_7_f5_12 (Inst_register_file/Mmux__varindex0001_7_f513)
     MUXF6:I1->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_36_7
    ----------------------------------------
    Total                     19.121ns (12.089ns logic, 7.032ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_37_cmp_eq0000'
  Clock period: 19.077ns (frequency: 52.418MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               19.077ns (Levels of Logic = 19)
  Source:            Inst_register_file/reg_37_21 (LATCH)
  Destination:       Inst_register_file/reg_37_7 (LATCH)
  Source Clock:      Inst_register_file/reg_37_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_37_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_37_21 to Inst_register_file/reg_37_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_37_21 (Inst_register_file/reg_37_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_940 (Inst_register_file/Mmux__varindex0001_940)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_7_f5_12 (Inst_register_file/Mmux__varindex0001_7_f513)
     MUXF6:I1->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_37_7
    ----------------------------------------
    Total                     19.077ns (12.089ns logic, 6.988ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_38_cmp_eq0000'
  Clock period: 19.121ns (frequency: 52.297MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               19.121ns (Levels of Logic = 19)
  Source:            Inst_register_file/reg_38_21 (LATCH)
  Destination:       Inst_register_file/reg_38_7 (LATCH)
  Source Clock:      Inst_register_file/reg_38_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_38_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_38_21 to Inst_register_file/reg_38_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_38_21 (Inst_register_file/reg_38_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_813 (Inst_register_file/Mmux__varindex0001_813)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_7_f5_12 (Inst_register_file/Mmux__varindex0001_7_f513)
     MUXF6:I1->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_38_7
    ----------------------------------------
    Total                     19.121ns (12.089ns logic, 7.032ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_39_cmp_eq0000'
  Clock period: 19.077ns (frequency: 52.418MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               19.077ns (Levels of Logic = 19)
  Source:            Inst_register_file/reg_39_21 (LATCH)
  Destination:       Inst_register_file/reg_39_7 (LATCH)
  Source Clock:      Inst_register_file/reg_39_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_39_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_39_21 to Inst_register_file/reg_39_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_39_21 (Inst_register_file/reg_39_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_813 (Inst_register_file/Mmux__varindex0001_813)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_7_f5_12 (Inst_register_file/Mmux__varindex0001_7_f513)
     MUXF6:I1->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_39_7
    ----------------------------------------
    Total                     19.077ns (12.089ns logic, 6.988ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_10_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_10_21 (LATCH)
  Destination:       Inst_register_file/reg_10_7 (LATCH)
  Source Clock:      Inst_register_file/reg_10_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_10_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_10_21 to Inst_register_file/reg_10_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_10_21 (Inst_register_file/reg_10_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1253 (Inst_register_file/Mmux__varindex0001_1253)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_39 (Inst_register_file/Mmux__varindex0001_10_f540)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_10_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_register_file/reg_11_cmp_eq0000'
  Clock period: 20.088ns (frequency: 49.780MHz)
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Delay:               20.088ns (Levels of Logic = 21)
  Source:            Inst_register_file/reg_11_21 (LATCH)
  Destination:       Inst_register_file/reg_11_7 (LATCH)
  Source Clock:      Inst_register_file/reg_11_cmp_eq0000 falling
  Destination Clock: Inst_register_file/reg_11_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_11_21 to Inst_register_file/reg_11_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_11_21 (Inst_register_file/reg_11_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1181 (Inst_register_file/Mmux__varindex0001_1181)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_40 (Inst_register_file/Mmux__varindex0001_9_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_11_7
    ----------------------------------------
    Total                     20.088ns (13.131ns logic, 6.957ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_psr_modifier/nzvc_0_not0001'
  Total number of paths / destination ports: 354241 / 4
-------------------------------------------------------------------------
Offset:              24.706ns (Levels of Logic = 21)
  Source:            RST (PAD)
  Destination:       Inst_psr_modifier/nzvc_2 (LATCH)
  Destination Clock: Inst_psr_modifier/nzvc_0_not0001 falling

  Data Path: RST to Inst_psr_modifier/nzvc_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.357  Inst_alu/r<4>405 (R_4_OBUF)
     LUT4:I1->O            1   0.704   0.455  Inst_psr_modifier/nzvc_2_mux0003262 (Inst_psr_modifier/nzvc_2_mux0003262)
     LUT4:I2->O            1   0.704   0.424  Inst_psr_modifier/nzvc_2_mux0003289 (Inst_psr_modifier/nzvc_2_mux0003289)
     LUT4:I3->O            1   0.704   0.000  Inst_psr_modifier/nzvc_2_mux0003303 (Inst_psr_modifier/nzvc_2_mux0003)
     LD:D                      0.308          Inst_psr_modifier/nzvc_2
    ----------------------------------------
    Total                     24.706ns (12.838ns logic, 11.868ns route)
                                       (52.0% logic, 48.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 2048 / 32
-------------------------------------------------------------------------
Offset:              11.425ns (Levels of Logic = 33)
  Source:            RST (PAD)
  Destination:       Inst_npc/sig_31 (FF)
  Destination Clock: CLK rising

  Data Path: RST to Inst_npc/sig_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.465  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT2:I0->O            1   0.704   0.000  Inst_sumDisp22/Madd_R_lut<5> (Inst_sumDisp22/Madd_R_lut<5>)
     MUXCY:S->O            1   0.464   0.000  Inst_sumDisp22/Madd_R_cy<5> (Inst_sumDisp22/Madd_R_cy<5>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<6> (Inst_sumDisp22/Madd_R_cy<6>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<7> (Inst_sumDisp22/Madd_R_cy<7>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<8> (Inst_sumDisp22/Madd_R_cy<8>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<9> (Inst_sumDisp22/Madd_R_cy<9>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<10> (Inst_sumDisp22/Madd_R_cy<10>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<11> (Inst_sumDisp22/Madd_R_cy<11>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<12> (Inst_sumDisp22/Madd_R_cy<12>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<13> (Inst_sumDisp22/Madd_R_cy<13>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<14> (Inst_sumDisp22/Madd_R_cy<14>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<15> (Inst_sumDisp22/Madd_R_cy<15>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<16> (Inst_sumDisp22/Madd_R_cy<16>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<17> (Inst_sumDisp22/Madd_R_cy<17>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<18> (Inst_sumDisp22/Madd_R_cy<18>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<19> (Inst_sumDisp22/Madd_R_cy<19>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<20> (Inst_sumDisp22/Madd_R_cy<20>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<21> (Inst_sumDisp22/Madd_R_cy<21>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<22> (Inst_sumDisp22/Madd_R_cy<22>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<23> (Inst_sumDisp22/Madd_R_cy<23>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<24> (Inst_sumDisp22/Madd_R_cy<24>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<25> (Inst_sumDisp22/Madd_R_cy<25>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<26> (Inst_sumDisp22/Madd_R_cy<26>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<27> (Inst_sumDisp22/Madd_R_cy<27>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<28> (Inst_sumDisp22/Madd_R_cy<28>)
     MUXCY:CI->O           1   0.059   0.000  Inst_sumDisp22/Madd_R_cy<29> (Inst_sumDisp22/Madd_R_cy<29>)
     MUXCY:CI->O           0   0.059   0.000  Inst_sumDisp22/Madd_R_cy<30> (Inst_sumDisp22/Madd_R_cy<30>)
     XORCY:CI->O           1   0.804   0.499  Inst_sumDisp22/Madd_R_xor<31> (aux22<31>)
     LUT3:I1->O            1   0.704   0.000  Inst_MuxPC/Mmux_nPC_324 (Inst_MuxPC/Mmux_nPC_324)
     MUXF5:I1->O           1   0.321   0.000  Inst_MuxPC/Mmux_nPC_2_f5_23 (aux25<31>)
     FDC:D                     0.308          Inst_npc/sig_31
    ----------------------------------------
    Total                     11.425ns (7.406ns logic, 4.019ns route)
                                       (64.8% logic, 35.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_control_unit/wrenDM'
  Total number of paths / destination ports: 15666848 / 32
-------------------------------------------------------------------------
Offset:              25.033ns (Levels of Logic = 23)
  Source:            RST (PAD)
  Destination:       Inst_DataMemory/datoToWr_31 (LATCH)
  Destination Clock: Inst_control_unit/wrenDM rising

  Data Path: RST to Inst_DataMemory/datoToWr_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3_D:I2->O         12   0.704   0.996  Inst_alu/r_cmp_eq00351 (Inst_alu/r_cmp_eq0035)
     LUT4_D:I2->O         13   0.704   1.018  Inst_alu/r<10>192 (Inst_alu/N69)
     LUT4:I2->O            1   0.704   0.499  Inst_alu/r<1>172 (Inst_alu/r<1>172)
     LUT4:I1->O            1   0.704   0.424  Inst_alu/r<1>187_SW0 (N788)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<1>197 (Inst_alu/r<1>197)
     LUT4:I3->O          574   0.704   1.410  Inst_alu/r<1>433 (R_1_OBUF)
     MUXF5:S->O            1   0.739   0.000  Inst_DataMemory/Mmux__varindex0000_8_f5 (Inst_DataMemory/Mmux__varindex0000_8_f5)
     MUXF6:I1->O           1   0.521   0.000  Inst_DataMemory/Mmux__varindex0000_7_f6 (Inst_DataMemory/Mmux__varindex0000_7_f6)
     MUXF7:I1->O           1   0.521   0.000  Inst_DataMemory/Mmux__varindex0000_6_f7 (Inst_DataMemory/Mmux__varindex0000_6_f7)
     MUXF8:I1->O           1   0.521   0.499  Inst_DataMemory/Mmux__varindex0000_5_f8 (Inst_DataMemory/Mmux__varindex0000_5_f8)
     LUT3:I1->O            1   0.704   0.000  Inst_DataMemory/address<5>1 (Inst_DataMemory/_varindex0000<0>)
     LDC_1:D                   0.308          Inst_DataMemory/datoToWr_0
    ----------------------------------------
    Total                     25.033ns (13.697ns logic, 11.336ns route)
                                       (54.7% logic, 45.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_windows_manager/rs1int_cmp_le0000'
  Total number of paths / destination ports: 6 / 4
-------------------------------------------------------------------------
Offset:              5.778ns (Levels of Logic = 3)
  Source:            RST (PAD)
  Destination:       Inst_windows_manager/rs1int_5 (LATCH)
  Destination Clock: Inst_windows_manager/rs1int_cmp_le0000 falling

  Data Path: RST to Inst_windows_manager/rs1int_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.489  RST_IBUF (RST_IBUF)
     LUT3:I1->O           75   0.704   1.355  Inst_instructionMemory/outInstruction<2>11 (Inst_instructionMemory/N17)
     LUT4:I1->O            2   0.704   0.000  Inst_windows_manager/rs1int_5__and00011 (Inst_windows_manager/rs1int_5__and0001)
     LDCP:D                    0.308          Inst_windows_manager/rs1int_5
    ----------------------------------------
    Total                      5.778ns (2.934ns logic, 2.844ns route)
                                       (50.8% logic, 49.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_windows_manager/rs2int_cmp_le0000'
  Total number of paths / destination ports: 6 / 6
-------------------------------------------------------------------------
Offset:              5.778ns (Levels of Logic = 3)
  Source:            RST (PAD)
  Destination:       Inst_windows_manager/rs2int_4 (LATCH)
  Destination Clock: Inst_windows_manager/rs2int_cmp_le0000 falling

  Data Path: RST to Inst_windows_manager/rs2int_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.489  RST_IBUF (RST_IBUF)
     LUT3:I1->O           75   0.704   1.355  Inst_instructionMemory/outInstruction<2>11 (Inst_instructionMemory/N17)
     LUT4:I1->O            2   0.704   0.000  Inst_windows_manager/rs2int_4__and000111 (Inst_windows_manager/rs2int_4__and0001)
     LDCP:D                    0.308          Inst_windows_manager/rs2int_4
    ----------------------------------------
    Total                      5.778ns (2.934ns logic, 2.844ns route)
                                       (50.8% logic, 49.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_windows_manager/rdint_cmp_le0000'
  Total number of paths / destination ports: 8 / 6
-------------------------------------------------------------------------
Offset:              5.874ns (Levels of Logic = 3)
  Source:            RST (PAD)
  Destination:       Inst_windows_manager/rdint_1 (LATCH)
  Destination Clock: Inst_windows_manager/rdint_cmp_le0000 falling

  Data Path: RST to Inst_windows_manager/rdint_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.489  RST_IBUF (RST_IBUF)
     LUT3:I1->O           75   0.704   1.451  Inst_instructionMemory/outInstruction<2>11 (Inst_instructionMemory/N17)
     LUT4:I0->O            6   0.704   0.000  Inst_instructionMemory/outInstruction<26> (aux4<26>)
     LDCP:D                    0.308          Inst_windows_manager/rdint_1
    ----------------------------------------
    Total                      5.874ns (2.934ns logic, 2.940ns route)
                                       (50.0% logic, 50.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_control_unit/Mmux_RFSource_mux0007270'
  Total number of paths / destination ports: 4 / 1
-------------------------------------------------------------------------
Offset:              8.288ns (Levels of Logic = 5)
  Source:            RST (PAD)
  Destination:       Inst_windows_manager/ncwp_signal (LATCH)
  Destination Clock: Inst_control_unit/Mmux_RFSource_mux0007270 falling

  Data Path: RST to Inst_windows_manager/ncwp_signal
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.706  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I0->O           28   0.704   1.340  Inst_instructionMemory/outInstruction<22>21 (aux4<22>)
     LUT4:I1->O            1   0.704   0.455  Inst_windows_manager/ncwp_signal_mux0002_SW1 (N275)
     LUT4:I2->O            1   0.704   0.000  Inst_windows_manager/ncwp_signal_mux0002 (Inst_windows_manager/ncwp_signal_mux0002)
     LD:D                      0.308          Inst_windows_manager/ncwp_signal
    ----------------------------------------
    Total                      8.288ns (4.342ns logic, 3.946ns route)
                                       (52.4% logic, 47.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_control_unit/Aluop_not0001'
  Total number of paths / destination ports: 166 / 12
-------------------------------------------------------------------------
Offset:              10.807ns (Levels of Logic = 7)
  Source:            RST (PAD)
  Destination:       Inst_control_unit/RFSource_0 (LATCH)
  Destination Clock: Inst_control_unit/Aluop_not0001 falling

  Data Path: RST to Inst_control_unit/RFSource_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.489  RST_IBUF (RST_IBUF)
     LUT3:I1->O           75   0.704   1.311  Inst_instructionMemory/outInstruction<2>11 (Inst_instructionMemory/N17)
     LUT4:I2->O           25   0.704   1.435  Inst_instructionMemory/outInstruction<27>1 (aux4<27>)
     LUT3:I0->O            1   0.704   0.595  Inst_control_unit/Mmux_write_enable_mux000722_SW1 (N283)
     LUT4:I0->O            3   0.704   0.610  Inst_control_unit/Mmux_write_enable_mux000722 (Inst_control_unit/N13)
     LUT2:I1->O            1   0.704   0.000  Inst_control_unit/Mmux_RFSource_mux000711 (Inst_control_unit/Mmux_RFSource_mux00071)
     MUXF5:I1->O           1   0.321   0.000  Inst_control_unit/Mmux_RFSource_mux00071_f5 (Inst_control_unit/RFSource_mux0007<0>)
     LD:D                      0.308          Inst_control_unit/RFSource_0
    ----------------------------------------
    Total                     10.807ns (5.367ns logic, 5.440ns route)
                                       (49.7% logic, 50.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_control_unit/RFdest_not0001'
  Total number of paths / destination ports: 2 / 1
-------------------------------------------------------------------------
Offset:              7.777ns (Levels of Logic = 4)
  Source:            RST (PAD)
  Destination:       Inst_control_unit/RFdest (LATCH)
  Destination Clock: Inst_control_unit/RFdest_not0001 falling

  Data Path: RST to Inst_control_unit/RFdest
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.489  RST_IBUF (RST_IBUF)
     LUT3:I1->O           75   0.704   1.311  Inst_instructionMemory/outInstruction<2>11 (Inst_instructionMemory/N17)
     LUT4:I2->O           25   0.704   1.339  Inst_instructionMemory/outInstruction<27>1 (aux4<27>)
     LUT2:I1->O            1   0.704   0.000  Inst_control_unit/Mmux_write_enable_mux0007241 (Inst_control_unit/RFdest_mux0006)
     LD:D                      0.308          Inst_control_unit/RFdest
    ----------------------------------------
    Total                      7.777ns (3.638ns logic, 4.139ns route)
                                       (46.8% logic, 53.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_1_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_1_7 (LATCH)
  Destination Clock: Inst_register_file/reg_1_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_1_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_1_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_12_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_12_7 (LATCH)
  Destination Clock: Inst_register_file/reg_12_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_12_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_12_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_2_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_2_7 (LATCH)
  Destination Clock: Inst_register_file/reg_2_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_2_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_2_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_13_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_13_7 (LATCH)
  Destination Clock: Inst_register_file/reg_13_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_13_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_13_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_3_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_3_7 (LATCH)
  Destination Clock: Inst_register_file/reg_3_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_3_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_3_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_14_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_14_7 (LATCH)
  Destination Clock: Inst_register_file/reg_14_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_14_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_14_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_4_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_4_7 (LATCH)
  Destination Clock: Inst_register_file/reg_4_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_4_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_4_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_15_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_15_7 (LATCH)
  Destination Clock: Inst_register_file/reg_15_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_15_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_15_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_20_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_20_7 (LATCH)
  Destination Clock: Inst_register_file/reg_20_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_20_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_20_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_5_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_5_7 (LATCH)
  Destination Clock: Inst_register_file/reg_5_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_5_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_5_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_16_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_16_7 (LATCH)
  Destination Clock: Inst_register_file/reg_16_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_16_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_16_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_21_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_21_7 (LATCH)
  Destination Clock: Inst_register_file/reg_21_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_21_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_21_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_6_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_6_7 (LATCH)
  Destination Clock: Inst_register_file/reg_6_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_6_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_6_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_17_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_17_7 (LATCH)
  Destination Clock: Inst_register_file/reg_17_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_17_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_17_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_22_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_22_7 (LATCH)
  Destination Clock: Inst_register_file/reg_22_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_22_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_22_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_7_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_7_7 (LATCH)
  Destination Clock: Inst_register_file/reg_7_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_7_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_7_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_18_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_18_7 (LATCH)
  Destination Clock: Inst_register_file/reg_18_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_18_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_18_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_23_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_23_7 (LATCH)
  Destination Clock: Inst_register_file/reg_23_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_23_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_23_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_8_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_8_7 (LATCH)
  Destination Clock: Inst_register_file/reg_8_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_8_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_8_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_19_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_19_7 (LATCH)
  Destination Clock: Inst_register_file/reg_19_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_19_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_19_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_24_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_24_7 (LATCH)
  Destination Clock: Inst_register_file/reg_24_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_24_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_24_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_9_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_9_7 (LATCH)
  Destination Clock: Inst_register_file/reg_9_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_9_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_9_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_25_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_25_7 (LATCH)
  Destination Clock: Inst_register_file/reg_25_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_25_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_25_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_30_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_30_7 (LATCH)
  Destination Clock: Inst_register_file/reg_30_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_30_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_30_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_26_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_26_7 (LATCH)
  Destination Clock: Inst_register_file/reg_26_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_26_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_26_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_31_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_31_7 (LATCH)
  Destination Clock: Inst_register_file/reg_31_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_31_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_31_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_27_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_27_7 (LATCH)
  Destination Clock: Inst_register_file/reg_27_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_27_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_27_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_32_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_32_7 (LATCH)
  Destination Clock: Inst_register_file/reg_32_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_32_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_32_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_33_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_33_7 (LATCH)
  Destination Clock: Inst_register_file/reg_33_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_33_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_33_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_28_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_28_7 (LATCH)
  Destination Clock: Inst_register_file/reg_28_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_28_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_28_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_29_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_29_7 (LATCH)
  Destination Clock: Inst_register_file/reg_29_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_29_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_29_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_34_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_34_7 (LATCH)
  Destination Clock: Inst_register_file/reg_34_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_34_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_34_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_35_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_35_7 (LATCH)
  Destination Clock: Inst_register_file/reg_35_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_35_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_35_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_36_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_36_7 (LATCH)
  Destination Clock: Inst_register_file/reg_36_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_36_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_36_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_37_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_37_7 (LATCH)
  Destination Clock: Inst_register_file/reg_37_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_37_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_37_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_38_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_38_7 (LATCH)
  Destination Clock: Inst_register_file/reg_38_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_38_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_38_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_39_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_39_7 (LATCH)
  Destination Clock: Inst_register_file/reg_39_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_39_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_39_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_10_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_10_7 (LATCH)
  Destination Clock: Inst_register_file/reg_10_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_10_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_10_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Inst_register_file/reg_11_cmp_eq0000'
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Offset:              21.560ns (Levels of Logic = 20)
  Source:            RST (PAD)
  Destination:       Inst_register_file/reg_11_7 (LATCH)
  Destination Clock: Inst_register_file/reg_11_cmp_eq0000 falling

  Data Path: RST to Inst_register_file/reg_11_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.304  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     LUT3:I2->O           24   0.704   1.287  Inst_alu/r_cmp_eq00441 (Inst_alu/r_cmp_eq0044)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_alu/r<10>103_1 (N1086)
     LUT4:I2->O            1   0.704   0.420  Inst_alu/r<7>220 (Inst_alu/r<7>220)
     MUXF5:S->O            1   0.739   0.424  Inst_alu/r<7>222 (Inst_alu/r<7>222)
     LUT4:I3->O            1   0.704   0.424  Inst_alu/r<7>302_SW0_SW0 (N727)
     LUT4_L:I3->LO         1   0.704   0.104  Inst_alu/r<7>302 (Inst_alu/r<7>302)
     LUT4:I3->O            3   0.704   0.531  Inst_alu/r<7>327 (R_7_OBUF)
     MUXF5:S->O           39   0.739   0.000  Inst_MuxDWR/Mmux_DTRF90 (aux10<7>)
     LDCE:D                    0.308          Inst_register_file/reg_11_7
    ----------------------------------------
    Total                     21.560ns (12.169ns logic, 9.391ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_control_unit/Aluop_not0001'
  Total number of paths / destination ports: 5538 / 32
-------------------------------------------------------------------------
Offset:              19.566ns (Levels of Logic = 11)
  Source:            Inst_control_unit/Aluop_4 (LATCH)
  Destination:       R<0> (PAD)
  Source Clock:      Inst_control_unit/Aluop_not0001 falling

  Data Path: Inst_control_unit/Aluop_4 to R<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q              15   0.676   1.192  Inst_control_unit/Aluop_4 (Inst_control_unit/Aluop_4)
     LUT2:I0->O            2   0.704   0.482  Inst_alu/r_or000111 (Inst_alu/N194)
     LUT4:I2->O           34   0.704   1.298  Inst_alu/r_or00041 (Inst_alu/r_or0004)
     LUT3:I2->O           55   0.704   1.444  Inst_alu/r<10>221011 (Inst_alu/N166)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<0>26 (Inst_alu/r<0>26)
     LUT4:I3->O            1   0.704   0.455  Inst_alu/r<0>35 (Inst_alu/r<0>35)
     LUT4:I2->O            1   0.704   0.424  Inst_alu/r<0>59_SW0 (N905)
     LUT4:I3->O            1   0.704   0.499  Inst_alu/r<0>81 (Inst_alu/r<0>81)
     LUT4:I1->O            1   0.704   0.424  Inst_alu/r<0>105 (Inst_alu/r<0>105)
     LUT4:I3->O            2   0.704   0.526  Inst_alu/r<0>220 (Inst_alu/r<0>220)
     LUT4:I1->O         1086   0.704   1.410  Inst_alu/r<0>444 (R_0_OBUF)
     OBUF:I->O                 3.272          R_0_OBUF (R<0>)
    ----------------------------------------
    Total                     19.566ns (10.988ns logic, 8.578ns route)
                                       (56.2% logic, 43.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_windows_manager/rs1int_cmp_le0000'
  Total number of paths / destination ports: 640380 / 32
-------------------------------------------------------------------------
Offset:              21.325ns (Levels of Logic = 17)
  Source:            Inst_windows_manager/rs1int_3 (LATCH)
  Destination:       R<2> (PAD)
  Source Clock:      Inst_windows_manager/rs1int_cmp_le0000 falling

  Data Path: Inst_windows_manager/rs1int_3 to R<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCP:G->Q           512   0.676   1.585  Inst_windows_manager/rs1int_3 (Inst_windows_manager/rs1int_3)
     LUT3:I0->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0000_9 (Inst_register_file/Mmux__varindex0000_9)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0000_8_f5 (Inst_register_file/Mmux__varindex0000_8_f5)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0000_7_f6 (Inst_register_file/Mmux__varindex0000_7_f6)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0000_6_f7 (Inst_register_file/Mmux__varindex0000_6_f7)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0000_5_f8 (Inst_register_file/Mmux__varindex0000_5_f8)
     LUT4:I3->O           59   0.704   1.446  Inst_register_file/crs1<0>1 (aux6<0>)
     LUT2:I0->O            1   0.704   0.000  Inst_alu/Msub_r_addsub0002_lut<0> (Inst_alu/Msub_r_addsub0002_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/Msub_r_addsub0002_cy<0> (Inst_alu/Msub_r_addsub0002_cy<0>)
     XORCY:CI->O           2   0.804   0.447  Inst_alu/Msub_r_addsub0002_xor<1> (Inst_alu/r_addsub0002<1>)
     INV:I->O              1   0.704   0.000  Inst_alu/Msub_r_addsub0003_lut<1>_INV_0 (Inst_alu/Msub_r_addsub0003_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/Msub_r_addsub0003_cy<1> (Inst_alu/Msub_r_addsub0003_cy<1>)
     XORCY:CI->O           1   0.804   0.595  Inst_alu/Msub_r_addsub0003_xor<2> (Inst_alu/r_addsub0003<2>)
     LUT4:I0->O            1   0.704   0.595  Inst_alu/r<2>376 (Inst_alu/r<2>376)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<2>386 (Inst_alu/r<2>386)
     LUT4_D:I3->O          1   0.704   0.455  Inst_alu/r<2>395 (Inst_alu/r<2>395)
     LUT4:I2->O          322   0.704   1.354  Inst_alu/r<2>421 (R_2_OBUF)
     OBUF:I->O                 3.272          R_2_OBUF (R<2>)
    ----------------------------------------
    Total                     21.325ns (14.000ns logic, 7.325ns route)
                                       (65.7% logic, 34.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_32_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              22.161ns (Levels of Logic = 18)
  Source:            Inst_register_file/reg_32_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_32_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_32_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_32_21 (Inst_register_file/reg_32_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1069 (Inst_register_file/Mmux__varindex0001_1069)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_26 (Inst_register_file/Mmux__varindex0001_8_f527)
     MUXF6:I0->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     22.161ns (13.610ns logic, 8.551ns route)
                                       (61.4% logic, 38.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_33_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              22.117ns (Levels of Logic = 18)
  Source:            Inst_register_file/reg_33_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_33_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_33_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_33_21 (Inst_register_file/reg_33_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1069 (Inst_register_file/Mmux__varindex0001_1069)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_26 (Inst_register_file/Mmux__varindex0001_8_f527)
     MUXF6:I0->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     22.117ns (13.610ns logic, 8.507ns route)
                                       (61.5% logic, 38.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_34_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              22.161ns (Levels of Logic = 18)
  Source:            Inst_register_file/reg_34_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_34_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_34_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_34_21 (Inst_register_file/reg_34_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_941 (Inst_register_file/Mmux__varindex0001_941)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_26 (Inst_register_file/Mmux__varindex0001_8_f527)
     MUXF6:I0->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     22.161ns (13.610ns logic, 8.551ns route)
                                       (61.4% logic, 38.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_35_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              22.117ns (Levels of Logic = 18)
  Source:            Inst_register_file/reg_35_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_35_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_35_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_35_21 (Inst_register_file/reg_35_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_941 (Inst_register_file/Mmux__varindex0001_941)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_26 (Inst_register_file/Mmux__varindex0001_8_f527)
     MUXF6:I0->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     22.117ns (13.610ns logic, 8.507ns route)
                                       (61.5% logic, 38.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_36_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              22.161ns (Levels of Logic = 18)
  Source:            Inst_register_file/reg_36_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_36_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_36_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_36_21 (Inst_register_file/reg_36_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_940 (Inst_register_file/Mmux__varindex0001_940)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_7_f5_12 (Inst_register_file/Mmux__varindex0001_7_f513)
     MUXF6:I1->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     22.161ns (13.610ns logic, 8.551ns route)
                                       (61.4% logic, 38.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_37_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              22.117ns (Levels of Logic = 18)
  Source:            Inst_register_file/reg_37_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_37_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_37_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_37_21 (Inst_register_file/reg_37_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_940 (Inst_register_file/Mmux__varindex0001_940)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_7_f5_12 (Inst_register_file/Mmux__varindex0001_7_f513)
     MUXF6:I1->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     22.117ns (13.610ns logic, 8.507ns route)
                                       (61.5% logic, 38.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_38_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              22.161ns (Levels of Logic = 18)
  Source:            Inst_register_file/reg_38_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_38_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_38_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_38_21 (Inst_register_file/reg_38_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_813 (Inst_register_file/Mmux__varindex0001_813)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_7_f5_12 (Inst_register_file/Mmux__varindex0001_7_f513)
     MUXF6:I1->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     22.161ns (13.610ns logic, 8.551ns route)
                                       (61.4% logic, 38.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_39_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              22.117ns (Levels of Logic = 18)
  Source:            Inst_register_file/reg_39_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_39_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_39_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_39_21 (Inst_register_file/reg_39_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_813 (Inst_register_file/Mmux__varindex0001_813)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_7_f5_12 (Inst_register_file/Mmux__varindex0001_7_f513)
     MUXF6:I1->O           1   0.521   0.455  Inst_register_file/Mmux__varindex0001_6_f6_12 (Inst_register_file/Mmux__varindex0001_6_f613)
     LUT4_D:I2->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     22.117ns (13.610ns logic, 8.507ns route)
                                       (61.5% logic, 38.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_8_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_8_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_8_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_8_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_8_21 (Inst_register_file/reg_8_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1313 (Inst_register_file/Mmux__varindex0001_1313)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_11_f5_12 (Inst_register_file/Mmux__varindex0001_11_f513)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_16_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_16_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_16_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_16_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_16_21 (Inst_register_file/reg_16_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1255 (Inst_register_file/Mmux__varindex0001_1255)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_11_f5_12 (Inst_register_file/Mmux__varindex0001_11_f513)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_24_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_24_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_24_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_24_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_24_21 (Inst_register_file/reg_24_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1255 (Inst_register_file/Mmux__varindex0001_1255)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_11_f5_12 (Inst_register_file/Mmux__varindex0001_11_f513)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_1_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_1_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_1_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_1_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_1_21 (Inst_register_file/reg_1_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1254 (Inst_register_file/Mmux__varindex0001_1254)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_40 (Inst_register_file/Mmux__varindex0001_10_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_9_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_9_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_9_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_9_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_9_21 (Inst_register_file/reg_9_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1254 (Inst_register_file/Mmux__varindex0001_1254)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_40 (Inst_register_file/Mmux__varindex0001_10_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_17_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_17_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_17_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_17_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_17_21 (Inst_register_file/reg_17_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1183 (Inst_register_file/Mmux__varindex0001_1183)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_40 (Inst_register_file/Mmux__varindex0001_10_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_25_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_25_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_25_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_25_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_25_21 (Inst_register_file/reg_25_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1183 (Inst_register_file/Mmux__varindex0001_1183)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_40 (Inst_register_file/Mmux__varindex0001_10_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_9_f6_12 (Inst_register_file/Mmux__varindex0001_9_f613)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_2_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_2_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_2_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_2_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_2_21 (Inst_register_file/reg_2_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1253 (Inst_register_file/Mmux__varindex0001_1253)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_39 (Inst_register_file/Mmux__varindex0001_10_f540)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_10_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_10_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_10_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_10_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_10_21 (Inst_register_file/reg_10_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1253 (Inst_register_file/Mmux__varindex0001_1253)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_39 (Inst_register_file/Mmux__varindex0001_10_f540)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_18_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_18_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_18_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_18_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_18_21 (Inst_register_file/reg_18_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1182 (Inst_register_file/Mmux__varindex0001_1182)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_39 (Inst_register_file/Mmux__varindex0001_10_f540)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_26_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_26_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_26_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_26_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_26_21 (Inst_register_file/reg_26_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1182 (Inst_register_file/Mmux__varindex0001_1182)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_39 (Inst_register_file/Mmux__varindex0001_10_f540)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_3_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_3_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_3_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_3_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_3_21 (Inst_register_file/reg_3_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1181 (Inst_register_file/Mmux__varindex0001_1181)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_40 (Inst_register_file/Mmux__varindex0001_9_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_11_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_11_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_11_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_11_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_11_21 (Inst_register_file/reg_11_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1181 (Inst_register_file/Mmux__varindex0001_1181)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_40 (Inst_register_file/Mmux__varindex0001_9_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_19_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_19_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_19_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_19_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_19_21 (Inst_register_file/reg_19_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1068 (Inst_register_file/Mmux__varindex0001_1068)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_40 (Inst_register_file/Mmux__varindex0001_9_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_27_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_27_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_27_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_27_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_27_21 (Inst_register_file/reg_27_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1068 (Inst_register_file/Mmux__varindex0001_1068)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_40 (Inst_register_file/Mmux__varindex0001_9_f541)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_26 (Inst_register_file/Mmux__varindex0001_8_f627)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f7_12 (Inst_register_file/Mmux__varindex0001_7_f713)
     MUXF8:I0->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_4_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_4_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_4_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_4_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_4_21 (Inst_register_file/reg_4_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1252 (Inst_register_file/Mmux__varindex0001_1252)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_38 (Inst_register_file/Mmux__varindex0001_10_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_12_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_12_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_12_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_12_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_12_21 (Inst_register_file/reg_12_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1252 (Inst_register_file/Mmux__varindex0001_1252)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_38 (Inst_register_file/Mmux__varindex0001_10_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_20_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_20_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_20_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_20_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_20_21 (Inst_register_file/reg_20_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1180 (Inst_register_file/Mmux__varindex0001_1180)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_38 (Inst_register_file/Mmux__varindex0001_10_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_28_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_28_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_28_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_28_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_28_21 (Inst_register_file/reg_28_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1180 (Inst_register_file/Mmux__varindex0001_1180)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_10_f5_38 (Inst_register_file/Mmux__varindex0001_10_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_5_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_5_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_5_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_5_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_5_21 (Inst_register_file/reg_5_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1179 (Inst_register_file/Mmux__varindex0001_1179)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_39 (Inst_register_file/Mmux__varindex0001_9_f540)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_13_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_13_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_13_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_13_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_13_21 (Inst_register_file/reg_13_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1179 (Inst_register_file/Mmux__varindex0001_1179)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_39 (Inst_register_file/Mmux__varindex0001_9_f540)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_21_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_21_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_21_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_21_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_21_21 (Inst_register_file/reg_21_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1067 (Inst_register_file/Mmux__varindex0001_1067)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_39 (Inst_register_file/Mmux__varindex0001_9_f540)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_29_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_29_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_29_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_29_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_29_21 (Inst_register_file/reg_29_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1067 (Inst_register_file/Mmux__varindex0001_1067)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_39 (Inst_register_file/Mmux__varindex0001_9_f540)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_8_f6_25 (Inst_register_file/Mmux__varindex0001_8_f626)
     MUXF7:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_6_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_6_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_6_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_6_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_6_21 (Inst_register_file/reg_6_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1178 (Inst_register_file/Mmux__varindex0001_1178)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_38 (Inst_register_file/Mmux__varindex0001_9_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_14_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_14_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_14_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_14_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_14_21 (Inst_register_file/reg_14_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1178 (Inst_register_file/Mmux__varindex0001_1178)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_38 (Inst_register_file/Mmux__varindex0001_9_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_22_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_22_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_22_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_22_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_22_21 (Inst_register_file/reg_22_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1066 (Inst_register_file/Mmux__varindex0001_1066)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_38 (Inst_register_file/Mmux__varindex0001_9_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_30_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_30_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_30_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_30_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_30_21 (Inst_register_file/reg_30_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1066 (Inst_register_file/Mmux__varindex0001_1066)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_9_f5_38 (Inst_register_file/Mmux__varindex0001_9_f539)
     MUXF6:I0->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_7_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_7_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_7_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_7_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_7_21 (Inst_register_file/reg_7_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1065 (Inst_register_file/Mmux__varindex0001_1065)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_25 (Inst_register_file/Mmux__varindex0001_8_f526)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_15_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_15_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_15_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_15_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_15_21 (Inst_register_file/reg_15_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_1065 (Inst_register_file/Mmux__varindex0001_1065)
     MUXF5:I0->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_25 (Inst_register_file/Mmux__varindex0001_8_f526)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_23_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.172ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_23_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_23_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_23_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.610  Inst_register_file/reg_23_21 (Inst_register_file/reg_23_21)
     LUT3:I1->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_939 (Inst_register_file/Mmux__varindex0001_939)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_25 (Inst_register_file/Mmux__varindex0001_8_f526)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.172ns (14.652ns logic, 8.520ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_register_file/reg_31_cmp_eq0000'
  Total number of paths / destination ports: 89132 / 32
-------------------------------------------------------------------------
Offset:              23.128ns (Levels of Logic = 20)
  Source:            Inst_register_file/reg_31_21 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_register_file/reg_31_cmp_eq0000 falling

  Data Path: Inst_register_file/reg_31_21 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             3   0.676   0.566  Inst_register_file/reg_31_21 (Inst_register_file/reg_31_21)
     LUT3:I2->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_939 (Inst_register_file/Mmux__varindex0001_939)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_25 (Inst_register_file/Mmux__varindex0001_8_f526)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.128ns (14.652ns logic, 8.476ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 1096205 / 32
-------------------------------------------------------------------------
Offset:              23.955ns (Levels of Logic = 18)
  Source:            Inst_pc/sig_5 (FF)
  Destination:       R<4> (PAD)
  Source Clock:      CLK rising

  Data Path: Inst_pc/sig_5 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             24   0.591   1.427  Inst_pc/sig_5 (Inst_pc/sig_5)
     LUT4:I0->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     23.955ns (13.063ns logic, 10.892ns route)
                                       (54.5% logic, 45.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_windows_manager/rs2int_cmp_le0000'
  Total number of paths / destination ports: 2835768 / 32
-------------------------------------------------------------------------
Offset:              24.147ns (Levels of Logic = 20)
  Source:            Inst_windows_manager/rs2int_3 (LATCH)
  Destination:       R<4> (PAD)
  Source Clock:      Inst_windows_manager/rs2int_cmp_le0000 falling

  Data Path: Inst_windows_manager/rs2int_3 to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCP:G->Q           512   0.676   1.585  Inst_windows_manager/rs2int_3 (Inst_windows_manager/rs2int_3)
     LUT3:I0->O            1   0.704   0.000  Inst_register_file/Mmux__varindex0001_939 (Inst_register_file/Mmux__varindex0001_939)
     MUXF5:I1->O           1   0.321   0.000  Inst_register_file/Mmux__varindex0001_8_f5_25 (Inst_register_file/Mmux__varindex0001_8_f526)
     MUXF6:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_7_f6_12 (Inst_register_file/Mmux__varindex0001_7_f613)
     MUXF7:I1->O           1   0.521   0.000  Inst_register_file/Mmux__varindex0001_6_f7_12 (Inst_register_file/Mmux__varindex0001_6_f713)
     MUXF8:I1->O           1   0.521   0.424  Inst_register_file/Mmux__varindex0001_5_f8_12 (Inst_register_file/Mmux__varindex0001_5_f813)
     LUT4_D:I3->LO         1   0.704   0.135  Inst_mux32b/O<21>_F (N1064)
     LUT3:I2->O            6   0.704   0.748  Inst_mux32b/O<21>1 (aux9<21>)
     LUT4:I1->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<1> (Inst_alu/r_cmp_eq00221_wg_lut<1>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     24.147ns (14.652ns logic, 9.495ns route)
                                       (60.7% logic, 39.3% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 290455 / 32
-------------------------------------------------------------------------
Delay:               24.600ns (Levels of Logic = 19)
  Source:            RST (PAD)
  Destination:       R<4> (PAD)

  Data Path: RST to R<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O          3519   1.218   1.445  RST_IBUF (RST_IBUF)
     LUT4:I2->O            3   0.704   0.610  Inst_instructionMemory/outInstruction<5>11 (Inst_instructionMemory/N31)
     LUT4:I1->O          120   0.704   1.369  Inst_instructionMemory/outInstruction<5>1 (aux4<10>)
     LUT4:I1->O            1   0.704   0.000  Inst_mux32b/O<24>1 (Inst_mux32b/O<24>)
     MUXF5:I1->O           7   0.321   0.883  Inst_mux32b/O<24>_f5 (aux9<24>)
     LUT3:I0->O            1   0.704   0.000  Inst_alu/r_cmp_eq00221_wg_lut<0> (Inst_alu/r_cmp_eq00221_wg_lut<0>)
     MUXCY:S->O            1   0.464   0.000  Inst_alu/r_cmp_eq00221_wg_cy<0> (Inst_alu/r_cmp_eq00221_wg_cy<0>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<1> (Inst_alu/r_cmp_eq00221_wg_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<2> (Inst_alu/r_cmp_eq00221_wg_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Inst_alu/r_cmp_eq00221_wg_cy<3> (Inst_alu/r_cmp_eq00221_wg_cy<3>)
     MUXCY:CI->O           1   0.459   0.455  Inst_alu/r_cmp_eq00221_wg_cy<4> (Inst_alu/r_cmp_eq00221_wg_cy<4>)
     LUT3:I2->O           55   0.704   1.269  Inst_alu/r_cmp_eq00221_wg_cy<6>1 (Inst_alu/r_cmp_eq00221_wg_cy<6>)
     MUXF5:S->O           16   0.739   1.069  Inst_alu/r_cmp_eq00411 (Inst_alu/r_cmp_eq0041)
     LUT4_D:I2->O         19   0.704   1.089  Inst_alu/r<10>1310 (Inst_alu/N45)
     LUT4:I3->O            1   0.704   0.595  Inst_alu/r<4>282 (Inst_alu/r<4>282)
     LUT4:I0->O            1   0.704   0.424  Inst_alu/r<4>292 (Inst_alu/r<4>292)
     LUT4_D:I3->O          1   0.704   0.424  Inst_alu/r<4>379 (Inst_alu/r<4>379)
     LUT4:I3->O           81   0.704   1.278  Inst_alu/r<4>405 (R_4_OBUF)
     OBUF:I->O                 3.272          R_4_OBUF (R<4>)
    ----------------------------------------
    Total                     24.600ns (13.690ns logic, 10.910ns route)
                                       (55.7% logic, 44.3% route)

=========================================================================


Total REAL time to Xst completion: 397.00 secs
Total CPU time to Xst completion: 396.71 secs
 
--> 

Total memory usage is 997316 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  177 (   0 filtered)
Number of infos    :   13 (   0 filtered)