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I use Verilog Some IDE will automaticly create a header block use multiple '/'. More than three / will affect the part after this
/
eg: no problem:
begin // begin end end begin // / / / / / / begin end end begin/*////*/ begin end end
problem level 1:
begin //// begin //no colored begin //no problem end end end begin/*/////*/ begin //no colored begin //no problem end end end
problem level 2:
begin ////// begin //no colored begin //no colored end end end begin/*///////*/ begin //no colored begin //no colored end end end
also :
//* begin //no colored begin //no colored begin //no colored end end end
The text was updated successfully, but these errors were encountered:
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I use Verilog
Some IDE will automaticly create a header block use multiple '/'.
More than three
/
will affect the part after thiseg:
no problem:
problem level 1:
problem level 2:
also :
The text was updated successfully, but these errors were encountered: