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DDR3.csv
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#Generated by MIG Version 1.9
#Coregen 14.5 - Build Number P.20131013 on ÖÜÎå ÈýÔÂ 3 14:34:39 2017
#FPGA Part xc7k325t-ffg900-2
IO Bank,Pin Number,Signal Name,IO Standard,Direction,Slew Rate,DiffPair Type,DiffPair Signal
34,AD3,ddr3_dq[0],SSTL15_T_DCI,INOUT,FAST,,
34,AC2,ddr3_dq[1],SSTL15_T_DCI,INOUT,FAST,,
34,AC1,ddr3_dq[2],SSTL15_T_DCI,INOUT,FAST,,
34,AC5,ddr3_dq[3],SSTL15_T_DCI,INOUT,FAST,,
34,AC4,ddr3_dq[4],SSTL15_T_DCI,INOUT,FAST,,
34,AD6,ddr3_dq[5],SSTL15_T_DCI,INOUT,FAST,,
34,AE6,ddr3_dq[6],SSTL15_T_DCI,INOUT,FAST,,
34,AC7,ddr3_dq[7],SSTL15_T_DCI,INOUT,FAST,,
34,AF2,ddr3_dq[8],SSTL15_T_DCI,INOUT,FAST,,
34,AE1,ddr3_dq[9],SSTL15_T_DCI,INOUT,FAST,,
34,AF1,ddr3_dq[10],SSTL15_T_DCI,INOUT,FAST,,
34,AE4,ddr3_dq[11],SSTL15_T_DCI,INOUT,FAST,,
34,AE3,ddr3_dq[12],SSTL15_T_DCI,INOUT,FAST,,
34,AE5,ddr3_dq[13],SSTL15_T_DCI,INOUT,FAST,,
34,AF5,ddr3_dq[14],SSTL15_T_DCI,INOUT,FAST,,
34,AF6,ddr3_dq[15],SSTL15_T_DCI,INOUT,FAST,,
34,AH4,ddr3_dq[16],SSTL15_T_DCI,INOUT,FAST,,
34,AJ4,ddr3_dq[17],SSTL15_T_DCI,INOUT,FAST,,
34,AH6,ddr3_dq[18],SSTL15_T_DCI,INOUT,FAST,,
34,AH5,ddr3_dq[19],SSTL15_T_DCI,INOUT,FAST,,
34,AJ2,ddr3_dq[20],SSTL15_T_DCI,INOUT,FAST,,
34,AJ1,ddr3_dq[21],SSTL15_T_DCI,INOUT,FAST,,
34,AK1,ddr3_dq[22],SSTL15_T_DCI,INOUT,FAST,,
34,AJ3,ddr3_dq[23],SSTL15_T_DCI,INOUT,FAST,,
34,AF7,ddr3_dq[24],SSTL15_T_DCI,INOUT,FAST,,
34,AG7,ddr3_dq[25],SSTL15_T_DCI,INOUT,FAST,,
34,AJ6,ddr3_dq[26],SSTL15_T_DCI,INOUT,FAST,,
34,AK6,ddr3_dq[27],SSTL15_T_DCI,INOUT,FAST,,
34,AJ8,ddr3_dq[28],SSTL15_T_DCI,INOUT,FAST,,
34,AK8,ddr3_dq[29],SSTL15_T_DCI,INOUT,FAST,,
34,AK5,ddr3_dq[30],SSTL15_T_DCI,INOUT,FAST,,
34,AK4,ddr3_dq[31],SSTL15_T_DCI,INOUT,FAST,,
32,AK15,ddr3_dq[32],SSTL15_T_DCI,INOUT,FAST,,
32,AG15,ddr3_dq[33],SSTL15_T_DCI,INOUT,FAST,,
32,AH15,ddr3_dq[34],SSTL15_T_DCI,INOUT,FAST,,
32,AF15,ddr3_dq[35],SSTL15_T_DCI,INOUT,FAST,,
32,AG14,ddr3_dq[36],SSTL15_T_DCI,INOUT,FAST,,
32,AH17,ddr3_dq[37],SSTL15_T_DCI,INOUT,FAST,,
32,AJ17,ddr3_dq[38],SSTL15_T_DCI,INOUT,FAST,,
32,AE16,ddr3_dq[39],SSTL15_T_DCI,INOUT,FAST,,
32,AK19,ddr3_dq[40],SSTL15_T_DCI,INOUT,FAST,,
32,AG19,ddr3_dq[41],SSTL15_T_DCI,INOUT,FAST,,
32,AH19,ddr3_dq[42],SSTL15_T_DCI,INOUT,FAST,,
32,AD19,ddr3_dq[43],SSTL15_T_DCI,INOUT,FAST,,
32,AE19,ddr3_dq[44],SSTL15_T_DCI,INOUT,FAST,,
32,AF18,ddr3_dq[45],SSTL15_T_DCI,INOUT,FAST,,
32,AG18,ddr3_dq[46],SSTL15_T_DCI,INOUT,FAST,,
32,AF17,ddr3_dq[47],SSTL15_T_DCI,INOUT,FAST,,
32,AD18,ddr3_dq[48],SSTL15_T_DCI,INOUT,FAST,,
32,AE18,ddr3_dq[49],SSTL15_T_DCI,INOUT,FAST,,
32,AD17,ddr3_dq[50],SSTL15_T_DCI,INOUT,FAST,,
32,AD16,ddr3_dq[51],SSTL15_T_DCI,INOUT,FAST,,
32,AB18,ddr3_dq[52],SSTL15_T_DCI,INOUT,FAST,,
32,AB19,ddr3_dq[53],SSTL15_T_DCI,INOUT,FAST,,
32,AC19,ddr3_dq[54],SSTL15_T_DCI,INOUT,FAST,,
32,AB17,ddr3_dq[55],SSTL15_T_DCI,INOUT,FAST,,
32,AA15,ddr3_dq[56],SSTL15_T_DCI,INOUT,FAST,,
32,AB15,ddr3_dq[57],SSTL15_T_DCI,INOUT,FAST,,
32,AC14,ddr3_dq[58],SSTL15_T_DCI,INOUT,FAST,,
32,AD14,ddr3_dq[59],SSTL15_T_DCI,INOUT,FAST,,
32,AA17,ddr3_dq[60],SSTL15_T_DCI,INOUT,FAST,,
32,AA16,ddr3_dq[61],SSTL15_T_DCI,INOUT,FAST,,
32,Y16,ddr3_dq[62],SSTL15_T_DCI,INOUT,FAST,,
32,Y15,ddr3_dq[63],SSTL15_T_DCI,INOUT,FAST,,
33,AA12,ddr3_addr[14],SSTL15,OUT,FAST,,
33,AB12,ddr3_addr[13],SSTL15,OUT,FAST,,
33,AA8,ddr3_addr[12],SSTL15,OUT,FAST,,
33,AB8,ddr3_addr[11],SSTL15,OUT,FAST,,
33,Y11,ddr3_addr[10],SSTL15,OUT,FAST,,
33,Y10,ddr3_addr[9],SSTL15,OUT,FAST,,
33,AA11,ddr3_addr[8],SSTL15,OUT,FAST,,
33,AA10,ddr3_addr[7],SSTL15,OUT,FAST,,
33,AA13,ddr3_addr[6],SSTL15,OUT,FAST,,
33,AB13,ddr3_addr[5],SSTL15,OUT,FAST,,
33,AB10,ddr3_addr[4],SSTL15,OUT,FAST,,
33,AC10,ddr3_addr[3],SSTL15,OUT,FAST,,
33,AD8,ddr3_addr[2],SSTL15,OUT,FAST,,
33,AE8,ddr3_addr[1],SSTL15,OUT,FAST,,
33,AC12,ddr3_addr[0],SSTL15,OUT,FAST,,
33,AC11,ddr3_ba[2],SSTL15,OUT,FAST,,
33,AD9,ddr3_ba[1],SSTL15,OUT,FAST,,
33,AE9,ddr3_ba[0],SSTL15,OUT,FAST,,
33,AE11,ddr3_ras_n,SSTL15,OUT,FAST,,
33,AF11,ddr3_cas_n,SSTL15,OUT,FAST,,
33,AD12,ddr3_we_n,SSTL15,OUT,FAST,,
34,AG5,ddr3_reset_n,LVCMOS15,OUT,FAST,,
33,AJ9,ddr3_cke[0],SSTL15,OUT,FAST,,
33,AK9,ddr3_odt[0],SSTL15,OUT,FAST,,
33,AD11,ddr3_cs_n[0],SSTL15,OUT,FAST,,
34,AD4,ddr3_dm[0],SSTL15,OUT,FAST,,
34,AF3,ddr3_dm[1],SSTL15,OUT,FAST,,
34,AH2,ddr3_dm[2],SSTL15,OUT,FAST,,
34,AF8,ddr3_dm[3],SSTL15,OUT,FAST,,
32,AK16,ddr3_dm[4],SSTL15,OUT,FAST,,
32,AJ19,ddr3_dm[5],SSTL15,OUT,FAST,,
32,AA18,ddr3_dm[6],SSTL15,OUT,FAST,,
32,AE15,ddr3_dm[7],SSTL15,OUT,FAST,,
33,AE10,sys_clk_p,DIFF_SSTL15,IN,,P,sys_clk_n
33,AF10,sys_clk_n,DIFF_SSTL15,IN,,N,sys_clk_p
14,R28,clk_ref_p,LVDS_25,IN,,,
14,T28,clk_ref_n,LVDS_25,IN,,,
34,AD2,ddr3_dqs_p[0],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[0]
34,AD1,ddr3_dqs_n[0],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[0]
34,AG4,ddr3_dqs_p[1],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[1]
34,AG3,ddr3_dqs_n[1],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[1]
34,AG2,ddr3_dqs_p[2],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[2]
34,AH1,ddr3_dqs_n[2],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[2]
34,AH7,ddr3_dqs_p[3],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[3]
34,AJ7,ddr3_dqs_n[3],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[3]
32,AH16,ddr3_dqs_p[4],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[4]
32,AJ16,ddr3_dqs_n[4],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[4]
32,AJ18,ddr3_dqs_p[5],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[5]
32,AK18,ddr3_dqs_n[5],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[5]
32,Y19,ddr3_dqs_p[6],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[6]
32,Y18,ddr3_dqs_n[6],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[6]
32,AC16,ddr3_dqs_p[7],DIFF_SSTL15_T_DCI,INOUT,FAST,P,ddr3_dqs_n[7]
32,AC15,ddr3_dqs_n[7],DIFF_SSTL15_T_DCI,INOUT,FAST,N,ddr3_dqs_p[7]
33,AB9,ddr3_ck_p[0],DIFF_SSTL15,OUT,FAST,P,ddr3_ck_n[0]
33,AC9,ddr3_ck_n[0],DIFF_SSTL15,OUT,FAST,N,ddr3_ck_p[0]