diff --git a/hw-latest/fpga/fpga_configuration.tcl b/hw-latest/fpga/fpga_configuration.tcl index e278017225..29fbeb345f 100644 --- a/hw-latest/fpga/fpga_configuration.tcl +++ b/hw-latest/fpga/fpga_configuration.tcl @@ -1,9 +1,11 @@ # Clean and create output directory. set outputDir ./caliptra_build set packageDir $outputDir/caliptra_package +set adapterDir $outputDir/soc_adapter_package file delete -force $outputDir file mkdir $outputDir file mkdir $packageDir +file mkdir $adapterDir # Path to rtl set rtlDir ../caliptra-rtl @@ -34,6 +36,28 @@ if {$GUI} { start_gui } +# Create a project to package a module to connect SOC signals to +create_project soc_adapter_package_project $outputDir -part xczu7ev-ffvc1156-2-e +# Add source +add_files [ glob ./src/soc_adapter.v ] + +# Package IP +ipx::package_project -root_dir $adapterDir -vendor design -library user -taxonomy /UserIP -import_files -set_current false +ipx::unload_core $adapterDir/component.xml +ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $adapterDir $adapterDir/component.xml +ipx::infer_bus_interfaces xilinx.com:interface:axi:1.0 [ipx::current_core] +set_property core_revision 1 [ipx::current_core] +ipx::update_source_project_archive -component [ipx::current_core] +ipx::create_xgui_files [ipx::current_core] +ipx::update_checksums [ipx::current_core] +ipx::check_integrity [ipx::current_core] +ipx::save_core [ipx::current_core] +# Close temp project +close_project +# Close soc_adapter_package_project +close_project + + # Create a project to package Caliptra. # Packaging Caliptra allows Vivado to recognize the APB bus as an endpoint for the memory map. create_project caliptra_package_project $outputDir -part xczu7ev-ffvc1156-2-e @@ -148,7 +172,7 @@ close_project create_project caliptra_fpga_project $outputDir -part xczu7ev-ffvc1156-2-e # Include the packaged IP -set_property ip_repo_paths "$packageDir ./src/caliptra_soc_1_0" [current_project] +set_property ip_repo_paths "$packageDir $adapterDir" [current_project] update_ip_catalog # Create SOC block design @@ -166,7 +190,7 @@ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnec set_property CONFIG.NUM_MI {3} [get_bd_cells axi_interconnect_0] # Add caliptra_soc -create_bd_cell -type ip -vlnv design:user:caliptra_soc:1.0 caliptra_soc_0 +create_bd_cell -type ip -vlnv design:user:soc_adapter:1.0 caliptra_soc_0 # Add AXI APB Bridge for Caliptra create_bd_cell -type ip -vlnv xilinx.com:ip:axi_apb_bridge:3.0 axi_apb_bridge_0 @@ -194,18 +218,19 @@ set_property location {4 1335 456} [get_bd_cells caliptra_package_top_0] # Create interface connections connect_bd_intf_net -intf_net axi_apb_bridge_0_APB_M [get_bd_intf_pins axi_apb_bridge_0/APB_M] [get_bd_intf_pins caliptra_package_top_0/s_apb] -connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins caliptra_soc_0/S00_AXI] +connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins caliptra_soc_0/interface_aximm] connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_apb_bridge_0/AXI4_LITE] [get_bd_intf_pins axi_interconnect_0/M01_AXI] connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD] connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M02_AXI] connect_bd_intf_net [get_bd_intf_pins caliptra_package_top_0/axi_bram] [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] # Create port connections -connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins axi_apb_bridge_0/s_axi_aresetn] [get_bd_pins caliptra_soc_0/s00_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] -connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_apb_bridge_0/s_axi_aclk] [get_bd_pins caliptra_soc_0/s00_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins caliptra_package_top_0/core_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] +connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins axi_apb_bridge_0/s_axi_aresetn] [get_bd_pins caliptra_soc_0/rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] +connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_apb_bridge_0/s_axi_aclk] [get_bd_pins caliptra_soc_0/aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins caliptra_package_top_0/core_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins caliptra_package_top_0/gpio_in] [get_bd_pins caliptra_soc_0/gpio_out] connect_bd_net [get_bd_pins caliptra_package_top_0/gpio_out] [get_bd_pins caliptra_soc_0/gpio_in] connect_bd_net [get_bd_pins caliptra_package_top_0/pauser] [get_bd_pins caliptra_soc_0/pauser] +connect_bd_net [get_bd_pins caliptra_package_top_0/cptra_obf_key] [get_bd_pins caliptra_soc_0/cptra_obf_key] connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] connect_bd_net [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] @@ -213,10 +238,9 @@ connect_bd_net [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins proc_sys connect_bd_net [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] connect_bd_net [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] -connect_bd_net [get_bd_pins caliptra_package_top_0/cptra_obf_key] [get_bd_pins caliptra_soc_0/cptra_obf_key] # Create address segments -assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs caliptra_soc_0/S00_AXI/S00_AXI_reg] -force +assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs caliptra_soc_0/interface_aximm/reg0] -force assign_bd_address -offset 0x82000000 -range 0x00008000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force assign_bd_address -offset 0x90000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs caliptra_package_top_0/s_apb/Reg] -force diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/bd/bd.tcl b/hw-latest/fpga/src/caliptra_soc_1_0/bd/bd.tcl deleted file mode 100644 index 4804aeba80..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/bd/bd.tcl +++ /dev/null @@ -1,86 +0,0 @@ - -proc init { cellpath otherInfo } { - - set cell_handle [get_bd_cells $cellpath] - set all_busif [get_bd_intf_pins $cellpath/*] - set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] - set full_sbusif_list [list ] - - foreach busif $all_busif { - if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { - set busif_param_list [list] - set busif_name [get_property NAME $busif] - if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { - continue - } - foreach tparam $axi_standard_param_list { - lappend busif_param_list "C_${busif_name}_${tparam}" - } - bd::mark_propagate_only $cell_handle $busif_param_list - } - } -} - - -proc pre_propagate {cellpath otherInfo } { - - set cell_handle [get_bd_cells $cellpath] - set all_busif [get_bd_intf_pins $cellpath/*] - set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] - - foreach busif $all_busif { - if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { - continue - } - if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { - continue - } - - set busif_name [get_property NAME $busif] - foreach tparam $axi_standard_param_list { - set busif_param_name "C_${busif_name}_${tparam}" - - set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] - set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] - - if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { - if { $val_on_cell != "" } { - set_property CONFIG.${tparam} $val_on_cell $busif - } - } - } - } -} - - -proc propagate {cellpath otherInfo } { - - set cell_handle [get_bd_cells $cellpath] - set all_busif [get_bd_intf_pins $cellpath/*] - set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] - - foreach busif $all_busif { - if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { - continue - } - if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { - continue - } - - set busif_name [get_property NAME $busif] - foreach tparam $axi_standard_param_list { - set busif_param_name "C_${busif_name}_${tparam}" - - set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] - set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] - - if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { - #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. - if { $val_on_cell_intf_pin != "" } { - set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle - } - } - } - } -} - diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/component.xml b/hw-latest/fpga/src/caliptra_soc_1_0/component.xml deleted file mode 100644 index 3d22a25b31..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/component.xml +++ /dev/null @@ -1,894 +0,0 @@ - - - design - user - caliptra_soc - 1.0 - - - S00_AXI - - - - - - - - - AWADDR - - - s00_axi_awaddr - - - - - AWPROT - - - s00_axi_awprot - - - - - AWVALID - - - s00_axi_awvalid - - - - - AWREADY - - - s00_axi_awready - - - - - WDATA - - - s00_axi_wdata - - - - - WSTRB - - - s00_axi_wstrb - - - - - WVALID - - - s00_axi_wvalid - - - - - WREADY - - - s00_axi_wready - - - - - BRESP - - - s00_axi_bresp - - - - - BVALID - - - s00_axi_bvalid - - - - - BREADY - - - s00_axi_bready - - - - - ARADDR - - - s00_axi_araddr - - - - - ARPROT - - - s00_axi_arprot - - - - - ARVALID - - - s00_axi_arvalid - - - - - ARREADY - - - s00_axi_arready - - - - - RDATA - - - s00_axi_rdata - - - - - RRESP - - - s00_axi_rresp - - - - - RVALID - - - s00_axi_rvalid - - - - - RREADY - - - s00_axi_rready - - - - - - WIZ_DATA_WIDTH - 32 - - - WIZ_NUM_REG - 16 - - - SUPPORTS_NARROW_BURST - 0 - - - - - S00_AXI_RST - - - - - - - RST - - - s00_axi_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - S00_AXI_CLK - - - - - - - CLK - - - s00_axi_aclk - - - - - - ASSOCIATED_BUSIF - S00_AXI - - - ASSOCIATED_RESET - s00_axi_aresetn - - - - - - - S00_AXI - - S00_AXI_reg - 0 - 4096 - 32 - register - - - OFFSET_BASE_PARAM - C_S00_AXI_BASEADDR - - - OFFSET_HIGH_PARAM - C_S00_AXI_HIGHADDR - - - - - - - - - xilinx_verilogsynthesis - Verilog Synthesis - verilogSource:vivado.xilinx.com:synthesis - verilog - caliptra_soc_v1_0 - - xilinx_verilogsynthesis_view_fileset - - - - viewChecksum - 9e1fcefd - - - - - xilinx_verilogbehavioralsimulation - Verilog Simulation - verilogSource:vivado.xilinx.com:simulation - verilog - caliptra_soc_v1_0 - - xilinx_verilogbehavioralsimulation_view_fileset - - - - viewChecksum - 9e1fcefd - - - - - xilinx_softwaredriver - Software Driver - :vivado.xilinx.com:sw.driver - - xilinx_softwaredriver_view_fileset - - - - viewChecksum - 62a7488d - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - 080b65eb - - - - - bd_tcl - Block Diagram - :vivado.xilinx.com:block.diagram - - bd_tcl_view_fileset - - - - viewChecksum - 45a2f450 - - - - - - - gpio_in - - in - - 31 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - gpio_out - - out - - 31 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - pauser - - out - - 31 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - cptra_obf_key - - out - - 255 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_aclk - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_aresetn - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_awaddr - - in - - 5 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_awprot - - in - - 2 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_awvalid - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_awready - - out - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_wdata - - in - - 31 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_wstrb - - in - - 3 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_wvalid - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_wready - - out - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_bresp - - out - - 1 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_bvalid - - out - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_bready - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_araddr - - in - - 5 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_arprot - - in - - 2 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_arvalid - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_arready - - out - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_rdata - - out - - 31 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_rresp - - out - - 1 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_rvalid - - out - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - s00_axi_rready - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - - C_S00_AXI_DATA_WIDTH - C S00 AXI DATA WIDTH - Width of S_AXI data bus - 32 - - - C_S00_AXI_ADDR_WIDTH - C S00 AXI ADDR WIDTH - Width of S_AXI address bus - 6 - - - - - - choice_list_6fc15197 - 32 - - - choice_list_74b5137e - ACTIVE_HIGH - ACTIVE_LOW - - - choice_pairs_ce1226b1 - 1 - 0 - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/caliptra_soc_v1_0_S00_AXI.v - verilogSource - - - hdl/caliptra_soc_v1_0.v - verilogSource - CHECKSUM_1cf73c9b - - - - xilinx_verilogbehavioralsimulation_view_fileset - - hdl/caliptra_soc_v1_0_S00_AXI.v - verilogSource - - - hdl/caliptra_soc_v1_0.v - verilogSource - - - - xilinx_softwaredriver_view_fileset - - drivers/caliptra_soc_v1_0/data/caliptra_soc.mdd - mdd - driver_mdd - - - drivers/caliptra_soc_v1_0/data/caliptra_soc.tcl - tclSource - driver_tcl - - - drivers/caliptra_soc_v1_0/src/Makefile - driver_src - - - drivers/caliptra_soc_v1_0/src/caliptra_soc.h - cSource - driver_src - - - drivers/caliptra_soc_v1_0/src/caliptra_soc.c - cSource - driver_src - - - drivers/caliptra_soc_v1_0/src/caliptra_soc_selftest.c - cSource - driver_src - - - - xilinx_xpgui_view_fileset - - xgui/caliptra_soc_v1_0.tcl - tclSource - CHECKSUM_080b65eb - XGUI_VERSION_2 - - - - bd_tcl_view_fileset - - bd/bd.tcl - tclSource - - - - Registers for Caliptra SOC signals - - - C_S00_AXI_DATA_WIDTH - C S00 AXI DATA WIDTH - Width of S_AXI data bus - 32 - - - - false - - - - - - C_S00_AXI_ADDR_WIDTH - C S00 AXI ADDR WIDTH - Width of S_AXI address bus - 6 - - - - false - - - - - - C_S00_AXI_BASEADDR - C S00 AXI BASEADDR - 0xFFFFFFFF - - - - false - - - - - - C_S00_AXI_HIGHADDR - C S00 AXI HIGHADDR - 0x00000000 - - - - false - - - - - - Component_Name - caliptra_soc_v1_0 - - - - - - zynquplus - - - AXI_Peripheral - - caliptra_soc_v1.0 - 2 - 2023-06-28T21:21:03Z - - - 2022.2 - - - - - - - - - diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/data/caliptra_soc.mdd b/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/data/caliptra_soc.mdd deleted file mode 100644 index 6cd8cec49d..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/data/caliptra_soc.mdd +++ /dev/null @@ -1,10 +0,0 @@ - - -OPTION psf_version = 2.1; - -BEGIN DRIVER caliptra_soc - OPTION supported_peripherals = (caliptra_soc); - OPTION copyfiles = all; - OPTION VERSION = 1.0; - OPTION NAME = caliptra_soc; -END DRIVER diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/data/caliptra_soc.tcl b/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/data/caliptra_soc.tcl deleted file mode 100644 index ea75dfb578..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/data/caliptra_soc.tcl +++ /dev/null @@ -1,5 +0,0 @@ - - -proc generate {drv_handle} { - xdefine_include_file $drv_handle "xparameters.h" "caliptra_soc" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" -} diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/src/Makefile b/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/src/Makefile deleted file mode 100644 index cc075ada17..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/src/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -INCLUDEFILES=*.h -LIBSOURCES=*.c -OUTS = *.o - -libs: - echo "Compiling caliptra_soc..." - $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} - make clean - -include: - ${CP} $(INCLUDEFILES) $(INCLUDEDIR) - -clean: - rm -rf ${OUTS} diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/src/caliptra_soc.c b/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/src/caliptra_soc.c deleted file mode 100644 index a81c477554..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/src/caliptra_soc.c +++ /dev/null @@ -1,7 +0,0 @@ -// Licensed under the Apache-2.0 license - - -/***************************** Include Files *******************************/ -#include "caliptra_soc.h" - -/************************** Function Definitions ***************************/ diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/src/caliptra_soc.h b/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/src/caliptra_soc.h deleted file mode 100644 index c6d62a2f2e..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/src/caliptra_soc.h +++ /dev/null @@ -1,80 +0,0 @@ -// Licensed under the Apache-2.0 license - -#ifndef CALIPTRA_SOC_H -#define CALIPTRA_SOC_H - - -/****************** Include Files ********************/ -#include "xil_types.h" -#include "xstatus.h" - -#define CALIPTRA_SOC_S00_AXI_SLV_REG0_OFFSET 0 -#define CALIPTRA_SOC_S00_AXI_SLV_REG1_OFFSET 4 -#define CALIPTRA_SOC_S00_AXI_SLV_REG2_OFFSET 8 -#define CALIPTRA_SOC_S00_AXI_SLV_REG3_OFFSET 12 - - -/**************************** Type Definitions *****************************/ -/** - * - * Write a value to a CALIPTRA_SOC register. A 32 bit write is performed. - * If the component is implemented in a smaller width, only the least - * significant data is written. - * - * @param BaseAddress is the base address of the CALIPTRA_SOCdevice. - * @param RegOffset is the register offset from the base to write to. - * @param Data is the data written to the register. - * - * @return None. - * - * @note - * C-style signature: - * void CALIPTRA_SOC_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) - * - */ -#define CALIPTRA_SOC_mWriteReg(BaseAddress, RegOffset, Data) \ - Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) - -/** - * - * Read a value from a CALIPTRA_SOC register. A 32 bit read is performed. - * If the component is implemented in a smaller width, only the least - * significant data is read from the register. The most significant data - * will be read as 0. - * - * @param BaseAddress is the base address of the CALIPTRA_SOC device. - * @param RegOffset is the register offset from the base to write to. - * - * @return Data is the data from the register. - * - * @note - * C-style signature: - * u32 CALIPTRA_SOC_mReadReg(u32 BaseAddress, unsigned RegOffset) - * - */ -#define CALIPTRA_SOC_mReadReg(BaseAddress, RegOffset) \ - Xil_In32((BaseAddress) + (RegOffset)) - -/************************** Function Prototypes ****************************/ -/** - * - * Run a self-test on the driver/device. Note this may be a destructive test if - * resets of the device are performed. - * - * If the hardware system is not built correctly, this function may never - * return to the caller. - * - * @param baseaddr_p is the base address of the CALIPTRA_SOC instance to be worked on. - * - * @return - * - * - XST_SUCCESS if all self-test code passed - * - XST_FAILURE if any self-test code failed - * - * @note Caching must be turned off for this function to work. - * @note Self test may fail if data memory and device are not on the same bus. - * - */ -XStatus CALIPTRA_SOC_Reg_SelfTest(void * baseaddr_p); - -#endif // CALIPTRA_SOC_H diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/src/caliptra_soc_selftest.c b/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/src/caliptra_soc_selftest.c deleted file mode 100644 index 24aa797359..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/drivers/caliptra_soc_v1_0/src/caliptra_soc_selftest.c +++ /dev/null @@ -1,61 +0,0 @@ -// Licensed under the Apache-2.0 license - -/***************************** Include Files *******************************/ -#include "caliptra_soc.h" -#include "xparameters.h" -#include "stdio.h" -#include "xil_io.h" - -/************************** Constant Definitions ***************************/ -#define READ_WRITE_MUL_FACTOR 0x10 - -/************************** Function Definitions ***************************/ -/** - * - * Run a self-test on the driver/device. Note this may be a destructive test if - * resets of the device are performed. - * - * If the hardware system is not built correctly, this function may never - * return to the caller. - * - * @param baseaddr_p is the base address of the CALIPTRA_SOCinstance to be worked on. - * - * @return - * - * - XST_SUCCESS if all self-test code passed - * - XST_FAILURE if any self-test code failed - * - * @note Caching must be turned off for this function to work. - * @note Self test may fail if data memory and device are not on the same bus. - * - */ -XStatus CALIPTRA_SOC_Reg_SelfTest(void * baseaddr_p) -{ - u32 baseaddr; - int write_loop_index; - int read_loop_index; - int Index; - - baseaddr = (u32) baseaddr_p; - - xil_printf("******************************\n\r"); - xil_printf("* User Peripheral Self Test\n\r"); - xil_printf("******************************\n\n\r"); - - /* - * Write to user logic slave module register(s) and read back - */ - xil_printf("User logic slave module test...\n\r"); - - for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) - CALIPTRA_SOC_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); - for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) - if ( CALIPTRA_SOC_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ - xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); - return XST_FAILURE; - } - - xil_printf(" - slave register write/read passed\n\n\r"); - - return XST_SUCCESS; -} diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/example_designs/bfm_design/caliptra_soc_v1_0_tb.sv b/hw-latest/fpga/src/caliptra_soc_1_0/example_designs/bfm_design/caliptra_soc_v1_0_tb.sv deleted file mode 100644 index 57ebca83bd..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/example_designs/bfm_design/caliptra_soc_v1_0_tb.sv +++ /dev/null @@ -1,197 +0,0 @@ - -`timescale 1ns / 1ps -`include "caliptra_soc_v1_0_tb_include.svh" - -import axi_vip_pkg::*; -import caliptra_soc_v1_0_bfm_1_master_0_0_pkg::*; - -module caliptra_soc_v1_0_tb(); - - -xil_axi_uint error_cnt = 0; -xil_axi_uint comparison_cnt = 0; -axi_transaction wr_transaction; -axi_transaction rd_transaction; -axi_monitor_transaction mst_monitor_transaction; -axi_monitor_transaction master_moniter_transaction_queue[$]; -xil_axi_uint master_moniter_transaction_queue_size =0; -axi_monitor_transaction mst_scb_transaction; -axi_monitor_transaction passthrough_monitor_transaction; -axi_monitor_transaction passthrough_master_moniter_transaction_queue[$]; -xil_axi_uint passthrough_master_moniter_transaction_queue_size =0; -axi_monitor_transaction passthrough_mst_scb_transaction; -axi_monitor_transaction passthrough_slave_moniter_transaction_queue[$]; -xil_axi_uint passthrough_slave_moniter_transaction_queue_size =0; -axi_monitor_transaction passthrough_slv_scb_transaction; -axi_monitor_transaction slv_monitor_transaction; -axi_monitor_transaction slave_moniter_transaction_queue[$]; -xil_axi_uint slave_moniter_transaction_queue_size =0; -axi_monitor_transaction slv_scb_transaction; -xil_axi_uint mst_agent_verbosity = 0; -xil_axi_uint slv_agent_verbosity = 0; -xil_axi_uint passthrough_agent_verbosity = 0; -bit clock; -bit reset; -integer result_slave; -bit [31:0] S00_AXI_test_data[3:0]; - localparam LC_AXI_BURST_LENGTH = 8; - localparam LC_AXI_DATA_WIDTH = 32; -task automatic COMPARE_DATA; - input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected; - input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual; - begin - if (expected === 'hx || actual === 'hx) begin - $display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); - result_slave = 0; $stop; - end - if (actual != expected) begin - $display("TESTBENCH ERROR! Data expected is not equal to actual.", " expected = 0x%h",expected, " actual = 0x%h",actual); - result_slave = 0; - $stop; - end - else - begin - $display("TESTBENCH Passed! Data expected is equal to actual.", - " expected = 0x%h",expected, " actual = 0x%h",actual); - end - end -endtask -integer i; -integer j; -xil_axi_uint trans_cnt_before_switch = 48; -xil_axi_uint passthrough_cmd_switch_cnt = 0; -event passthrough_mastermode_start_event; -event passthrough_mastermode_end_event; -event passthrough_slavemode_end_event; -xil_axi_uint mtestID; -xil_axi_ulong mtestADDR; -xil_axi_len_t mtestBurstLength; -xil_axi_size_t mtestDataSize; -xil_axi_burst_t mtestBurstType; -xil_axi_lock_t mtestLOCK; -xil_axi_cache_t mtestCacheType = 0; -xil_axi_prot_t mtestProtectionType = 3'b000; -xil_axi_region_t mtestRegion = 4'b000; -xil_axi_qos_t mtestQOS = 4'b000; -xil_axi_data_beat dbeat; -xil_axi_data_beat [255:0] mtestWUSER; -xil_axi_data_beat mtestAWUSER = 'h0; -xil_axi_data_beat mtestARUSER = 0; -xil_axi_data_beat [255:0] mtestRUSER; -xil_axi_uint mtestBUSER = 0; -xil_axi_resp_t mtestBresp; -xil_axi_resp_t[255:0] mtestRresp; -bit [63:0] mtestWDataL; -bit [63:0] mtestRDataL; -axi_transaction pss_wr_transaction; -axi_transaction pss_rd_transaction; -axi_transaction reactive_transaction; -axi_transaction rd_payload_transaction; -axi_transaction wr_rand; -axi_transaction rd_rand; -axi_transaction wr_reactive; -axi_transaction rd_reactive; -axi_transaction wr_reactive2; -axi_transaction rd_reactive2; -axi_ready_gen bready_gen; -axi_ready_gen rready_gen; -axi_ready_gen awready_gen; -axi_ready_gen wready_gen; -axi_ready_gen arready_gen; -axi_ready_gen bready_gen2; -axi_ready_gen rready_gen2; -axi_ready_gen awready_gen2; -axi_ready_gen wready_gen2; -axi_ready_gen arready_gen2; -xil_axi_payload_byte data_mem[xil_axi_ulong]; -caliptra_soc_v1_0_bfm_1_master_0_0_mst_t mst_agent_0; - - `BD_WRAPPER DUT( - .ARESETN(reset), - .ACLK(clock) - ); - -initial begin - mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms - mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE); - mst_agent_0.set_agent_tag("Master VIP"); - mst_agent_0.set_verbosity(mst_agent_verbosity); - mst_agent_0.start_master(); - $timeformat (-12, 1, " ps", 1); - end - initial begin - reset <= 1'b0; - #200ns; - reset <= 1'b1; - repeat (5) @(negedge clock); - end - always #5 clock <= ~clock; - initial begin - S_AXI_TEST ( ); - - #1ns; - $finish; - end -task automatic S_AXI_TEST; -begin -#1; - $display("Sequential write transfers example similar to AXI BFM WRITE_BURST method starts"); - mtestID = 0; - mtestADDR = 64'h00000000; - mtestBurstLength = 0; - mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); - mtestBurstType = XIL_AXI_BURST_TYPE_INCR; - mtestLOCK = XIL_AXI_ALOCK_NOLOCK; - mtestCacheType = 0; - mtestProtectionType = 0; - mtestRegion = 0; - mtestQOS = 0; - result_slave = 1; - mtestWDataL[31:0] = 32'h00000001; - for(int i = 0; i < 4;i++) begin - S00_AXI_test_data[i] <= mtestWDataL[31:0]; - mst_agent_0.AXI4LITE_WRITE_BURST( - mtestADDR, - mtestProtectionType, - mtestWDataL, - mtestBresp - ); - mtestWDataL[31:0] = mtestWDataL[31:0] + 1; - mtestADDR = mtestADDR + 64'h4; - end - $display("Sequential write transfers example similar to AXI BFM WRITE_BURST method completes"); - $display("Sequential read transfers example similar to AXI BFM READ_BURST method starts"); - mtestID = 0; - mtestADDR = 64'h00000000; - mtestBurstLength = 0; - mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); - mtestBurstType = XIL_AXI_BURST_TYPE_INCR; - mtestLOCK = XIL_AXI_ALOCK_NOLOCK; - mtestCacheType = 0; - mtestProtectionType = 0; - mtestRegion = 0; - mtestQOS = 0; - for(int i = 0; i < 4;i++) begin - mst_agent_0.AXI4LITE_READ_BURST( - mtestADDR, - mtestProtectionType, - mtestRDataL, - mtestRresp - ); - mtestADDR = mtestADDR + 64'h4; - COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL); - end - $display("Sequential read transfers example similar to AXI BFM READ_BURST method completes"); - $display("Sequential read transfers example similar to AXI VIP READ_BURST method completes"); - $display("---------------------------------------------------------"); - $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); - if ( result_slave ) begin - $display("PTGEN_TEST: PASSED!"); - end else begin - $display("PTGEN_TEST: FAILED!"); - end - $display("---------------------------------------------------------"); - end -endtask - -endmodule diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/example_designs/bfm_design/design.tcl b/hw-latest/fpga/src/caliptra_soc_1_0/example_designs/bfm_design/design.tcl deleted file mode 100644 index 16021bbcfa..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/example_designs/bfm_design/design.tcl +++ /dev/null @@ -1,88 +0,0 @@ -proc create_ipi_design { offsetfile design_name } { - create_bd_design $design_name - open_bd_design $design_name - - # Create Clock and Reset Ports - set ACLK [ create_bd_port -dir I -type clk ACLK ] - set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK - set ARESETN [ create_bd_port -dir I -type rst ARESETN ] - set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN - set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK - - # Create instance: caliptra_soc_0, and set properties - set caliptra_soc_0 [ create_bd_cell -type ip -vlnv design:user:caliptra_soc:1.0 caliptra_soc_0] - - # Create instance: master_0, and set properties - set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip master_0] - set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0 - - # Create interface connections - connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins caliptra_soc_0/S00_AXI] - - # Create port connections - connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins caliptra_soc_0/S00_AXI_ACLK] - connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins caliptra_soc_0/S00_AXI_ARESETN] -set_property target_simulator XSim [current_project] -set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1] - - # Auto assign address - assign_bd_address - - # Copy all address to interface_address.vh file - set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]] - upvar 1 $offsetfile offset_file - set offset_file "${bd_path}/caliptra_soc_v1_0_tb_include.svh" - set fp [open $offset_file "w"] - puts $fp "`ifndef caliptra_soc_v1_0_tb_include_vh_" - puts $fp "`define caliptra_soc_v1_0_tb_include_vh_\n" - puts $fp "//Configuration current bd names" - puts $fp "`define BD_NAME ${design_name}" - puts $fp "`define BD_INST_NAME ${design_name}_i" - puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n" - puts $fp "//Configuration address parameters" - - puts $fp "`endif" - close $fp -} - -set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores design:user:caliptra_soc:1.0]]]] -set test_bench_file ${ip_path}/example_designs/bfm_design/caliptra_soc_v1_0_tb.sv -set interface_address_vh_file "" - -# Set IP Repository and Update IP Catalogue -set repo_paths [get_property ip_repo_paths [current_fileset]] -if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { - set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] - update_ip_catalog -} - -set design_name "" -set all_bd {} -set all_bd_files [get_files *.bd -quiet] -foreach file $all_bd_files { -set file_name [string range $file [expr {[string last "/" $file] + 1}] end] -set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] -lappend all_bd $bd_name -} - -for { set i 1 } { 1 } { incr i } { - set design_name "caliptra_soc_v1_0_bfm_${i}" - if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { - break - } -} - -create_ipi_design interface_address_vh_file ${design_name} -validate_bd_design - -set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] -import_files -force -norecurse $wrapper_file - -set_property SOURCE_SET sources_1 [get_filesets sim_1] -import_files -fileset sim_1 -norecurse -force $test_bench_file -remove_files -quiet -fileset sim_1 caliptra_soc_v1_0_tb_include.vh -import_files -fileset sim_1 -norecurse -force $interface_address_vh_file -set_property top caliptra_soc_v1_0_tb [get_filesets sim_1] -set_property top_lib {} [get_filesets sim_1] -set_property top_file {} [get_filesets sim_1] -launch_simulation -simset sim_1 -mode behavioral diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/example_designs/debug_hw_design/caliptra_soc_v1_0_hw_test.tcl b/hw-latest/fpga/src/caliptra_soc_1_0/example_designs/debug_hw_design/caliptra_soc_v1_0_hw_test.tcl deleted file mode 100644 index fa00d19d9d..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/example_designs/debug_hw_design/caliptra_soc_v1_0_hw_test.tcl +++ /dev/null @@ -1,45 +0,0 @@ -# Runtime Tcl commands to interact with - caliptra_soc_v1_0 - -# Sourcing design address info tcl -set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd -source ${bd_path}/caliptra_soc_v1_0_include.tcl - -# jtag axi master interface hardware name, change as per your design. -set jtag_axi_master hw_axi_1 -set ec 0 - -# hw test script -# Delete all previous axis transactions -if { [llength [get_hw_axi_txns -quiet]] } { - delete_hw_axi_txn [get_hw_axi_txns -quiet] -} - - -# Test all lite slaves. -set wdata_1 abcd1234 - -# Test: S00_AXI -# Create a write transaction at s00_axi_addr address -create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1 -# Create a read transaction at s00_axi_addr address -create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr -# Initiate transactions -run_hw_axi r_s00_axi_addr -run_hw_axi w_s00_axi_addr -run_hw_axi r_s00_axi_addr -set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]] -# Compare read data -if { $rdata_tmp == $wdata_1 } { - puts "Data comparison test pass for - S00_AXI" -} else { - puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp" - inc ec -} - -# Check error flag -if { $ec == 0 } { - puts "PTGEN_TEST: PASSED!" -} else { - puts "PTGEN_TEST: FAILED!" -} - diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/example_designs/debug_hw_design/design.tcl b/hw-latest/fpga/src/caliptra_soc_1_0/example_designs/debug_hw_design/design.tcl deleted file mode 100644 index 68cc1c65a2..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/example_designs/debug_hw_design/design.tcl +++ /dev/null @@ -1,118 +0,0 @@ - -proc create_ipi_design { offsetfile design_name } { - - create_bd_design $design_name - open_bd_design $design_name - - # Create and configure Clock/Reset - create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0 - create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0 - - #Constraints will be provided manually while pin planning. - create_bd_port -dir I -type rst reset_rtl - set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl] - connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl] - connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset] - set external_reset_port reset_rtl - create_bd_port -dir I -type clk clock_rtl - connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl] - set external_clock_port clock_rtl - - #Avoid IPI DRC, make clock port synchronous to reset - if { $external_clock_port ne "" && $external_reset_port ne "" } { - set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port] - } - - # Connect other sys_reset pins - connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1] - connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked] - - # Create instance: caliptra_soc_0, and set properties - set caliptra_soc_0 [ create_bd_cell -type ip -vlnv design:user:caliptra_soc:1.0 caliptra_soc_0 ] - - # Create instance: jtag_axi_0, and set properties - set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ] - set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0] - connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1] - connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] - - # Create instance: axi_peri_interconnect, and set properties - set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ] - connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1] - connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn] - set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect - connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1] - connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] - connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI] - - set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect - connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1] - connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] - - # Connect all clock & reset of caliptra_soc_0 slave interfaces.. - connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins caliptra_soc_0/S00_AXI] - connect_bd_net [get_bd_pins caliptra_soc_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1] - connect_bd_net [get_bd_pins caliptra_soc_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] - - - # Auto assign address - assign_bd_address - - # Copy all address to caliptra_soc_v1_0_include.tcl file - set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd - upvar 1 $offsetfile offset_file - set offset_file "${bd_path}/caliptra_soc_v1_0_include.tcl" - set fp [open $offset_file "w"] - puts $fp "# Configuration address parameters" - - set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_caliptra_soc_0_S00_AXI_* ]] - puts $fp "set s00_axi_addr ${offset}" - - close $fp -} - -# Set IP Repository and Update IP Catalogue -set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores design:user:caliptra_soc:1.0]]]] -set hw_test_file ${ip_path}/example_designs/debug_hw_design/caliptra_soc_v1_0_hw_test.tcl - -set repo_paths [get_property ip_repo_paths [current_fileset]] -if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { - set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] - update_ip_catalog -} - -set design_name "" -set all_bd {} -set all_bd_files [get_files *.bd -quiet] -foreach file $all_bd_files { -set file_name [string range $file [expr {[string last "/" $file] + 1}] end] -set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] -lappend all_bd $bd_name -} - -for { set i 1 } { 1 } { incr i } { - set design_name "caliptra_soc_v1_0_hw_${i}" - if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { - break - } -} - -set intf_address_include_file "" -create_ipi_design intf_address_include_file ${design_name} -save_bd_design -validate_bd_design - -set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] -import_files -force -norecurse $wrapper_file - -puts "-------------------------------------------------------------------------------------------------" -puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, " -puts " please perform following steps to test design in targeted board." -puts "1. Generate bitstream" -puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target" -puts "3. Download generated bitstream" -puts "4. Run generated hardware test using below command, this invokes basic read/write operation" -puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0" -puts " : source -notrace ${hw_test_file}" -puts "-------------------------------------------------------------------------------------------------" - diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/hdl/caliptra_soc_v1_0.v b/hw-latest/fpga/src/caliptra_soc_1_0/hdl/caliptra_soc_v1_0.v deleted file mode 100644 index 1d8c87055b..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/hdl/caliptra_soc_v1_0.v +++ /dev/null @@ -1,85 +0,0 @@ - -`timescale 1 ns / 1 ps - - module caliptra_soc_v1_0 # - ( - // Users to add parameters here - - // User parameters ends - // Do not modify the parameters beyond this line - - // Parameters of Axi Slave Bus Interface S00_AXI - parameter integer C_S00_AXI_DATA_WIDTH = 32, - parameter integer C_S00_AXI_ADDR_WIDTH = 6 - ) - ( - // Users to add ports here - input wire [31:0] gpio_in, - output wire [31:0] gpio_out, - output wire [31:0] pauser, - output wire [255:0] cptra_obf_key, - - // User ports ends - // Do not modify the ports beyond this line - - - // Ports of Axi Slave Bus Interface S00_AXI - input wire s00_axi_aclk, - input wire s00_axi_aresetn, - input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr, - input wire [2 : 0] s00_axi_awprot, - input wire s00_axi_awvalid, - output wire s00_axi_awready, - input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata, - input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb, - input wire s00_axi_wvalid, - output wire s00_axi_wready, - output wire [1 : 0] s00_axi_bresp, - output wire s00_axi_bvalid, - input wire s00_axi_bready, - input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr, - input wire [2 : 0] s00_axi_arprot, - input wire s00_axi_arvalid, - output wire s00_axi_arready, - output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata, - output wire [1 : 0] s00_axi_rresp, - output wire s00_axi_rvalid, - input wire s00_axi_rready - ); -// Instantiation of Axi Bus Interface S00_AXI - caliptra_soc_v1_0_S00_AXI # ( - .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH), - .C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH) - ) caliptra_soc_v1_0_S00_AXI_inst ( - .S_AXI_ACLK(s00_axi_aclk), - .S_AXI_ARESETN(s00_axi_aresetn), - .S_AXI_AWADDR(s00_axi_awaddr), - .S_AXI_AWPROT(s00_axi_awprot), - .S_AXI_AWVALID(s00_axi_awvalid), - .S_AXI_AWREADY(s00_axi_awready), - .S_AXI_WDATA(s00_axi_wdata), - .S_AXI_WSTRB(s00_axi_wstrb), - .S_AXI_WVALID(s00_axi_wvalid), - .S_AXI_WREADY(s00_axi_wready), - .S_AXI_BRESP(s00_axi_bresp), - .S_AXI_BVALID(s00_axi_bvalid), - .S_AXI_BREADY(s00_axi_bready), - .S_AXI_ARADDR(s00_axi_araddr), - .S_AXI_ARPROT(s00_axi_arprot), - .S_AXI_ARVALID(s00_axi_arvalid), - .S_AXI_ARREADY(s00_axi_arready), - .S_AXI_RDATA(s00_axi_rdata), - .S_AXI_RRESP(s00_axi_rresp), - .S_AXI_RVALID(s00_axi_rvalid), - .S_AXI_RREADY(s00_axi_rready), - .gpio_in(gpio_in), - .gpio_out(gpio_out), - .pauser(pauser), - .cptra_obf_key(cptra_obf_key) - ); - - // Add user logic here - - // User logic ends - - endmodule diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/hdl/caliptra_soc_v1_0_S00_AXI.v b/hw-latest/fpga/src/caliptra_soc_1_0/hdl/caliptra_soc_v1_0_S00_AXI.v deleted file mode 100644 index a3a5710a21..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/hdl/caliptra_soc_v1_0_S00_AXI.v +++ /dev/null @@ -1,506 +0,0 @@ - -`timescale 1 ns / 1 ps - - module caliptra_soc_v1_0_S00_AXI # - ( - // Users to add parameters here - - // User parameters ends - // Do not modify the parameters beyond this line - - // Width of S_AXI data bus - parameter integer C_S_AXI_DATA_WIDTH = 32, - // Width of S_AXI address bus - parameter integer C_S_AXI_ADDR_WIDTH = 6 - ) - ( - // Users to add ports here - input wire [31:0] gpio_in, - output wire [31:0] gpio_out, - output wire [31:0] pauser, - output wire [255:0] cptra_obf_key, - - // User ports ends - // Do not modify the ports beyond this line - - // Global Clock Signal - input wire S_AXI_ACLK, - // Global Reset Signal. This Signal is Active LOW - input wire S_AXI_ARESETN, - // Write address (issued by master, acceped by Slave) - input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR, - // Write channel Protection type. This signal indicates the - // privilege and security level of the transaction, and whether - // the transaction is a data access or an instruction access. - input wire [2 : 0] S_AXI_AWPROT, - // Write address valid. This signal indicates that the master signaling - // valid write address and control information. - input wire S_AXI_AWVALID, - // Write address ready. This signal indicates that the slave is ready - // to accept an address and associated control signals. - output wire S_AXI_AWREADY, - // Write data (issued by master, acceped by Slave) - input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA, - // Write strobes. This signal indicates which byte lanes hold - // valid data. There is one write strobe bit for each eight - // bits of the write data bus. - input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB, - // Write valid. This signal indicates that valid write - // data and strobes are available. - input wire S_AXI_WVALID, - // Write ready. This signal indicates that the slave - // can accept the write data. - output wire S_AXI_WREADY, - // Write response. This signal indicates the status - // of the write transaction. - output wire [1 : 0] S_AXI_BRESP, - // Write response valid. This signal indicates that the channel - // is signaling a valid write response. - output wire S_AXI_BVALID, - // Response ready. This signal indicates that the master - // can accept a write response. - input wire S_AXI_BREADY, - // Read address (issued by master, acceped by Slave) - input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR, - // Protection type. This signal indicates the privilege - // and security level of the transaction, and whether the - // transaction is a data access or an instruction access. - input wire [2 : 0] S_AXI_ARPROT, - // Read address valid. This signal indicates that the channel - // is signaling valid read address and control information. - input wire S_AXI_ARVALID, - // Read address ready. This signal indicates that the slave is - // ready to accept an address and associated control signals. - output wire S_AXI_ARREADY, - // Read data (issued by slave) - output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA, - // Read response. This signal indicates the status of the - // read transfer. - output wire [1 : 0] S_AXI_RRESP, - // Read valid. This signal indicates that the channel is - // signaling the required read data. - output wire S_AXI_RVALID, - // Read ready. This signal indicates that the master can - // accept the read data and response information. - input wire S_AXI_RREADY - ); - - // AXI4LITE signals - reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; - reg axi_awready; - reg axi_wready; - reg [1 : 0] axi_bresp; - reg axi_bvalid; - reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; - reg axi_arready; - reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; - reg [1 : 0] axi_rresp; - reg axi_rvalid; - - // Example-specific design signals - // local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH - // ADDR_LSB is used for addressing 32/64 bit registers/memories - // ADDR_LSB = 2 for 32 bits (n downto 2) - // ADDR_LSB = 3 for 64 bits (n downto 3) - localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; - localparam integer OPT_MEM_ADDR_BITS = 3; - //---------------------------------------------- - //-- Signals for user logic register space example - //------------------------------------------------ - //-- Number of Slave Registers 12 - reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; - reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; - reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; - reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; - reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4; - reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; - reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; - reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; - reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; - reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9; - reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10; - reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11; - wire slv_reg_rden; - wire slv_reg_wren; - reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; - integer byte_index; - reg aw_en; - - // I/O Connections assignments - - assign S_AXI_AWREADY = axi_awready; - assign S_AXI_WREADY = axi_wready; - assign S_AXI_BRESP = axi_bresp; - assign S_AXI_BVALID = axi_bvalid; - assign S_AXI_ARREADY = axi_arready; - assign S_AXI_RDATA = axi_rdata; - assign S_AXI_RRESP = axi_rresp; - assign S_AXI_RVALID = axi_rvalid; - // Implement axi_awready generation - // axi_awready is asserted for one S_AXI_ACLK clock cycle when both - // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is - // de-asserted when reset is low. - - always @( posedge S_AXI_ACLK ) - begin - if ( S_AXI_ARESETN == 1'b0 ) - begin - axi_awready <= 1'b0; - aw_en <= 1'b1; - end - else - begin - if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) - begin - // slave is ready to accept write address when - // there is a valid write address and write data - // on the write address and data bus. This design - // expects no outstanding transactions. - axi_awready <= 1'b1; - aw_en <= 1'b0; - end - else if (S_AXI_BREADY && axi_bvalid) - begin - aw_en <= 1'b1; - axi_awready <= 1'b0; - end - else - begin - axi_awready <= 1'b0; - end - end - end - - // Implement axi_awaddr latching - // This process is used to latch the address when both - // S_AXI_AWVALID and S_AXI_WVALID are valid. - - always @( posedge S_AXI_ACLK ) - begin - if ( S_AXI_ARESETN == 1'b0 ) - begin - axi_awaddr <= 0; - end - else - begin - if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) - begin - // Write Address latching - axi_awaddr <= S_AXI_AWADDR; - end - end - end - - // Implement axi_wready generation - // axi_wready is asserted for one S_AXI_ACLK clock cycle when both - // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is - // de-asserted when reset is low. - - always @( posedge S_AXI_ACLK ) - begin - if ( S_AXI_ARESETN == 1'b0 ) - begin - axi_wready <= 1'b0; - end - else - begin - if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en ) - begin - // slave is ready to accept write data when - // there is a valid write address and write data - // on the write address and data bus. This design - // expects no outstanding transactions. - axi_wready <= 1'b1; - end - else - begin - axi_wready <= 1'b0; - end - end - end - - // Implement memory mapped register select and write logic generation - // The write data is accepted and written to memory mapped registers when - // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to - // select byte enables of slave registers while writing. - // These registers are cleared when reset (active low) is applied. - // Slave register write enable is asserted when valid address and data are available - // and the slave is ready to accept the write address and write data. - assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID; - - always @( posedge S_AXI_ACLK ) - begin - if ( S_AXI_ARESETN == 1'b0 ) - begin - slv_reg0 <= 0; - slv_reg1 <= 0; - slv_reg2 <= 0; - slv_reg3 <= 0; - slv_reg4 <= 0; - slv_reg5 <= 0; - slv_reg6 <= 0; - slv_reg7 <= 0; - slv_reg8 <= 0; - slv_reg9 <= 0; - slv_reg10 <= 0; - slv_reg11 <= 0; - end - else begin - if (slv_reg_wren) - begin - case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) - 4'h0: - for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) - if ( S_AXI_WSTRB[byte_index] == 1 ) begin - // Respective byte enables are asserted as per write strobes - // Slave register 0 - slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; - end - 4'h1: - for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) - if ( S_AXI_WSTRB[byte_index] == 1 ) begin - // Respective byte enables are asserted as per write strobes - // Slave register 1 - slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; - end - 4'h2: - for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) - if ( S_AXI_WSTRB[byte_index] == 1 ) begin - // Respective byte enables are asserted as per write strobes - // Slave register 2 - slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; - end - 4'h3: - for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) - if ( S_AXI_WSTRB[byte_index] == 1 ) begin - // Respective byte enables are asserted as per write strobes - // Slave register 3 - slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; - end - 4'h4: - for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) - if ( S_AXI_WSTRB[byte_index] == 1 ) begin - // Respective byte enables are asserted as per write strobes - // Slave register 4 - slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; - end - 4'h5: - for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) - if ( S_AXI_WSTRB[byte_index] == 1 ) begin - // Respective byte enables are asserted as per write strobes - // Slave register 5 - slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; - end - 4'h6: - for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) - if ( S_AXI_WSTRB[byte_index] == 1 ) begin - // Respective byte enables are asserted as per write strobes - // Slave register 6 - slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; - end - 4'h7: - for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) - if ( S_AXI_WSTRB[byte_index] == 1 ) begin - // Respective byte enables are asserted as per write strobes - // Slave register 7 - slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; - end - 4'h8: - for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) - if ( S_AXI_WSTRB[byte_index] == 1 ) begin - // Respective byte enables are asserted as per write strobes - // Slave register 8 - slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; - end - 4'h9: - for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) - if ( S_AXI_WSTRB[byte_index] == 1 ) begin - // Respective byte enables are asserted as per write strobes - // Slave register 9 - slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; - end - 4'ha: - for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) - if ( S_AXI_WSTRB[byte_index] == 1 ) begin - // Respective byte enables are asserted as per write strobes - // Slave register 10 - slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; - end - 4'hb: - for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) - if ( S_AXI_WSTRB[byte_index] == 1 ) begin - // Respective byte enables are asserted as per write strobes - // Slave register 11 - slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; - end - default : begin - slv_reg0 <= slv_reg0; - slv_reg1 <= slv_reg1; - slv_reg2 <= slv_reg2; - slv_reg3 <= slv_reg3; - slv_reg4 <= slv_reg4; - slv_reg5 <= slv_reg5; - slv_reg6 <= slv_reg6; - slv_reg7 <= slv_reg7; - slv_reg8 <= slv_reg8; - slv_reg9 <= slv_reg9; - slv_reg10 <= slv_reg10; - slv_reg11 <= slv_reg11; - end - endcase - end - end - end - - // Implement write response logic generation - // The write response and response valid signals are asserted by the slave - // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. - // This marks the acceptance of address and indicates the status of - // write transaction. - - always @( posedge S_AXI_ACLK ) - begin - if ( S_AXI_ARESETN == 1'b0 ) - begin - axi_bvalid <= 0; - axi_bresp <= 2'b0; - end - else - begin - if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID) - begin - // indicates a valid write response is available - axi_bvalid <= 1'b1; - axi_bresp <= 2'b0; // 'OKAY' response - end // work error responses in future - else - begin - if (S_AXI_BREADY && axi_bvalid) - //check if bready is asserted while bvalid is high) - //(there is a possibility that bready is always asserted high) - begin - axi_bvalid <= 1'b0; - end - end - end - end - - // Implement axi_arready generation - // axi_arready is asserted for one S_AXI_ACLK clock cycle when - // S_AXI_ARVALID is asserted. axi_awready is - // de-asserted when reset (active low) is asserted. - // The read address is also latched when S_AXI_ARVALID is - // asserted. axi_araddr is reset to zero on reset assertion. - - always @( posedge S_AXI_ACLK ) - begin - if ( S_AXI_ARESETN == 1'b0 ) - begin - axi_arready <= 1'b0; - axi_araddr <= 32'b0; - end - else - begin - if (~axi_arready && S_AXI_ARVALID) - begin - // indicates that the slave has acceped the valid read address - axi_arready <= 1'b1; - // Read address latching - axi_araddr <= S_AXI_ARADDR; - end - else - begin - axi_arready <= 1'b0; - end - end - end - - // Implement axi_arvalid generation - // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both - // S_AXI_ARVALID and axi_arready are asserted. The slave registers - // data are available on the axi_rdata bus at this instance. The - // assertion of axi_rvalid marks the validity of read data on the - // bus and axi_rresp indicates the status of read transaction.axi_rvalid - // is deasserted on reset (active low). axi_rresp and axi_rdata are - // cleared to zero on reset (active low). - always @( posedge S_AXI_ACLK ) - begin - if ( S_AXI_ARESETN == 1'b0 ) - begin - axi_rvalid <= 0; - axi_rresp <= 0; - end - else - begin - if (axi_arready && S_AXI_ARVALID && ~axi_rvalid) - begin - // Valid read data is available at the read data bus - axi_rvalid <= 1'b1; - axi_rresp <= 2'b0; // 'OKAY' response - end - else if (axi_rvalid && S_AXI_RREADY) - begin - // Read data is accepted by the master - axi_rvalid <= 1'b0; - end - end - end - - // Implement memory mapped register select and read logic generation - // Slave register read enable is asserted when valid address is available - // and the slave is ready to accept the read address. - assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid; - always @(*) - begin - // Address decoding for reading registers - case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) - 4'h0 : reg_data_out <= slv_reg0; - 4'h1 : reg_data_out <= slv_reg1; - 4'h2 : reg_data_out <= gpio_in; - 4'h3 : reg_data_out <= slv_reg3; - 4'h4 : reg_data_out <= slv_reg4; - 4'h5 : reg_data_out <= slv_reg5; - 4'h6 : reg_data_out <= slv_reg6; - 4'h7 : reg_data_out <= slv_reg7; - 4'h8 : reg_data_out <= slv_reg8; - 4'h9 : reg_data_out <= slv_reg9; - 4'ha : reg_data_out <= slv_reg10; - 4'hb : reg_data_out <= slv_reg11; - default : reg_data_out <= 0; - endcase - end - - // Output register or memory read data - always @( posedge S_AXI_ACLK ) - begin - if ( S_AXI_ARESETN == 1'b0 ) - begin - axi_rdata <= 0; - end - else - begin - // When there is a valid read address (S_AXI_ARVALID) with - // acceptance of read address by the slave (axi_arready), - // output the read dada - if (slv_reg_rden) - begin - axi_rdata <= reg_data_out; // register read data - end - end - end - - // Add user logic here - assign gpio_out = slv_reg0; - assign pauser = slv_reg3; - - assign cptra_obf_key[31:0] = slv_reg4; - assign cptra_obf_key[63:32] = slv_reg5; - assign cptra_obf_key[95:64] = slv_reg6; - assign cptra_obf_key[127:96] = slv_reg7; - assign cptra_obf_key[159:128] = slv_reg8; - assign cptra_obf_key[191:160] = slv_reg9; - assign cptra_obf_key[223:192] = slv_reg10; - assign cptra_obf_key[255:224] = slv_reg11; - // User logic ends - - endmodule diff --git a/hw-latest/fpga/src/caliptra_soc_1_0/xgui/caliptra_soc_v1_0.tcl b/hw-latest/fpga/src/caliptra_soc_1_0/xgui/caliptra_soc_v1_0.tcl deleted file mode 100644 index 7f70db3589..0000000000 --- a/hw-latest/fpga/src/caliptra_soc_1_0/xgui/caliptra_soc_v1_0.tcl +++ /dev/null @@ -1,60 +0,0 @@ -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox - ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0} - ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0} - ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0} - - -} - -proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { - # Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { - # Procedure called to validate C_S00_AXI_DATA_WIDTH - return true -} - -proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { - # Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { - # Procedure called to validate C_S00_AXI_ADDR_WIDTH - return true -} - -proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { - # Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { - # Procedure called to validate C_S00_AXI_BASEADDR - return true -} - -proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { - # Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { - # Procedure called to validate C_S00_AXI_HIGHADDR - return true -} - - -proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} -} - -proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} -} - diff --git a/hw-latest/fpga/src/soc_adapter.v b/hw-latest/fpga/src/soc_adapter.v new file mode 100644 index 0000000000..ccc3fa880b --- /dev/null +++ b/hw-latest/fpga/src/soc_adapter.v @@ -0,0 +1,97 @@ + +module soc_adapter #(TAGW=16) ( +input aclk, +input rstn, +input arvalid, +output wire arready, +input [31:0] araddr, +input [TAGW-1:0] arid, +input [7:0] arlen, +input [1:0] arburst, +input [2:0] arsize, + +output reg rvalid, +input rready, +output wire [31:0] rdata, +output wire [1:0] rresp, +output reg [TAGW-1:0] rid, +output rlast, + +input awvalid, +output awready, +input [31:0] awaddr, +input [TAGW-1:0] awid, +input [7:0] awlen, +input [1:0] awburst, +input [2:0] awsize, + +input [31:0] wdata, +input [3:0] wstrb, +input wvalid, +output wready, + +output reg bvalid, +input bready, +output wire [1:0] bresp, +output reg [TAGW-1:0] bid, + +// Caliptra SOC signals +input wire [31:0] gpio_in, +output wire [31:0] gpio_out, +output wire [31:0] pauser, +output wire [255:0] cptra_obf_key +); + +reg [7:0] mem [63:0]; +reg [31:0] memdata; + +wire [5:0] awaddr_masked; +assign awaddr_masked = awaddr[5:0]; + +always @ ( posedge aclk) begin + if(!rstn) begin + rvalid <= 0; + bvalid <= 0; + end + else begin + bid <= awid; + rid <= arid; + rvalid <= arvalid; + bvalid <= awvalid; + end + + if(arvalid) memdata <= {mem[araddr+3], mem[araddr+2], mem[araddr+1], mem[araddr]}; + if(awvalid) begin + if (awaddr_masked != 8) begin + if(wstrb[3]) mem[awaddr_masked+3] <= wdata[31:24]; + if(wstrb[2]) mem[awaddr_masked+2] <= wdata[23:16]; + if(wstrb[1]) mem[awaddr_masked+1] <= wdata[15:08]; + if(wstrb[0]) mem[awaddr_masked+0] <= wdata[07:00]; + end + end + + mem[8] <= gpio_in[7:0]; + mem[9] <= gpio_in[15:8]; + mem[10] <= gpio_in[23:16]; + mem[11] <= gpio_in[31:24]; +end + +assign arready = 1'b1; +assign awready = 1'b1; +assign wready = 1'b1; +assign rresp = 2'b0; +assign bresp = 2'b0; +assign rlast = 1'b1; +assign rdata = memdata; + +assign gpio_out = {mem[3], mem[2], mem[1], mem[0]}; +assign pauser = {mem[15], mem[14], mem[13], mem[12]}; + +genvar i; +generate + for (i = 0; i < 32; i = i + 1) begin + assign cptra_obf_key[(i*8)+7:(i*8)] = mem[16 + i]; + end +endgenerate + +endmodule