From e44b6716acda01b85d6a36af20e82a3280191cbb Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 6 Dec 2023 20:05:32 -0800 Subject: [PATCH] Skip internal register hack --- tests/test_setattr_interface.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/test_setattr_interface.py b/tests/test_setattr_interface.py index d892733c..76bba683 100644 --- a/tests/test_setattr_interface.py +++ b/tests/test_setattr_interface.py @@ -65,6 +65,7 @@ def test_tester_magma_internal_signals(target, simulator, capsys): assert expected == actual, "Print of internal register value did not work" +@pytest.mark.skip("Unsupported for MLIR") def test_tester_poke_internal_register(target, simulator, capsys): if target == "python": pytest.skip("Wrapped verilog not supported by Python simulator")