From aba72df69be96dd026cb6b7622d8fa3ddda35b79 Mon Sep 17 00:00:00 2001
From: AllenDBoston <84749409+AllenDBoston@users.noreply.github.com>
Date: Wed, 20 Mar 2024 00:52:20 +0000
Subject: [PATCH] Update README.md

---
 README.md | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index 7cf9ae5..7d6bd68 100644
--- a/README.md
+++ b/README.md
@@ -54,13 +54,13 @@ Testing feature to move the contents of the FPGA core to and output of the PMU s
 ##### JTAG TAP Controller
 The PMU utilizes a JTAG implementation from OpenCores found [here](https://github.com/freecores/jtag) as a template. A new instruction is added to enable and route serial data to the pmu core. 
 
-##### PMU FSM
-
 ##### SHA 256b
-
+[SHA Implementation](https://github.com/secworks/sha256)
 ##### AES 128b
+[AES Implementation](https://github.com/secworks/aes)
 
 ##### 2x2 FPGA (SOFA)
+Generated with [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA)
 
 ###### Note on Key Storage
 Due to the limitations of the skywater130 pdk PMU v3 uses registers to store the AES key. Ideally this key would be stored in a custom 128b ePROM/FLASH write only memory or the another key manage approach would be to utilize a rolling AES key as has been done in Xillinx FPGAs. From a hardware security perspective cipher key storage is considered one of the biggest weaknesses of a system. However, the scope of the project ends at key management techniques as this aspect of the design could be left to another research project.