diff --git a/openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_on_indexed_names/config/module_names.xml b/openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_on_indexed_names/config/module_names.xml
index 0345c12521..96a11c378e 100644
--- a/openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_on_indexed_names/config/module_names.xml
+++ b/openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_on_indexed_names/config/module_names.xml
@@ -1,12 +1,12 @@
 <module_names>
   <module_name default="mux_tree_tapbuf_size10_mem" given="mux_tree_mem_max"/>
-  <module_name default="mux_tree_size_2" given="mux_tree_mini"/>
+  <module_name default="mux_tree_size2" given="mux_tree_mini"/>
   <module_name default="logical_tile_clb_mode_clb_" given="logical_tile_clb_mode_clb_unique"/>
-  <module_name default="sb_1__1_" given="sb_max"/>
-  <module_name default="cby_1__1_" given="cby_max"/>
-  <module_name default="cbx_1__1_" given="cbx_max"/>
-  <module_name default="tile_1__1_" given="tile_clb"/>
-  <module_name default="tile_2__1_" given="tile_dsp"/>
+  <module_name default="sb_4_" given="sb_max"/>
+  <module_name default="cby_1_" given="cby_max"/>
+  <module_name default="cbx_1_" given="cbx_max"/>
+  <module_name default="tile_4_" given="tile_clb"/>
+  <module_name default="tile_7_" given="tile_dsp"/>
   <module_name default="fpga_core" given="pfabric_core"/>
   <module_name default="fpga_top" given="pfabric_top"/>
 </module_names>