diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
index b29ce75d88..d518bc9fce 100644
--- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
+++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
@@ -14,13 +14,13 @@ write_fabric_verilog
 
     Specify the output directory for the Verilog netlists. For example, ``--file /temp/fabric_netlist/``
 
-  .. option:: --constant_undriven_inputs
+  .. option:: --constant_undriven_inputs <string>
 
-  .. note:: This option is automatically enabled when the option ``perimeter_cb`` of tileable routing resource graph is enabled (see details in :ref`addon_vpr_syntax`). 
+  .. note:: This option is automatically enabled and set to ``bus0`` when the option ``perimeter_cb`` of tileable routing resource graph is enabled (see details in :ref`addon_vpr_syntax`). 
 
   .. note:: Enable this option may shadow issues in your FPGA architecture, which causes them difficult to be found in design verification.
    
-    Use constant gnd for undriven wires in Verilog netlists. Recommand to enable when there are boundary routing tracks in FPGA fabric.
+    Can be [``none`` | ``bus0`` | ``bus1`` | ``bit0`` | ``bit1`` ]. Use constant 0 or 1 for undriven wires in Verilog netlists. Recommand to enable when there are boundary routing tracks in FPGA fabric. When ``bus0`` or ``bus1`` are set, the constant wiring will be done in a bus format. When ``bit0`` or ``bit1`` are set, the constant wiring will be done in a bit-blast style. Suggest to use bit-blast style only when downstream Verilog parsers do not support bus format. By default, it is ``none``. 
 
   .. option:: --default_net_type <string>
 
diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h
index 001f7ee403..99376f5fef 100644
--- a/openfpga/src/base/openfpga_verilog_command_template.h
+++ b/openfpga/src/base/openfpga_verilog_command_template.h
@@ -31,10 +31,13 @@ ShellCommandId add_write_fabric_verilog_command_template(
   shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
 
   /* Add an option '--constant_undriven_inputs' */
-  shell_cmd.add_option(
+  CommandOptionId const_undriven_inputs_opt = shell_cmd.add_option(
     "constant_undriven_inputs", false,
-    "Use constant gnd for undriven wires in Verilog netlists. Recommand to "
+    "Can be [none|bus0|bus1|bit0|bit1]. Use constant vdd/gnd for undriven "
+    "wires in Verilog netlists. Recommand to "
     "enable when there are boundary routing tracks in FPGA fabric");
+  shell_cmd.set_option_require_value(const_undriven_inputs_opt,
+                                     openfpga::OPT_STRING);
 
   /* Add an option '--explicit_port_mapping' */
   shell_cmd.add_option("explicit_port_mapping", false,
diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h
index 93dc8035a2..dd024c72ca 100644
--- a/openfpga/src/base/openfpga_verilog_template.h
+++ b/openfpga/src/base/openfpga_verilog_template.h
@@ -58,16 +58,21 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
   }
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
   options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
-  /* For perimeter cb, enable the constant undriven inputs, unless it is off by
-   * user */
-  if (g_vpr_ctx.device().arch->perimeter_cb) {
-    options.set_constant_undriven_inputs(true);
-    VTR_LOG(
-      "Automatically enable the constant_undriven_input option as perimeter "
-      "connection blocks are seen in FPGA fabric\n");
-  } else {
+  /* For perimeter cb, enable the constant-zero undriven inputs, unless it is
+   * defined by user. Throw error if the constant inputs are not selected! */
+  if (cmd_context.option_enable(cmd, opt_constant_undriven_inputs)) {
     options.set_constant_undriven_inputs(
-      cmd_context.option_enable(cmd, opt_constant_undriven_inputs));
+      cmd_context.option_value(cmd, opt_constant_undriven_inputs));
+  }
+  if (g_vpr_ctx.device().arch->perimeter_cb) {
+    if (FabricVerilogOption::e_undriven_input_type::NONE ==
+        options.constant_undriven_inputs()) {
+      options.set_constant_undriven_inputs(
+        FabricVerilogOption::e_undriven_input_type::BUS0);
+      VTR_LOG(
+        "Automatically enable the constant_undriven_input option as perimeter "
+        "connection blocks are seen in FPGA fabric\n");
+    }
   }
 
   return fpga_fabric_verilog(
diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
index 23f6aef12c..0dafb44142 100644
--- a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
@@ -21,7 +21,9 @@ FabricVerilogOption::FabricVerilogOption() {
   default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
   time_stamp_ = true;
   use_relative_path_ = false;
-  constant_undriven_inputs_ = false;
+  constant_undriven_inputs_ = FabricVerilogOption::e_undriven_input_type::NONE;
+  CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_ = {"none", "bus0", "bus1", "bit0",
+                                          "bit1"};
   verbose_output_ = false;
 }
 
@@ -54,10 +56,41 @@ e_verilog_default_net_type FabricVerilogOption::default_net_type() const {
   return default_net_type_;
 }
 
-bool FabricVerilogOption::constant_undriven_inputs() const {
+FabricVerilogOption::e_undriven_input_type
+FabricVerilogOption::constant_undriven_inputs() const {
   return constant_undriven_inputs_;
 }
 
+bool FabricVerilogOption::constant_undriven_inputs_use_bus() const {
+  return constant_undriven_inputs_ ==
+           FabricVerilogOption::e_undriven_input_type::BUS0 ||
+         constant_undriven_inputs_ ==
+           FabricVerilogOption::e_undriven_input_type::BUS1;
+}
+
+size_t FabricVerilogOption::constant_undriven_inputs_value() const {
+  if (constant_undriven_inputs_ ==
+        FabricVerilogOption::e_undriven_input_type::BUS1 ||
+      constant_undriven_inputs_ ==
+        FabricVerilogOption::e_undriven_input_type::BIT1) {
+    return 1;
+  }
+  return 0;
+}
+
+std::string FabricVerilogOption::full_constant_undriven_input_type_str() const {
+  std::string full_type_str("[");
+  for (size_t itype = 0;
+       itype < size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES);
+       ++itype) {
+    full_type_str += std::string(CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_[itype]) +
+                     std::string("|");
+  }
+  full_type_str.pop_back();
+  full_type_str += std::string("]");
+  return full_type_str;
+}
+
 bool FabricVerilogOption::verbose_output() const { return verbose_output_; }
 
 /******************************************************************************
@@ -111,8 +144,31 @@ void FabricVerilogOption::set_default_net_type(
   }
 }
 
-void FabricVerilogOption::set_constant_undriven_inputs(const bool& enabled) {
-  constant_undriven_inputs_ = enabled;
+bool FabricVerilogOption::set_constant_undriven_inputs(
+  const std::string& type_str) {
+  bool valid_type = false;
+  for (size_t itype = 0;
+       itype < size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES);
+       ++itype) {
+    if (std::string(CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_[itype]) == type_str) {
+      constant_undriven_inputs_ =
+        static_cast<FabricVerilogOption::e_undriven_input_type>(itype);
+      valid_type = true;
+      break;
+    }
+  }
+  if (!valid_type) {
+    VTR_LOG_ERROR("Invalid types for undriven inputs: %s. Expect %s\n",
+                  type_str.c_str(),
+                  full_constant_undriven_input_type_str().c_str());
+  }
+  return valid_type;
+}
+
+bool FabricVerilogOption::set_constant_undriven_inputs(
+  const FabricVerilogOption::e_undriven_input_type& type) {
+  constant_undriven_inputs_ = type;
+  return type != FabricVerilogOption::e_undriven_input_type::NUM_TYPES;
 }
 
 void FabricVerilogOption::set_verbose_output(const bool& enabled) {
diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.h b/openfpga/src/fpga_verilog/fabric_verilog_options.h
index c8d5cc5ebf..83483112a6 100644
--- a/openfpga/src/fpga_verilog/fabric_verilog_options.h
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.h
@@ -15,6 +15,16 @@ namespace openfpga {
  * Options for Fabric Verilog generator
  *******************************************************************/
 class FabricVerilogOption {
+ public: /* Types */
+  enum class e_undriven_input_type {
+    NONE = 0, /* Leave undriven input to be dangling */
+    BUS0,     /* Wire to a bus format of constant 0 */
+    BUS1,     /* Wire to a bus format of constant 1 */
+    BIT0,     /* Wire to a blast-bit format of constant 0 */
+    BIT1,     /* Wire to a blast-bit format of constant 1 */
+    NUM_TYPES
+  };
+
  public: /* Public constructor */
   /* Set default options */
   FabricVerilogOption();
@@ -28,7 +38,14 @@ class FabricVerilogOption {
   bool compress_routing() const;
   e_verilog_default_net_type default_net_type() const;
   bool print_user_defined_template() const;
-  bool constant_undriven_inputs() const;
+  e_undriven_input_type constant_undriven_inputs() const;
+  /* Identify if a bus format should be applied when wiring undriven inputs to
+   * constants */
+  bool constant_undriven_inputs_use_bus() const;
+  /* Identify the logic value should be applied when wiring undriven inputs to
+   * constants */
+  size_t constant_undriven_inputs_value() const;
+  std::string full_constant_undriven_input_type_str() const;
   bool verbose_output() const;
 
  public: /* Public mutators */
@@ -40,7 +57,13 @@ class FabricVerilogOption {
   void set_compress_routing(const bool& enabled);
   void set_print_user_defined_template(const bool& enabled);
   void set_default_net_type(const std::string& default_net_type);
-  void set_constant_undriven_inputs(const bool& enabled);
+  /** Decode the type from string to enumeration
+   * "none" -> NONE, "bus0" -> BUS0, "bus1" -> BUS1, "bit0" -> BIT0, "bit1" ->
+   * BIT1 For invalid types, error out
+   */
+  bool set_constant_undriven_inputs(const std::string& type_str);
+  /** For invalid types, error out */
+  bool set_constant_undriven_inputs(const e_undriven_input_type& type);
   void set_verbose_output(const bool& enabled);
 
  private: /* Internal Data */
@@ -52,7 +75,11 @@ class FabricVerilogOption {
   e_verilog_default_net_type default_net_type_;
   bool time_stamp_;
   bool use_relative_path_;
-  bool constant_undriven_inputs_;
+  e_undriven_input_type constant_undriven_inputs_;
+  std::array<const char*,
+             size_t(FabricVerilogOption::e_undriven_input_type::NUM_TYPES)>
+    CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_;  // String versions of constant
+                                           // undriven input types
   bool verbose_output_;
 };
 
diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp
index 4da841564f..f5cc2acf47 100644
--- a/openfpga/src/fpga_verilog/verilog_grid.cpp
+++ b/openfpga/src/fpga_verilog/verilog_grid.cpp
@@ -113,9 +113,10 @@ static void print_verilog_primitive_block(
            module_manager.module_name(primitive_module).c_str());
 
   /* Write the verilog module */
-  write_verilog_module_to_file(fp, module_manager, primitive_module, true,
-                               options.constant_undriven_inputs(),
-                               options.default_net_type());
+  FabricVerilogOption curr_options = options;
+  curr_options.set_explicit_port_mapping(true);
+  write_verilog_module_to_file(fp, module_manager, primitive_module,
+                               curr_options);
 
   /* Close file handler */
   fp.close();
@@ -233,9 +234,7 @@ static void rec_print_verilog_logical_tile(
           std::string(physical_pb_type->name) + " -----"));
 
   /* Write the verilog module */
-  write_verilog_module_to_file(
-    fp, module_manager, pb_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+  write_verilog_module_to_file(fp, module_manager, pb_module, options);
 
   print_verilog_comment(
     fp,
@@ -347,9 +346,7 @@ static void print_verilog_physical_tile_netlist(
   print_verilog_comment(
     fp, std::string("----- BEGIN Grid Verilog module: " +
                     module_manager.module_name(grid_module) + " -----"));
-  write_verilog_module_to_file(
-    fp, module_manager, grid_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+  write_verilog_module_to_file(fp, module_manager, grid_module, options);
 
   print_verilog_comment(
     fp, std::string("----- END Grid Verilog module: " +
diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp
index 45dc0b8628..267ff8f15c 100644
--- a/openfpga/src/fpga_verilog/verilog_lut.cpp
+++ b/openfpga/src/fpga_verilog/verilog_lut.cpp
@@ -59,11 +59,11 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
     ModuleId lut_module = module_manager.find_module(
       module_name_map.name(circuit_lib.model_name(lut_model)));
     VTR_ASSERT(true == module_manager.valid_module_id(lut_module));
-    write_verilog_module_to_file(
-      fp, module_manager, lut_module,
+    FabricVerilogOption curr_options = options;
+    curr_options.set_explicit_port_mapping(
       options.explicit_port_mapping() ||
-        circuit_lib.dump_explicit_port_map(lut_model),
-      options.constant_undriven_inputs(), options.default_net_type());
+      circuit_lib.dump_explicit_port_map(lut_model));
+    write_verilog_module_to_file(fp, module_manager, lut_module, curr_options);
   }
 
   /* Close the file handler */
diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp
index 99557e6b90..d3799264a1 100644
--- a/openfpga/src/fpga_verilog/verilog_memory.cpp
+++ b/openfpga/src/fpga_verilog/verilog_memory.cpp
@@ -57,11 +57,12 @@ static void print_verilog_mux_memory_module(
       ModuleId mem_module = module_manager.find_module(module_name);
       VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
       /* Write the module content in Verilog format */
-      write_verilog_module_to_file(
-        fp, module_manager, mem_module,
+      FabricVerilogOption curr_options = options;
+      curr_options.set_explicit_port_mapping(
         options.explicit_port_mapping() ||
-          circuit_lib.dump_explicit_port_map(mux_model),
-        options.constant_undriven_inputs(), options.default_net_type());
+        circuit_lib.dump_explicit_port_map(mux_model));
+      write_verilog_module_to_file(fp, module_manager, mem_module,
+                                   curr_options);
 
       /* Add an empty line as a splitter */
       fp << std::endl;
@@ -80,11 +81,8 @@ static void print_verilog_mux_memory_module(
       if (module_manager.valid_module_id(feedthru_mem_module)) {
         VTR_ASSERT(true == module_manager.valid_module_id(feedthru_mem_module));
         /* Write the module content in Verilog format */
-        write_verilog_module_to_file(
-          fp, module_manager, feedthru_mem_module,
-          options.explicit_port_mapping() ||
-            circuit_lib.dump_explicit_port_map(mux_model),
-          options.constant_undriven_inputs(), options.default_net_type());
+        write_verilog_module_to_file(fp, module_manager, feedthru_mem_module,
+                                     curr_options);
 
         /* Add an empty line as a splitter */
         fp << std::endl;
@@ -205,11 +203,11 @@ void print_verilog_submodule_memories(
     ModuleId mem_module = module_manager.find_module(module_name);
     VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
     /* Write the module content in Verilog format */
-    write_verilog_module_to_file(fp, module_manager, mem_module,
-                                 options.explicit_port_mapping() ||
-                                   circuit_lib.dump_explicit_port_map(model),
-                                 options.constant_undriven_inputs(),
-                                 options.default_net_type());
+    FabricVerilogOption curr_options = options;
+    curr_options.set_explicit_port_mapping(
+      options.explicit_port_mapping() ||
+      circuit_lib.dump_explicit_port_map(model));
+    write_verilog_module_to_file(fp, module_manager, mem_module, curr_options);
 
     /* Add an empty line as a splitter */
     fp << std::endl;
@@ -227,10 +225,7 @@ void print_verilog_submodule_memories(
     if (module_manager.valid_module_id(feedthru_mem_module)) {
       /* Write the module content in Verilog format */
       write_verilog_module_to_file(fp, module_manager, feedthru_mem_module,
-                                   options.explicit_port_mapping() ||
-                                     circuit_lib.dump_explicit_port_map(model),
-                                   options.constant_undriven_inputs(),
-                                   options.default_net_type());
+                                   curr_options);
 
       /* Add an empty line as a splitter */
       fp << std::endl;
@@ -241,9 +236,7 @@ void print_verilog_submodule_memories(
   for (ModuleId mem_group_module : module_manager.modules_by_usage(
          ModuleManager::e_module_usage_type::MODULE_CONFIG_GROUP)) {
     /* Write the module content in Verilog format */
-    write_verilog_module_to_file(
-      fp, module_manager, mem_group_module, options.explicit_port_mapping(),
-      options.constant_undriven_inputs(), options.default_net_type());
+    write_verilog_module_to_file(fp, module_manager, mem_group_module, options);
 
     /* Add an empty line as a splitter */
     fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
index c99a088c03..72599e4bcc 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
@@ -570,11 +570,10 @@ static void write_verilog_instance_to_file(std::fstream& fp,
  * This is a key function, maybe most frequently called in our Verilog writer
  * Note that file stream must be valid
  *******************************************************************/
-void write_verilog_module_to_file(
-  std::fstream& fp, const ModuleManager& module_manager,
-  const ModuleId& module_id, const bool& use_explicit_port_map,
-  const bool& constant_local_undriven_wires,
-  const e_verilog_default_net_type& default_net_type) {
+void write_verilog_module_to_file(std::fstream& fp,
+                                  const ModuleManager& module_manager,
+                                  const ModuleId& module_id,
+                                  const FabricVerilogOption& options) {
   VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Ensure we have a valid module_id */
@@ -582,7 +581,7 @@ void write_verilog_module_to_file(
 
   /* Print module declaration */
   print_verilog_module_declaration(fp, module_manager, module_id,
-                                   default_net_type);
+                                   options.default_net_type());
 
   /* Print an empty line as splitter */
   fp << std::endl;
@@ -595,7 +594,7 @@ void write_verilog_module_to_file(
     for (const BasicPort& local_wire : port_group.second) {
       /* When default net type is wire, we can skip single-bit wires whose LSB
        * is 0 */
-      if ((VERILOG_DEFAULT_NET_TYPE_WIRE == default_net_type) &&
+      if ((VERILOG_DEFAULT_NET_TYPE_WIRE == options.default_net_type()) &&
           (1 == local_wire.get_width()) && (0 == local_wire.get_lsb())) {
         continue;
       }
@@ -605,7 +604,8 @@ void write_verilog_module_to_file(
   }
 
   /* Use constant to drive undriven local wires */
-  if (constant_local_undriven_wires) {
+  if (options.constant_undriven_inputs() !=
+      FabricVerilogOption::e_undriven_input_type::NONE) {
     std::vector<ModuleManager::e_module_port_type> blacklist = {
       ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT,
       ModuleManager::e_module_port_type::MODULE_GPIN_PORT,
@@ -620,9 +620,17 @@ void write_verilog_module_to_file(
     for (std::pair<std::string, std::vector<BasicPort>> port_group :
          local_undriven_wires) {
       for (const BasicPort& local_undriven_wire : port_group.second) {
-        print_verilog_wire_constant_values(
-          fp, local_undriven_wire,
-          std::vector<size_t>(local_undriven_wire.get_width(), 0));
+        if (options.constant_undriven_inputs_use_bus()) {
+          print_verilog_wire_constant_values(
+            fp, local_undriven_wire,
+            std::vector<size_t>(local_undriven_wire.get_width(),
+                                options.constant_undriven_inputs_value()));
+        } else {
+          print_verilog_wire_constant_values_bit_blast(
+            fp, local_undriven_wire,
+            std::vector<size_t>(local_undriven_wire.get_width(),
+                                options.constant_undriven_inputs_value()));
+        }
       }
     }
   }
@@ -653,7 +661,7 @@ void write_verilog_module_to_file(
       /* Print an instance */
       write_verilog_instance_to_file(fp, module_manager, module_id,
                                      child_module, instance,
-                                     use_explicit_port_map);
+                                     options.explicit_port_mapping());
       /* Print an empty line as splitter */
       fp << std::endl;
     }
@@ -661,7 +669,7 @@ void write_verilog_module_to_file(
 
   /* Print an end for the module */
   print_verilog_module_end(fp, module_manager.module_name(module_id),
-                           default_net_type);
+                           options.default_net_type());
 
   /* Print an empty line as splitter */
   fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.h b/openfpga/src/fpga_verilog/verilog_module_writer.h
index 0657c3985d..3c4c024e55 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.h
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.h
@@ -6,6 +6,7 @@
  *******************************************************************/
 #include <fstream>
 
+#include "fabric_verilog_options.h"
 #include "module_manager.h"
 #include "verilog_port_types.h"
 
@@ -16,11 +17,10 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void write_verilog_module_to_file(
-  std::fstream& fp, const ModuleManager& module_manager,
-  const ModuleId& module_id, const bool& use_explicit_port_map,
-  const bool& constant_local_undriven_wires,
-  const e_verilog_default_net_type& default_net_type);
+void write_verilog_module_to_file(std::fstream& fp,
+                                  const ModuleManager& module_manager,
+                                  const ModuleId& module_id,
+                                  const FabricVerilogOption& options);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp
index 6f7a2a2820..d4844b0800 100644
--- a/openfpga/src/fpga_verilog/verilog_mux.cpp
+++ b/openfpga/src/fpga_verilog/verilog_mux.cpp
@@ -643,8 +643,7 @@ static void generate_verilog_rram_mux_branch_module(
 static void generate_verilog_mux_branch_module(
   ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
   std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph,
-  const ModuleNameMap& module_name_map, const bool& use_explicit_port_map,
-  const e_verilog_default_net_type& default_net_type,
+  const ModuleNameMap& module_name_map, const FabricVerilogOption& options,
   std::map<std::string, bool>& branch_mux_module_is_outputted) {
   std::string module_name = generate_mux_branch_subckt_name(
     circuit_lib, mux_model, mux_graph.num_inputs(), mux_graph.num_memory_bits(),
@@ -675,24 +674,28 @@ static void generate_verilog_mux_branch_module(
         /* Structural verilog can be easily generated by module writer */
         ModuleId mux_module = module_manager.find_module(module_name);
         VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
-        write_verilog_module_to_file(
-          fp, module_manager, mux_module,
-          use_explicit_port_map ||
-            circuit_lib.dump_explicit_port_map(mux_model),
-          false, default_net_type);
+        FabricVerilogOption curr_options = options;
+        curr_options.set_explicit_port_mapping(
+          curr_options.explicit_port_mapping() ||
+          circuit_lib.dump_explicit_port_map(mux_model));
+        curr_options.set_constant_undriven_inputs(
+          FabricVerilogOption::e_undriven_input_type::NONE);
+        write_verilog_module_to_file(fp, module_manager, mux_module,
+                                     curr_options);
         /* Add an empty line as a splitter */
         fp << std::endl;
       } else {
         /* Behavioral verilog requires customized generation */
         print_verilog_cmos_mux_branch_module_behavioral(
           module_manager, circuit_lib, fp, mux_model, module_name, mux_graph,
-          default_net_type);
+          options.default_net_type());
       }
       break;
     case CIRCUIT_MODEL_DESIGN_RRAM:
       generate_verilog_rram_mux_branch_module(
         module_manager, circuit_lib, fp, mux_model, module_name, mux_graph,
-        default_net_type, circuit_lib.dump_structural_verilog(mux_model));
+        options.default_net_type(),
+        circuit_lib.dump_structural_verilog(mux_model));
       break;
     default:
       VTR_LOGF_ERROR(__FILE__, __LINE__,
@@ -1401,8 +1404,7 @@ static void generate_verilog_rram_mux_module(
 static void generate_verilog_mux_module(
   ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
   std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph,
-  const ModuleNameMap& module_name_map, const bool& use_explicit_port_map,
-  const e_verilog_default_net_type& default_net_type) {
+  const ModuleNameMap& module_name_map, const FabricVerilogOption& options) {
   std::string module_name =
     generate_mux_subckt_name(circuit_lib, mux_model,
                              find_mux_num_datapath_inputs(
@@ -1417,13 +1419,16 @@ static void generate_verilog_mux_module(
       /* Use Verilog writer to print the module to file */
       ModuleId mux_module = module_manager.find_module(module_name);
       VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
-      write_verilog_module_to_file(
-        fp, module_manager, mux_module,
-        (use_explicit_port_map ||
+      FabricVerilogOption curr_options = options;
+      curr_options.set_explicit_port_mapping(
+        (curr_options.explicit_port_mapping() ||
          circuit_lib.dump_explicit_port_map(mux_model) ||
          circuit_lib.dump_explicit_port_map(
-           circuit_lib.pass_gate_logic_model(mux_model))),
-        false, default_net_type);
+           circuit_lib.pass_gate_logic_model(mux_model))));
+      curr_options.set_constant_undriven_inputs(
+        FabricVerilogOption::e_undriven_input_type::NONE);
+      write_verilog_module_to_file(fp, module_manager, mux_module,
+                                   curr_options);
       /* Add an empty line as a splitter */
       fp << std::endl;
       break;
@@ -1432,7 +1437,7 @@ static void generate_verilog_mux_module(
       /* TODO: RRAM-based Multiplexer Verilog module generation */
       generate_verilog_rram_mux_module(module_manager, circuit_lib, fp,
                                        mux_model, module_name, mux_graph,
-                                       default_net_type);
+                                       options.default_net_type());
       break;
     default:
       VTR_LOGF_ERROR(__FILE__, __LINE__,
@@ -1486,8 +1491,7 @@ static void print_verilog_submodule_mux_primitives(
     for (auto branch_mux_graph : branch_mux_graphs) {
       generate_verilog_mux_branch_module(
         module_manager, circuit_lib, fp, mux_circuit_model, branch_mux_graph,
-        module_name_map, options.explicit_port_mapping(),
-        options.default_net_type(), branch_mux_module_is_outputted);
+        module_name_map, options, branch_mux_module_is_outputted);
     }
   }
 
@@ -1540,8 +1544,7 @@ static void print_verilog_submodule_mux_top_modules(
     /* Create MUX circuits */
     generate_verilog_mux_module(module_manager, circuit_lib, fp,
                                 mux_circuit_model, mux_graph, module_name_map,
-                                options.explicit_port_mapping(),
-                                options.default_net_type());
+                                options);
   }
 
   /* Close the file stream */
diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp
index 00bcaeda50..f346b70874 100644
--- a/openfpga/src/fpga_verilog/verilog_routing.cpp
+++ b/openfpga/src/fpga_verilog/verilog_routing.cpp
@@ -115,9 +115,7 @@ static void print_verilog_routing_connection_box_unique_module(
   VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
 
   /* Write the verilog module */
-  write_verilog_module_to_file(
-    fp, module_manager, cb_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+  write_verilog_module_to_file(fp, module_manager, cb_module, options);
 
   /* Add an empty line as a splitter */
   fp << std::endl;
@@ -236,9 +234,7 @@ static void print_verilog_routing_switch_box_unique_module(
   VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
 
   /* Write the verilog module */
-  write_verilog_module_to_file(
-    fp, module_manager, sb_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+  write_verilog_module_to_file(fp, module_manager, sb_module, options);
 
   /* Close file handler */
   fp.close();
diff --git a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
index 6f548d8ec2..67ccdb4afa 100644
--- a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
+++ b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
@@ -56,9 +56,7 @@ void print_verilog_submodule_shift_register_banks(
   for (const ModuleId& sr_module : blwl_sr_banks.bl_bank_unique_modules()) {
     VTR_ASSERT(true == module_manager.valid_module_id(sr_module));
     /* Write the module content in Verilog format */
-    write_verilog_module_to_file(
-      fp, module_manager, sr_module, options.explicit_port_mapping(),
-      options.constant_undriven_inputs(), options.default_net_type());
+    write_verilog_module_to_file(fp, module_manager, sr_module, options);
 
     /* Add an empty line as a splitter */
     fp << std::endl;
@@ -67,9 +65,7 @@ void print_verilog_submodule_shift_register_banks(
   for (const ModuleId& sr_module : blwl_sr_banks.wl_bank_unique_modules()) {
     VTR_ASSERT(true == module_manager.valid_module_id(sr_module));
     /* Write the module content in Verilog format */
-    write_verilog_module_to_file(
-      fp, module_manager, sr_module, options.explicit_port_mapping(),
-      options.constant_undriven_inputs(), options.default_net_type());
+    write_verilog_module_to_file(fp, module_manager, sr_module, options);
 
     /* Add an empty line as a splitter */
     fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_tile.cpp b/openfpga/src/fpga_verilog/verilog_tile.cpp
index a3bb1e992f..9de47fe16f 100644
--- a/openfpga/src/fpga_verilog/verilog_tile.cpp
+++ b/openfpga/src/fpga_verilog/verilog_tile.cpp
@@ -58,9 +58,7 @@ static int print_verilog_tile_module_netlist(
                             options.time_stamp());
 
   /* Write the module content in Verilog format */
-  write_verilog_module_to_file(
-    fp, module_manager, tile_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+  write_verilog_module_to_file(fp, module_manager, tile_module, options);
 
   /* Add an empty line as a splitter */
   fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp
index 26268e4c16..9812e9db51 100644
--- a/openfpga/src/fpga_verilog/verilog_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp
@@ -61,9 +61,7 @@ void print_verilog_core_module(NetlistManager& netlist_manager,
                             options.time_stamp());
 
   /* Write the module content in Verilog format */
-  write_verilog_module_to_file(
-    fp, module_manager, core_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+  write_verilog_module_to_file(fp, module_manager, core_module, options);
 
   /* Add an empty line as a splitter */
   fp << std::endl;
@@ -127,9 +125,7 @@ void print_verilog_top_module(NetlistManager& netlist_manager,
     fp, std::string("Top-level Verilog module for FPGA"), options.time_stamp());
 
   /* Write the module content in Verilog format */
-  write_verilog_module_to_file(
-    fp, module_manager, top_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+  write_verilog_module_to_file(fp, module_manager, top_module, options);
 
   /* Add an empty line as a splitter */
   fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
index dd95205de4..2dab191cd9 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -831,6 +831,24 @@ void print_verilog_wire_constant_values(
   fp << ";" << std::endl;
 }
 
+/********************************************************************
+ * Generate a wire connection, that assigns constant values to a
+ * Verilog port
+ *******************************************************************/
+void print_verilog_wire_constant_values_bit_blast(
+  std::fstream& fp, const BasicPort& output_port,
+  const std::vector<size_t>& const_values) {
+  /* Make sure we have a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  for (size_t ipin : output_port.pins()) {
+    BasicPort curr_pin(output_port.get_name(), ipin, ipin);
+    print_verilog_wire_constant_values(
+      fp, curr_pin,
+      std::vector<size_t>(curr_pin.get_width(), const_values[ipin]));
+  }
+}
+
 /********************************************************************
  * Deposit constant values to a Verilog port
  *******************************************************************/
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h
index 665f191a2d..cffd10425b 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h
@@ -123,6 +123,10 @@ void print_verilog_wire_constant_values(
   std::fstream& fp, const BasicPort& output_port,
   const std::vector<size_t>& const_values);
 
+void print_verilog_wire_constant_values_bit_blast(
+  std::fstream& fp, const BasicPort& output_port,
+  const std::vector<size_t>& const_values);
+
 void print_verilog_deposit_wire_constant_values(
   std::fstream& fp, const BasicPort& output_port,
   const std::vector<size_t>& const_values);
diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga
new file mode 100644
index 0000000000..ff7fd19d22
--- /dev/null
+++ b/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga
@@ -0,0 +1,73 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --constant_undriven_inputs ${OPENFPGA_VERILOG_UNDRIVEN_INPUT_TYPE} --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  --explicit_port_mapping
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping 
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
index c716757ab6..7f418b15d9 100755
--- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
+++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
@@ -117,6 +117,13 @@ run-task fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_w
 echo -e "Testing explicit Verilog generation";
 run-task fpga_verilog/verilog_netlist_formats/explicit_port_mapping_default_nettype_wire $@
 
+echo -e "Testing undriven net wiring in Verilog generation";
+run-task fpga_verilog/verilog_netlist_formats/undriven_input_none $@
+run-task fpga_verilog/verilog_netlist_formats/undriven_input_bus0 $@
+run-task fpga_verilog/verilog_netlist_formats/undriven_input_bus1 $@
+run-task fpga_verilog/verilog_netlist_formats/undriven_input_bit0 $@
+run-task fpga_verilog/verilog_netlist_formats/undriven_input_bit1 $@
+
 echo -e "Testing Verilog generation with flatten routing modules";
 run-task fpga_verilog/flatten_routing $@
 
diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit0/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit0/config/task.conf
new file mode 100644
index 0000000000..461859af6e
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit0/config/task.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=3x3
+openfpga_verilog_undriven_input_type=bit0
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit1/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit1/config/task.conf
new file mode 100644
index 0000000000..ade3f8a34f
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bit1/config/task.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=3x3
+openfpga_verilog_undriven_input_type=bit1
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus0/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus0/config/task.conf
new file mode 100644
index 0000000000..078590872a
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus0/config/task.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=3x3
+openfpga_verilog_undriven_input_type=bus0
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus1/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus1/config/task.conf
new file mode 100644
index 0000000000..310cf2adcc
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_bus1/config/task.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=3x3
+openfpga_verilog_undriven_input_type=bus1
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none/config/task.conf
new file mode 100644
index 0000000000..b44946e4bf
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none/config/task.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=3x3
+openfpga_verilog_undriven_input_type=none
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none_force/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none_force/config/task.conf
new file mode 100644
index 0000000000..b0246bb330
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/undriven_input_none_force/config/task.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_const_undriven_net_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=3x3
+openfpga_verilog_undriven_input_type=none
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=