From 517be141ba6d7746e3cea5c4fd0624debcc16f37 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 26 Sep 2023 18:37:49 -0700 Subject: [PATCH] [doc] format --- docs/source/manual/arch_lang/annotate_vpr_arch.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/source/manual/arch_lang/annotate_vpr_arch.rst b/docs/source/manual/arch_lang/annotate_vpr_arch.rst index a12e49556c..9fd1024a79 100644 --- a/docs/source/manual/arch_lang/annotate_vpr_arch.rst +++ b/docs/source/manual/arch_lang/annotate_vpr_arch.rst @@ -85,7 +85,7 @@ For subtile port merge support (see an illustrative example in :numref:`fig_subt .. _fig_subtile_port_merge: .. figure:: ./figures/subtile_port_merge.png - :scale: 100% + :width: 100% :alt: Difference in netlists with and without subtile port merging Difference in netlists with and without subtile port merging @@ -136,7 +136,7 @@ A more illustrative example: .. _fig_global_tile_ports: .. figure:: ./figures/global_tile_ports.png - :scale: 100% + :width: 100% :alt: Difference between global port definition through circuit model and tile annotation Difference between global port definition through circuit model and tile annotation